View 82801FR_971391.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel ? i/o controller hub 6 (ich6) family datasheet for the intel ? 82801fb ich6, 82801FR ic h6r and 82801fbm ich6-m i/o controller hubs january 2005 document number: 301473-002
2 intel ? i/o controller hub 6 (ich 6) family datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended fo r use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? 82801fb ich6, intel ? 82801FR ich6r, and intel ? 82801fbm ich6-m components may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current charac terized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. alert on lan is a result of the intel-ibm advanced manageability alliance and a trademark of ibm. intel, intel speedstep and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in t he united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2004-2005, intel corporation
intel ? i/o controller hub 6 (ich6) family datasheet 3 contents contents 1 introduction ............................................................................................................................. 43 1.2 overview.................................................................................................................... ......... 46 2 signal description ................................................................................................................. 53 2.1 direct media interface (dmi) to host contro ller.................................................................. 56 2.2 pci express* ................................................................................................................ ...... 56 2.3 link to lan connect ......................................................................................................... ..57 2.4 eeprom interface ... ................ ................ ................ ................ ................ ............. ............ .57 2.5 firmware hub interface ...................................................................................................... 57 2.6 pci interface ............................................................................................................... ........ 58 2.7 serial ata interface........................................................................................................ .... 60 2.8 ide interface ............................................................................................................... ........ 61 2.9 lpc interface............................................................................................................... ....... 62 2.10 interrupt interface ........................................................................................................ ....... 63 2.11 usb interface .............................................................................................................. ....... 64 2.12 power management interface ............................................................................................. 65 2.13 processor interface........................................................................................................ ..... 67 2.14 smbus interface ............................................................................................................ ..... 68 2.15 system management interface........................................................................................... 68 2.16 real time clock interface . ................................................................................................. 69 2.17 other clocks ............................................................................................................... ........ 69 2.18 miscellaneous signals ...................................................................................................... .. 69 2.19 ac ?97/intel ? high definition audio link ............................................................................. 70 2.20 general purpose i/o ........................................................................................................ ...71 2.21 power and ground........................................................................................................... ... 73 2.22 pin straps ................................................................................................................. .......... 74 2.22.1 functional straps ................................................................................................... 74 2.22.2 external rtc circuitry ........................................................................................... 76 2.22.3 power sequencing requirements ......................................................................... 76 2.22.3.1 v5ref / vcc3_3 sequencing requ irements ......................................... 76 2.22.3.2 3.3 v/1.5 v standby power seque ncing requirements ........................ 76 2.22.3.3 3.3 v/2.5 v power sequencing requirements....................................... 77 2.22.3.4 vcc1_5/v_process or_io power sequencing re quirements ................. 77 3 pin states ............................................................................................................................... ... 79 3.1 integrated pull-ups and pull-downs ................................................................................... 79 3.2 ide integrated series termination resistor s ..................................................................... 80 3.3 output and i/o signals planes and states ......................................................................... 80 3.4 power planes for input signals........................................................................................... 89 4 system clock domains ....................................................................................................... 95 5 functional description ........................................................................................................ 97 5.1 pci-to-pci bridge (d30:f0) ................................................................................................ 97 5.1.1 pci bus interface................................................................................................... 97 5.1.2 pci bridge as an initiator ...................................................................................... 97 5.1.2.1 memory reads and writes .................................................................... 98
4 intel ? i/o controller hub 6 (ich 6) family datasheet contents 5.1.2.2 i/o reads and writes............................................................................. 98 5.1.2.3 configuration reads and writes .. .......................................................... 98 5.1.2.4 locked cycles........................................................................................ 98 5.1.2.5 target / master aborts ........................................................................... 98 5.1.2.6 secondary master latency timer .......................................................... 98 5.1.2.7 dual address cycle (dac) .................................................................... 98 5.1.2.8 memory and i/o decode to pci............................................................. 99 5.1.3 parity error detection and generation................................................................... 99 5.1.4 pcirst#.............................................................................................................. 100 5.1.5 peer cycles ......................................................................................................... 100 5.1.6 pci-to-pci bridge model ..................................................................................... 100 5.1.7 idsel to device number mapping...................................................................... 100 5.1.8 standard pci bus configuration mechani sm ...................................................... 100 5.2 pci express* root ports (d28:f0,f1,f2,f3).................................................................... 101 5.2.1 interrupt generation............................................................................................. 101 5.2.2 power management............................................................................................. 102 5.2.2.1 s3/s4/s5 support ................................................................................ 102 5.2.2.2 resuming from suspended state ........................................................ 102 5.2.2.3 device initiated pm_pme message..................................................... 102 5.2.2.4 smi/sci generation............................................................................. 103 5.2.3 serr# generation .............................................................................................. 103 5.2.4 hot-plug............................................................................................................... 103 5.2.4.1 presence detection.............................................................................. 103 5.2.4.2 message generation............................................................................ 104 5.2.4.3 attention button detection ................................................................... 104 5.2.4.4 smi/sci generation............................................................................. 105 5.3 lan controller (b1:d8:f0)................................................................................................ 105 5.3.1 lan controller pci bus interface ........................................................................ 106 5.3.1.1 bus slave operation ............................................................................ 106 5.3.1.2 clkrun# signal (mobile only)........................................................... 107 5.3.1.3 pci power management...................................................................... 107 5.3.1.4 pci reset signal.................................................................................. 108 5.3.1.5 wake-up events .................................................................................. 108 5.3.1.6 wake on lan* (preboot wake-up) ..................................................... 109 5.3.2 serial eeprom interface . .............. ................ ................ ................ ............. ........ 109 5.3.3 csma/cd unit..................................................................................................... 110 5.3.3.1 full duplex ........................................................................................... 110 5.3.3.2 flow control......................................................................................... 111 5.3.3.3 vlan support ...................................................................................... 111 5.3.4 media management interface .............................................................................. 111 5.3.5 tco functionality ................................................................................................ 111 5.3.5.1 advanced tco mode .......................................................................... 111 5.4 alert standard format (asf) ............................................................................................ 113 5.4.1 asf management solution features/capabilities ............................................... 114 5.4.2 asf hardware support... ..................................................................................... 115 5.4.2.1 82562em/ex........................................................................................ 115 5.4.2.2 eeprom (256x16, 1 mhz)............. ................ ................ ............. ........ 115 5.4.2.3 legacy sensor smbus devices........................................................... 115 5.4.2.4 remote control smbus devices ......................................................... 115 5.4.2.5 asf sensor smbus devices ....... ........................................................ 115 5.4.3 asf software support ......................................................................................... 115 5.5 lpc bridge (w/ system an d management functions) (d31:f0)....................................... 116
intel ? i/o controller hub 6 (ich6) family datasheet 5 contents 5.5.1 lpc interface .......................................................................................................116 5.5.1.1 lpc cycle types .................................................................................117 5.5.1.2 start field definition.............................................................................117 5.5.1.3 cycle type / direction (cyctype + dir) .......... ............. ............ ........118 5.5.1.4 size .....................................................................................................118 5.5.1.5 sync ...................................................................................................119 5.5.1.6 sync time-out ...................................................................................119 5.5.1.7 sync error indication..........................................................................119 5.5.1.8 lframe# usage .................................................................................119 5.5.1.9 i/o cycles ............................................................................................120 5.5.1.10 bus master cycles ...............................................................................120 5.5.1.11 lpc power management .....................................................................120 5.5.1.12 configuration and intel ? ich6 implications..........................................120 5.6 dma operation (d31:f0) ..................................................................................................121 5.6.1 channel priority ...................................................................................................122 5.6.1.1 fixed priority ........................................................................................122 5.6.1.2 rotating priority ...................................................................................122 5.6.2 address compatibility mode ................................................................................122 5.6.3 summary of dma transfer sizes ........................................................................123 5.6.3.1 address shifting when programmed for 16-bit i/o count by words .............................................................................123 5.6.4 autoinitialize.........................................................................................................123 5.6.5 software commands ...........................................................................................124 5.7 lpc dma..................................................................................................................... .....124 5.7.1 asserting dma requests.....................................................................................124 5.7.2 abandoning dma requests ................................................................................125 5.7.3 general flow of dma transfers ............ ..............................................................125 5.7.4 terminal count ....................................................................................................126 5.7.5 verify mode..........................................................................................................126 5.7.6 dma request de-assertion .................................................................................126 5.7.7 sync field / ldrq# rules .................................................................................127 5.8 8254 timers (d31:f0).......................................................................................................1 28 5.8.1 timer programming .............................................................................................128 5.8.2 reading from the interval timer ..........................................................................129 5.8.2.1 simple read ........................................................................................130 5.8.2.2 counter latch command .....................................................................130 5.8.2.3 read back command ..........................................................................130 5.9 8259 interrupt controllers (pic) (d31:f0) ........................................................................131 5.9.1 interrupt handling ................................................................................................132 5.9.1.1 generating interrupts ...........................................................................132 5.9.1.2 acknowledging interr upts.....................................................................132 5.9.1.3 hardware/software interrupt sequence ...............................................133 5.9.2 initialization command words (icwx) .................................................................133 5.9.2.1 icw1 ....................................................................................................133 5.9.2.2 icw2 ....................................................................................................134 5.9.2.3 icw3 ....................................................................................................134 5.9.2.4 icw4 ....................................................................................................134 5.9.3 operation command words (ocw) ....................................................................134 5.9.4 modes of operation .............................................................................................134 5.9.4.1 fully nested mode ...............................................................................134 5.9.4.2 special fully-nested mode ..................................................................135 5.9.4.3 automatic rotation mode (equal pr iority devices) ..............................135
6 intel ? i/o controller hub 6 (ich 6) family datasheet contents 5.9.4.4 specific rotation mode (specific priority)............................................ 135 5.9.4.5 poll mode ............................................................................................. 135 5.9.4.6 cascade mode..................................................................................... 136 5.9.4.7 edge and level triggered mode.......................................................... 136 5.9.4.8 end of interrupt (eoi) operatio ns ........................................................ 136 5.9.4.9 normal end of interr upt........................................................................ 136 5.9.4.10 automatic end of in terrupt mode ......................................................... 136 5.9.5 masking interrupts .......... ..................................................................................... 137 5.9.5.1 masking on an individual interrupt request......................................... 137 5.9.5.2 special mask mode.............................................................................. 137 5.9.6 steering pci interrupts ........................................................................................ 137 5.10 advanced programmable interrupt controller (apic) (d31:f0)................................................................................................................ 138 5.10.1 interrupt handling ................................................................................................ 138 5.10.2 interrupt mapping................................................................................................. 138 5.10.3 pci / pci express* message-based inte rrupts ................................................... 139 5.10.4 front side bus interrupt delivery......................................................................... 139 5.10.4.1 edge-triggered operation ................................................................... 140 5.10.4.2 level-triggered operation ................................................................... 140 5.10.4.3 registers associated with front side bus interrupt delivery.......... ........................................................................ 140 5.10.4.4 interrupt message format.................................................................... 140 5.11 serial interrupt (d31:f0) .................................................................................................. .141 5.11.1 start frame.......................................................................................................... 142 5.11.2 data frames ........................................................................................................ 142 5.11.3 stop frame .......................................................................................................... 142 5.11.4 specific interrupts no t supported via serirq ................................................... 143 5.11.5 data frame format ............................................................................................. 143 5.12 real time clock (d31:f0) ................................................................................................ 144 5.12.1 update cycles ..................................................................................................... 144 5.12.2 interrupts.............................................................................................................. 1 45 5.12.3 lockable ram ranges ........................................................................................ 145 5.12.4 century rollover .................................................................................................. 145 5.12.5 clearing battery-backed rtc ram .................................................................... 145 5.13 processor interface (d31:f0) ...................... ..................................................................... 147 5.13.1 processor interface signals................................................................................. 147 5.13.1.1 a20m# (mask a20) .............................................................................. 147 5.13.1.2 init# (initialization) .............................................................................. 147 5.13.1.3 ferr#/ignne# (numeric coprocessor error / ignore numeric error) .......................................................................... 148 5.13.1.4 nmi (non-maskable interrupt) ............................................................. 149 5.13.1.5 stop clock request and processor sleep (stpclk# and cpuslp#) .................................................................. 149 5.13.1.6 processor power good (cpupw rgood) ......................................... 149 5.13.1.7 deeper sleep (dpslp#) (mobile only) ............................................... 149 5.13.2 dual-processor issues (desktop only). ............................................................... 149 5.13.2.1 signal differences................................................................................ 149 5.13.2.2 power management............................................................................. 150 5.14 power management (d31:f0) .......................................................................................... 150 5.14.1 features............................................................................................................... 15 0 5.14.2 intel ? ich6 and system power states ................................................................ 151 5.14.3 system power planes.......................................................................................... 153
intel ? i/o controller hub 6 (ich6) family datasheet 7 contents 5.14.4 smi#/sci generation............................. ..............................................................153 5.14.4.1 pci express* sci.................................................................................155 5.14.4.2 pci express* hot-pl ug.........................................................................155 5.14.5 dynamic processor clock control ......... ..............................................................156 5.14.5.1 transition rules among s0/cx and throttling states ..........................157 5.14.5.2 deferred c3/c4 (mobile only) .. ...........................................................157 5.14.5.3 popup (auto c3/c4 to c2) (mobile only) ..........................................158 5.14.5.4 popdown (auto c2 to c3/c4) (m obile only) ....................................158 5.14.6 dynamic pci clock contro l (mobile only) ...........................................................158 5.14.6.1 conditions for checking the pc i clock ................................................158 5.14.6.2 conditions for maintaining the pci clock ............................................159 5.14.6.3 conditions for stopping the pci clock.................................................159 5.14.6.4 conditions for re-starting the pci clock.............................................159 5.14.6.5 lpc devices and clkrun# ...............................................................159 5.14.7 sleep states ........................................................................................................160 5.14.7.1 sleep state overview ..........................................................................160 5.14.7.2 initiating sleep state ............................................................................160 5.14.7.3 exiting sleep states.............................................................................160 5.14.7.4 pci express* wake # signal and pme event message .....................162 5.14.7.5 sx-g3-sx, ha ndling power failures ............ ........................................162 5.14.8 thermal management..........................................................................................163 5.14.8.1 thrm# signal......................................................................................163 5.14.8.2 processor initiated passive coo ling ....................................................163 5.14.8.3 thrm# override software bit .. ...........................................................163 5.14.8.4 active cooling ........................... ...........................................................163 5.14.9 event input signals and their usage ..................................................................164 5.14.9.1 pwrbtn# (power bu tton) ..................................................................164 5.14.9.2 ri# (ring indicator) ..............................................................................165 5.14.9.3 pme# (pci power management ev ent) ..............................................165 5.14.9.4 sys_reset# signal ...........................................................................165 5.14.9.5 thrmtrip# signal .............................................................................166 5.14.9.6 bmbusy# (mob ile only) .....................................................................166 5.14.10 alt access mode................................................................................................167 5.14.10.1 write only registers with read paths in alt access mode ...............168 5.14.10.2 pic reserved bits................................................................................169 5.14.10.3 read only registers with write paths in alt access mode ...............170 5.14.11 system power supplies, planes, and si gnals .....................................................170 5.14.11.1 power plane control with slp_ s3#, slp_s4# and slp_s5# ............170 5.14.11.2 slp_s4# and suspend-to-ram sequencing .....................................171 5.14.11.3 pwrok signal ....................................................................................171 5.14.11.4 cpupwrgd signal.............................................................................171 5.14.11.5 vrmpwrgd signal ............................................................................171 5.14.11.6 batlow# (battery low) (mobile only) ...............................................171 5.14.11.7 controllin g leakage and power consumption during low-power states ....................................................................172 5.14.12 clock generators .................................................................................................172 5.14.12.1 clock control signals from intel ? ich6 to clock synthesizer (mobile only) ....................................................................173 5.14.13 legacy power management theory of operation ...............................................173 5.14.13.1 apm power management (desktop only) ...........................................173 5.14.13.2 mobile apm power management (mobile only) ..................................173 5.15 system management (d31:f0).........................................................................................174 5.15.1 theory of operation .............................................................................................174
8 intel ? i/o controller hub 6 (ich 6) family datasheet contents 5.15.1.1 detecting a system lockup ................................................................. 174 5.15.1.2 handling an intruder .................... ........................................................ 174 5.15.1.3 detecting im proper firmware hub programming ................................ 175 5.15.2 heartbeat and event reporting via sm bus ......................................................... 175 5.16 ide controller (d31:f1) .................................................................................................... 179 5.16.1 pio transfers ...................................................................................................... 179 5.16.1.1 pio ide timing modes ........................................................................ 179 5.16.1.2 iordy masking ................................................................................... 180 5.16.1.3 pio 32-bit ide data port acce sses..................................................... 180 5.16.1.4 pio ide data port prefetching and posting ........................................ 180 5.16.2 bus master function............................................................................................ 181 5.16.2.1 physical region descriptor format ..................................................... 181 5.16.2.2 bus master ide timings ...................................................................... 182 5.16.2.3 interrupts.............................................................................................. 182 5.16.2.4 bus master ide operation ................................................................... 182 5.16.2.5 error conditions ................................................................................... 183 5.16.3 ultra ata/100/66/33 protocol .............................................................................. 184 5.16.3.1 operation ............................................................................................. 184 5.16.4 ultra ata/33/66/100 timing ................................................................................ 185 5.16.5 ata swap bay..................................................................................................... 185 5.16.6 smi trapping ....................................................................................................... 185 5.17 sata host controller (d31:f2) ...................... .................................................................. 186 5.17.1 theory of operation............................................................................................. 186 5.17.1.1 standard ata emulation ..................................................................... 186 5.17.1.2 48-bit lba operation ........................................................................... 187 5.17.2 sata swap bay support..................................................................................... 187 5.17.3 intel ? matrix storage technology configuration (ich6r only) ........................... 187 5.17.3.1 intel ? application accelerator raid option rom................................ 187 5.17.4 power management operation............................................................................ 188 5.17.4.1 power state mappings......................................................................... 188 5.17.4.2 power state transitions....................................................................... 189 5.17.4.3 smi trapping (apm) ............................................................................ 190 5.17.5 sata led ........................................................................................................... 190 5.17.6 ahci operation ................................................................................................... 190 5.18 high precision event timers ............................................................................................ 191 5.18.1 timer accuracy.................................................................................................... 191 5.18.2 interrupt mapping................................................................................................. 191 5.18.3 periodic vs. non-periodic modes......................................................................... 192 5.18.4 enabling the timers............................................................................................. 192 5.18.5 interrupt levels .................................................................................................... 193 5.18.6 handling interrupts .............................................................................................. 193 5.18.7 issues related to 64-bit timers with 32-bit processors...................................... 193 5.19 usb uhci host controllers (d29:f0, f1, f2, and f3) .......... ........................................... 194 5.19.1 data structures in main memory ....... .................................................................. 194 5.19.2 data transfers to/from main memory ... ............................................................... 194 5.19.3 data encoding and bit stuffing............................................................................ 194 5.19.4 bus protocol ........................................................................................................ 194 5.19.4.1 bit ordering.......................................................................................... 194 5.19.4.2 sync field .......................................................................................... 194 5.19.4.3 packet field formats ........................................................................... 195 5.19.4.4 address fields ..................................................................................... 195
intel ? i/o controller hub 6 (ich6) family datasheet 9 contents 5.19.4.5 frame number field ............................................................................195 5.19.4.6 data field.............................................................................................195 5.19.4.7 cyclic redundancy check (crc) ........................................................195 5.19.5 packet formats............... .....................................................................................195 5.19.6 usb interrupts .....................................................................................................195 5.19.6.1 transaction-based interrupts...............................................................196 5.19.6.2 non-transaction based interrupts .......................................................198 5.19.7 usb power management ....................................................................................198 5.19.8 usb legacy keyboard op eration........................................................................199 5.20 usb ehci host controller (d29:f7)............ .....................................................................201 5.20.1 ehc initialization .................................................................................................201 5.20.1.1 bios initialization.................................................................................201 5.20.1.2 driver initialization................................................................................201 5.20.1.3 ehc resets .........................................................................................202 5.20.2 data structures in ma in memory .........................................................................202 5.20.3 usb 2.0 enhanced host controller dma . ...........................................................202 5.20.4 data encoding and bit stuffing .......... ..................................................................202 5.20.5 packet formats............... .....................................................................................202 5.20.6 usb 2.0 interrupts and error conditions .............................................................203 5.20.6.1 aborts on usb 2.0-initiated me mory reads ........................................203 5.20.7 usb 2.0 power management ..............................................................................204 5.20.7.1 pause feature .....................................................................................204 5.20.7.2 suspend feature .................................................................................204 5.20.7.3 acpi device states .............................................................................204 5.20.7.4 acpi system states ............................................................................205 5.20.7.5 mobile consideratio ns .........................................................................205 5.20.8 interaction with uhci ho st controllers ................................................................205 5.20.8.1 port-routing logic ...............................................................................206 5.20.8.2 device connects .......................... ........................................................207 5.20.8.3 device disconnects .............................................................................207 5.20.8.4 effect of resets on port-routing logic ................................................208 5.20.9 usb 2.0 legacy keyboard operation.................... ..............................................208 5.20.10 usb 2.0 based debug port .................................................................................208 5.20.10.1 theory of operation ............................................................................209 5.21 smbus controller (d31:f3) ..............................................................................................214 5.21.1 host controller .....................................................................................................214 5.21.1.1 command protocols ............................................................................215 5.21.2 bus arbitration .....................................................................................................218 5.21.3 bus timing ...........................................................................................................219 5.21.3.1 clock stretching ...................................................................................219 5.21.3.2 bus time out (intel ? ich6 as smbus master) ....................................219 5.21.4 interrupts / sm i# ..................................................................................................220 5.21.5 smbalert# .......................................................................................................221 5.21.6 smbus crc generation and checking.... ...........................................................221 5.21.7 smbus slave interface ........................................................................................221 5.21.7.1 format of slave write cycle ................................................................222 5.21.7.2 format of read command ..................................................................223 5.21.7.3 format of host notify command .........................................................225 5.22 ac ?97 controller (audio d30:f2, modem d30:f3) ..........................................................226 5.22.1 pci power management......................................................................................228 5.22.2 ac-link overview ................................................................................................228
10 intel ? i/o controller hub 6 (ich 6) family datasheet contents 5.22.2.1 register access ................................................................................... 230 5.22.3 ac-link low power mode ................................................................................... 231 5.22.3.1 external wake event ................... ........................................................ 232 5.22.4 ac ?97 cold reset ............................................................................................... 233 5.22.5 ac ?97 warm reset ........ ..................................................................................... 233 5.22.6 hardware assist to determine acz_sd in used per codec............................... 233 5.23 intel? high definition audio (d27:f0) ......... ..................................................................... 234 5.23.1 link protocol overview ........................................................................................ 234 5.23.1.1 frame composition.............................................................................. 234 5.23.2 link reset............................................................................................................ 235 5.23.3 link power management ..................................................................................... 235 6 register and memory mapping ...................................................................................... 237 6.1 pci devices and functions .............................................................................................. 238 6.2 pci configuration map ..................................................................................................... 23 9 6.3 i/o map ..................................................................................................................... ........ 239 6.3.1 fixed i/o address ranges................................................................................... 239 6.3.2 variable i/o decode ranges ............................................................................... 242 6.4 memory map.................................................................................................................. ... 243 6.4.1 boot-block update scheme................................................................................. 244 7 chipset configur ation registers .................................................................................. 247 7.1 chipset configuration registers (memory space) ........................................................... 247 7.1.1 vch?virtual channel capability header register ............................................. 249 7.1.2 vcap1?virtual channel capability #1 re gister................................................. 249 7.1.3 vcap2?virtual channel capability #2 re gister................................................. 250 7.1.4 pvc?port virtual channel control register....................................................... 250 7.1.5 pvs?port virtual channe l status register ... ................ ................ ............. ........ 250 7.1.6 v0cap?virtual channel 0 resource capability register .................................. 251 7.1.7 v0ctl?virtual channel 0 resource co ntrol register ....................................... 251 7.1.8 v0sts?virtual channel 0 resource st atus register ........................................ 252 7.1.9 rctcl?root complex topology capabilitie s list register .............................. 252 7.1.10 esd?element self description register ............................................................ 252 7.1.11 uld?upstream link descriptor register ........................................................... 253 7.1.12 ulba?upstream link base address register................................................... 253 7.1.13 rp1d?root port 1 descriptor register.............................................................. 253 7.1.14 rp1ba?root port 1 base address register ..................................................... 254 7.1.15 rp2d?root port 2 descriptor register.............................................................. 254 7.1.16 rp2ba?root port 2 base address register ..................................................... 254 7.1.17 rp3d?root port 3 descriptor register.............................................................. 255 7.1.18 rp3ba?root port 3 base address register ..................................................... 255 7.1.19 rp4d?root port 4 descriptor register.............................................................. 255 7.1.20 rp4ba?root port 4 base address register ..................................................... 256 7.1.21 hdd?intel ? high definition audio descriptor register ...................................... 256 7.1.22 hdba?intel ? high definition audio base address register .............................. 256 7.1.23 ilcl?internal link capabilities list register ..................................................... 257 7.1.24 lcap?link capabilities register ....................................................................... 257 7.1.25 lctl?link control register............................................................................... 257 7.1.26 lsts?link status register ................................................................................ 258 7.1.27 csir5?chipset initialization register 5 ............................................................. 258
intel ? i/o controller hub 6 (ich6) family datasheet 11 contents 7.1.28 csir6?chipset initializat ion register 6 .............................................................258 7.1.29 bcr?backbone configuration register .............................................................259 7.1.30 rpc?root port configuration register..............................................................259 7.1.31 csir7?chipset initializat ion register 7 .............................................................260 7.1.32 trsr?trap status register...............................................................................260 7.1.33 trcr?trapped cycle register..........................................................................260 7.1.34 twdr?trapped write data register.................................................................261 7.1.35 iotrn?i/o trap register (0:3)............................................................................261 7.1.36 dmc?dmi miscellaneous control regist er (mobile only) .................................262 7.1.37 cscr1?chipset configuration register 1 .........................................................262 7.1.38 cscr2?chipset configuration register 2 .........................................................262 7.1.39 pllmc?pll miscellaneous control regi ster (mobile only)..............................263 7.1.40 tctl?tco configuration register ....................................................................263 7.1.41 d31ip?device 31 interrupt pin register ............................................................264 7.1.42 d30ip?device 30 interrupt pin register ............................................................265 7.1.43 d29ip?device 29 interrupt pin register ............................................................266 7.1.44 d28ip?device 28 interrupt pin register ............................................................267 7.1.45 d27ip?device 27 interrupt pin register ............................................................267 7.1.46 d31ir?device 31 interrupt route register........................................................268 7.1.47 d30ir?device 30 interrupt route register........................................................269 7.1.48 d29ir?device 29 interrupt route register........................................................270 7.1.49 d28ir?device 28 interrupt route register........................................................271 7.1.50 d27ir?device 27 interrupt route register........................................................272 7.1.51 oic?other interrupt control register.................................................................273 7.1.52 rc?rtc configuration register ........................................................................273 7.1.53 hptc?high precision timer configuration register .........................................274 7.1.54 gcs?general control and status register........................................................274 7.1.55 buc?backed up control register .....................................................................276 7.1.56 fd?function disable register ...........................................................................277 7.1.57 cg?clock gating ...............................................................................................278 7.1.58 csir1?chipset initializat ion register 1 .............................................................279 7.1.59 csir2?chipset initializat ion register 2 .............................................................279 7.1.60 csir3?chipset initializat ion register 3 .............................................................279 7.1.61 csir4?chipset initializat ion register 4 .............................................................279 8 lan controller registers (b1:d8:f0) ..........................................................................281 8.1 pci configuration registers (lan controller?b1:d8:f0) ........................... ..................................................................281 8.1.1 vid?vendor identification register (lan controller?b1:d8:f0) ........................ ........................................................282 8.1.2 did?device identification register (lan controller?b1:d8:f0) ........................ ........................................................282 8.1.3 pcicmd?pci command register (lan controller?b1:d8:f0) ........................ ........................................................283 8.1.4 pcists?pci status register (lan controller?b1:d8:f0) ........................ ........................................................284 8.1.5 rid?revision identification register (lan controller?b1:d8:f0) ........................ ........................................................285
12 intel ? i/o controller hub 6 (ich 6) family datasheet contents 8.1.6 scc?sub class code register (lan controller?b1:d8:f0) ................................................................................ 285 8.1.7 bcc?base-class code register (lan controller?b1:d8:f0) ................................................................................ 285 8.1.8 cls?cache line size register (lan controller?b1:d8:f0) ................................................................................ 286 8.1.9 pmlt?primary master latency timer register (lan controller?b1:d8:f0) ................................................................................ 286 8.1.10 headtyp?header type register (lan controller?b1:d8:f0) ................................................................................ 286 8.1.11 csr_mem_base ? cs r memory-mapped base address register (lan controller?b1:d8:f0) ................................................... 287 8.1.12 csr_io_base ? csr i/o-mapped base address register (lan controller?b1:d8:f0) ................................................................................ 287 8.1.13 svid ? subsystem vendor identification (lan controller?b1:d8:f0) ................................................................................ 287 8.1.14 sid ? subsystem identification (lan controller?b1:d8:f0) ................................................................................ 288 8.1.15 cap_ptr ? capabilities pointer (lan controller?b1:d8:f0) ................................................................................ 288 8.1.16 int_ln ? interrupt line register (lan controller?b1:d8:f0) ................................................................................ 288 8.1.17 int_pn ? interrupt pin register (lan controller?b1:d8:f0) ................................................................................ 289 8.1.18 min_gnt ? mini mum grant register (lan controller?b1:d8:f0) ................................................................................ 289 8.1.19 max_lat ? maximum latency register (lan controller?b1:d8:f0) ................................................................................ 289 8.1.20 cap_id ? capability i dentification register (lan controller?b1:d8:f0) ................................................................................ 289 8.1.21 nxt_ptr ? next item pointer (lan controller?b1:d8:f0) ................................................................................ 290 8.1.22 pm_cap ? power management capabilities (lan controller?b1:d8:f0) ................................................................................ 290 8.1.23 pmcsr ? power management control/ status register (lan controller?b1:d8:f0) ...................................................... 291 8.1.24 pcidata ? pci power management data register (lan controller?b1:d8:f0) ................................................................................ 292 8.2 lan control / status registers (csr) (lan controller?b1:d8:f0) ............................................................................................. 293 8.2.1 scb_sta?system control block status word register (lan controller?b1:d8:f0) ................................................................................ 294 8.2.2 scb_cmd?system control block command word register (lan controller?b1 :d8:f0).................................................................. 296 8.2.3 scb_genpnt?system cont rol block general pointer register (lan controller?b1 :d8:f0).................................................................. 298 8.2.4 port?port interface register (lan controller?b1:d8:f0) ................................................................................ 298 8.2.5 eeprom_cntl?eeprom control register (lan controller?b1:d8:f0) ................................................................................ 299 8.2.6 mdi_cntl?management data interface (mdi) control register (lan controller?b1 :d8:f0).................................................................. 300
intel ? i/o controller hub 6 (ich6) family datasheet 13 contents 8.2.7 rec_dma_bc?receive dm a byte count register (lan controller?b1:d8:f0) ........................ ........................................................300 8.2.8 erec_intr?early receive interrupt register (lan controller?b1:d8:f0) ........................ ........................................................301 8.2.9 flow_cntl?flow control register (lan controller?b1:d8:f0) ........................ ........................................................302 8.2.10 pmdr?power management driver register (lan controller?b1:d8:f0) ........................ ........................................................303 8.2.11 gencntl?general control register (lan controller?b1:d8:f0) ........................ ........................................................304 8.2.12 gensta?general status register (lan controller?b1:d8:f0) ........................ ........................................................304 8.2.13 smb_pci?smb via pci register (lan controller?b1:d8:f0) ........................ ........................................................305 8.2.14 statistical counters (lan controller?b1:d8:f0) ........................ ........................................................306 8.3 asf configuration registers (lan controller?b1:d8:f0) ........................... ..................................................................308 8.3.1 asf_rid?asf revision identification register (lan controller?b1:d8:f0) ........................ ........................................................309 8.3.2 smb_cntl?smbus control register (lan controller?b1:d8:f0) ........................ ........................................................309 8.3.3 asf_cntl?asf control register (lan controller?b1:d8:f0) ........................ ........................................................310 8.3.4 asf_cntl_en?asf co ntrol enable register (asf controller?b1:d8:f0) ................................................................................311 8.3.5 enable?enable register (asf controller?b1:d8:f0) ................................................................................312 8.3.6 apm?apm register (asf controller?b1:d8:f0) ................................................................................313 8.3.7 wtim_conf?watchdog time r configuration register (asf controller?b1:d8:f0) ................................................................................313 8.3.8 heart_tim?heartb eat timer register (asf controller?b1:d8:f0) ................................................................................314 8.3.9 retran_int?retransmission interval register (asf controller?b1:d8:f0) ................................................................................314 8.3.10 retran_pcl?retrans mission packet count limit register (asf controller?b1:d8:f0)....... ...........................................................315 8.3.11 asf_wtim1?asf watchdog timer 1 register (asf controller?b1:d8:f0) ................................................................................315 8.3.12 asf_wtim2?asf watchdog timer 2 register (asf controller?b1:d8:f0) ................................................................................315 8.3.13 pet_seq1?pet sequence 1 register (asf controller?b1:d8:f0) ................................................................................316 8.3.14 pet_seq2?pet sequence 2 register (asf controller?b1:d8:f0) ................................................................................316 8.3.15 sta?status register (asf controller?b1:d8:f0) ................................................................................317 8.3.16 for_act?forced actions register (asf controller?b1:d8:f0) ................................................................................318 8.3.17 rmcp_snum?rmcp se quence number register (asf controller?b1:d8:f0) ................................................................................318
14 intel ? i/o controller hub 6 (ich 6) family datasheet contents 8.3.18 sp_mode?special modes register (asf controller?b1:d8:f0) ................................................................................ 319 8.3.19 inpoll_tconf?inter-poll timer configurat ion register (asf controller?b1:d8:f0) ................................................................................ 319 8.3.20 phist_clr?poll hi story clear register (asf controller?b1:d8:f0) ................................................................................ 320 8.3.21 pmsk1?polling mask 1 register (asf controller?b1:d8:f0) ................................................................................ 320 8.3.22 pmsk2?polling mask 2 register (asf controller?b1:d8:f0) ................................................................................ 321 8.3.23 pmsk3?polling mask 3 register (asf controller?b1:d8:f0) ................................................................................ 321 8.3.24 pmsk4?polling mask 4 register (asf controller?b1:d8:f0) ................................................................................ 321 8.3.25 pmsk5?polling mask 5 register (asf controller?b1:d8:f0) ................................................................................ 322 8.3.26 pmsk6?polling mask 6 register (asf controller?b1:d8:f0) ................................................................................ 322 8.3.27 pmsk7?polling mask 7 register (asf controller?b1:d8:f0) ................................................................................ 322 8.3.28 pmsk8?polling mask 8 register (asf controller?b1:d8:f0) ................................................................................ 323 9 pci-to-pci bridge registers (d30:f0) ......................................................................... 325 9.1 pci configuration registers (d30:f0) .............................................................................. 325 9.1.1 vid? vendor identification register (pci-pci?d30:f0) ................................... 326 9.1.2 did? device identification register (pci-pci?d30:f0) ................................... 326 9.1.3 pcicmd?pci command (pci-pci?d30:f 0) ................................................... 327 9.1.4 psts?pci status register (pci-pci?d30:f0) ................................................ 328 9.1.5 rid?revision identification register (pci-pci?d30:f0).................................. 329 9.1.6 cc?class code register (pci-pci?d30:f0) ................................................... 329 9.1.7 pmlt?primary master latency timer register (pci-pci?d30:f0).............................................................................................. 330 9.1.8 headtyp?header type register (pci-pci?d30:f0) ..................................... 330 9.1.9 bnum?bus number register (pci-pci?d30:f0) ............................................ 330 9.1.10 smlt?secondary master latency timer register (pci-pci?d30:f0).............................................................................................. 331 9.1.11 iobase_limit?i/o base and limit register (pci-pci?d30:f0).............................................................................................. 331 9.1.12 secsts?secondary status register (pci-pci?d30:f0) ................................ 332 9.1.13 membase_limit?memory base and limit register (pci-pci?d30:f0).............................................................................................. 333 9.1.14 pref_mem_base_limit? prefetchable memory base and limit register (pci-pci?d30:f0)................................................................ 333 9.1.15 pmbu32?prefetchable memory base upper 32 bits register (pci-pci?d30:f0) ............................................................................... 334 9.1.16 pmlu32?prefetchable memory limit upper 32 bits register (pci-pci?d30:f0) ............................................................................... 334 9.1.17 capp?capability list pointer register (pci-pci?d30:f0) ... ................ ........... 334 9.1.18 intr?interrupt information register (pci-pci?d30:f0) .................................. 334
intel ? i/o controller hub 6 (ich6) family datasheet 15 contents 9.1.19 bctrl?bridge control register (pci-pci?d30:f0) ........................................335 9.1.20 spdh?secondary pci device hiding register (pci-pci?d30:f0) ..............................................................................................336 9.1.21 pdpr?pci decode policy register (pci-pci?d30:f0) ..............................................................................................337 9.1.22 dtc?delayed transac tion control register (pci-pci?d30:f0) ..............................................................................................338 9.1.23 bps?bridge propri etary status register (pci-pci?d30:f0) ..............................................................................................339 9.1.24 bpc?bridge policy configuration register (pci-pci?d30:f0) ..............................................................................................340 9.1.25 svcap?subsystem vendor capability register (pci-pci?d30:f0) ..............................................................................................340 9.1.26 svid?subsystem vendor ids register (pci-pci?d30:f0)..............................341 10 lpc interface bridge registers (d31:f0) ...................................................................343 10.1 pci configuration registers (lpc i/f?d31: f0) ..............................................................343 10.1.1 vid?vendor identification register (lpc i/f?d31:f0) .....................................344 10.1.2 did?device identification register (lpc i/f?d31:f0)......................................344 10.1.3 pcicmd?pci command register (lpc i/f?d31:f0)....................................345 10.1.4 pcists?pci status register (lpc i/ f?d31:f0)..............................................346 10.1.5 rid?revision identification register (lpc i/f?d31:f0)...................................347 10.1.6 pi?programming interface register (l pc i/f?d31:f0) ....................................347 10.1.7 scc?sub class code register (lpc i/ f?d31:f0) ..........................................347 10.1.8 bcc?base class code register (lpc i/f?d31:f0) .........................................347 10.1.9 plt?primary latency ti mer register (lpc i/f?d31:f0) .................................348 10.1.10 headtyp?header type register (lpc i/f?d31:f0) ......................................348 10.1.11 ss?sub system identifiers register (lpc i/f?d31:f0) ...................................348 10.1.12 pmbase?acpi base address register (lpc i/f? d31:f0) ............ ............. ....349 10.1.13 acpi_cntl?acpi control register (l pc i/f ? d31:f0) .................................349 10.1.14 gpiobase?gpio base address register (lpc i/f ? d31:f0 ) ............ ...........350 10.1.15 gc?gpio control register (lpc i/f ? d31:f0) ...............................................350 10.1.16 pirq[n]_rout?pirq[a,b,c, d] routing control register (lpc i/f?d31:f0) ...............................................................................................351 10.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0) ...............................................................................................352 10.1.18 pirq[n]_rout?pirq[e,f,g, h] routing control register (lpc i/f?d31:f0) ...............................................................................................353 10.1.19 lpc_i/o_dec?i/o decode ranges register (lpc i/f?d31:f0) ...............................................................................................354 10.1.20 lpc_en?lpc i/f enable s register (lpc i/f?d31:f0)....................................355 10.1.21 gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0) ...............................................................................................356 10.1.22 gen2_dec?lpc i/f generic decode range 2 register (lpc i/f?d31:f0) ...............................................................................................356 10.1.23 fwh_sel1?firmware hub select 1 register (lpc i/f?d31:f0) ...............................................................................................357 10.1.24 fwh_sel2?firmware hub select 2 register (lpc i/f?d31:f0) ...............................................................................................358 10.1.25 fwh_dec_en1?firmware hub decode enable register (lpc i/f?d31:f0) ...............................................................................................359
16 intel ? i/o controller hub 6 (ich 6) family datasheet contents 10.1.26 bios_cntl?bios control register (lpc i/f?d31:f0)............................................................................................... 360 10.1.27 rcba?root complex base address register (lpc i/f?d31:f0)............................................................................................... 361 10.2 dma i/o registers (lpc i/f?d31:f0)............................................................................. 361 10.2.1 dmabase_ca?dma base and current address registers (lpc i/f?d31:f0)............................................................................... 363 10.2.2 dmabase_cc?dma ba se and current count registers (lpc i/f?d31:f0)............................................................................................... 363 10.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0)............................................................................................... 364 10.2.4 dmacmd?dma command register (lpc i/f?d31:f0) .................................. 364 10.2.5 dmasta?dma status register (lpc i/f?d31:f0).......................................... 365 10.2.6 dma_wrsmsk?dma writ e single mask register (lpc i/f?d31:f0)............................................................................................... 365 10.2.7 dmach_mode?dma ch annel mode register (lpc i/f?d31:f0)............................................................................................... 366 10.2.8 dma clear byte pointer register (lpc i/f?d31:f0) ......................................... 366 10.2.9 dma master clear regist er (lpc i/f?d31:f0).................................................. 367 10.2.10 dma_clmsk?dma clear mask register (lpc i/f?d31:f0) .......................... 367 10.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0)............................................................................................... 367 10.3 timer i/o registers (lpc i/f?d31:f0).......... .................................................................. 368 10.3.1 tcw?timer control word register (l pc i/f?d31:f0) .................................... 369 10.3.2 sbyte_fmt?interval timer status byte format register (lpc i/f?d31:f0)............................................................................................... 371 10.3.3 counter access ports register (lpc i/ f?d31:f0)............................................. 372 10.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0)............................................................................................................ 372 10.4.1 interrupt controller i/o map (lpc i/f? d31:f0) ................................................. 372 10.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0)............................................................................................... 373 10.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0)............................................................................................... 374 10.4.4 icw3?master controlle r initialization command word 3 register (lpc i/f?d31:f0).................................................................... 374 10.4.5 icw3?slave contro ller initialization command word 3 register (lpc i/f?d31:f0).................................................................... 375 10.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0)............................................................................................... 375 10.4.7 ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0) ................................................................................ 376 10.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0)............................................................................................... 376 10.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0)............................................................................................... 377 10.4.10 elcr1?master controller edge/level triggered register (lpc i/f?d31:f0)............................................................................................... 378 10.4.11 elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0)............................................................................................... 379 10.5 advanced programmable inte rrupt controller (apic)(d31:f0) ........................................ 380 10.5.1 apic register map (lpc i/f?d31:f0) ............................................................... 380
intel ? i/o controller hub 6 (ich6) family datasheet 17 contents 10.5.2 ind?index register (lpc i/f?d31:f0) . ............................................................380 10.5.3 dat?data register (lpc i/f?d31:f0) . ............................................................381 10.5.4 eoir?eoi register (lpc i/f?d31:f0) . ............................................................381 10.5.5 id?identification register (lpc i/f?d 31:f0) ....................................................382 10.5.6 ver?version register (lpc i/f?d31:f0) ........................................................382 10.5.7 redir_tbl?redirection table (lpc i/f?d31:f0) ..........................................383 10.6 real time clock registers (lpc i/f?d31:f0 ) ................................................................385 10.6.1 i/o register address ma p (lpc i/f?d31:f0).....................................................385 10.6.2 indexed registers (lpc i/f?d31:f0) .................................................................386 10.6.2.1 rtc_rega?register a (lpc i/f ?d31:f0) ......................................387 10.6.2.2 rtc_regb?register b (general configuration) (lpc i/f?d31:f0) ...............................................................................388 10.6.2.3 rtc_regc?register c (flag register) (lpc i/f?d31:f0) ...............................................................................389 10.6.2.4 rtc_regd?register d (flag register) (lpc i/f?d31:f0) ...............................................................................389 10.7 processor interface registers (lpc i/f?d3 1:f0) ...........................................................390 10.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) ...............................................................................................390 10.7.2 nmi_en?nmi enable (a nd real time clock index) register (lpc i/f?d31:f0).................................................................................391 10.7.3 port92?fast a20 and init register (l pc i/f?d31:f0)...................................391 10.7.4 coproc_err?coprocessor error register (lpc i/f?d31:f0) ...............................................................................................392 10.7.5 rst_cnt?reset co ntrol register (lpc i/f?d31:f0) .....................................392 10.8 power management register s (pm?d31:f0) .................................................................393 10.8.1 power management pci configuration registers (pm?d31:f0)......................................................................................................393 10.8.1.1 gen_pmcon_1?general pm configuration 1 register (pm?d31:f0) ......................................................................................394 10.8.1.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) ......................................................................................395 10.8.1.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) ......................................................................................397 10.8.1.4 cx-state_cnf?cx state configuration register (pm?d31:f0) (mobile only) ...............................................................398 10.8.1.5 c4-timing_cnt?c4 timing control register (pm?d31:f0) (mobile only) ...............................................................399 10.8.1.6 bm_break_en register (pm?d 31:f0) (mobile only ) ............. ........400 10.8.1.7 msc_fun?miscellaneous functionality register (pm?d31:f0) ......................................................................................401 10.8.1.8 gpi_rout?gpi ro uting control register (pm?d31:f0) ......................................................................................401 10.8.2 apm i/o decode ..................................................................................................402 10.8.2.1 apm_cnt?advanced power management control port register................................................................................................402 10.8.2.2 apm_sts?advanced power management status port register................................................................................................402 10.8.3 power management i/o registers......... ..............................................................403 10.8.3.1 pm1_sts?powe r management 1 status register ............................404 10.8.3.2 pm1_en?power m anagement 1 enable register .............................406 10.8.3.3 pm1_cnt?power management 1 c ontrol .........................................407 10.8.3.4 pm1_tmr?power ma nagement 1 timer register ............................408
18 intel ? i/o controller hub 6 (ich 6) family datasheet contents 10.8.3.5 proc_cnt?processo r control register .......................................... 408 10.8.3.6 lv2 ? level 2 register ............... ........................................................ 410 10.8.3.7 lv3?level 3 regist er (mobile only)................................................... 410 10.8.3.8 lv4?level 4 regist er (mobile only)................................................... 410 10.8.3.9 pm2_cnt?po wer management 2 control (m obile only) .................. 411 10.8.3.10 gpe0_sts?ge neral purpose event 0 status register..................... 411 10.8.3.11 gpe0_en?gen eral purpose event 0 enables register .................... 414 10.8.3.12 smi_en?smi control and enable register ....................................... 416 10.8.3.13 smi_sts?smi status register .. ........................................................ 418 10.8.3.14 alt_gp_smi_en?alt ernate gpi smi enable register..................... 420 10.8.3.15 alt_gp_smi_sts?al ternate gpi smi status register.................... 420 10.8.3.16 devact_sts ? device activity st atus register....... ................ ........ 421 10.8.3.17 ss_cnt? intel speedstep ? technology control register (mobile only)........ ..................................................... 422 10.8.3.18 c3_res? c3 residency register (mobile only) ............................... 422 10.9 system management tco regi sters (d31:f0)................................................................ 423 10.9.1 tco_rld?tco timer rel oad and current value register.............................. 423 10.9.2 tco_dat_in?tco data in register ................................................................ 424 10.9.3 tco_dat_out?tco data out register ......................................................... 424 10.9.4 tco1_sts?tco1 status register ................................................................... 424 10.9.5 tco2_sts?tco2 status register ................................................................... 426 10.9.6 tco1_cnt?tco1 control register.................................................................. 427 10.9.7 tco2_cnt?tco2 control register.................................................................. 428 10.9.8 tco_message1 and tco_ message2 registers........ ............. ............. ........ 428 10.9.9 tco_wdcnt?tco watchdog control re gister .............................................. 429 10.9.10 sw_irq_gen?software ir q generation register .......................................... 429 10.9.11 tco_tmr?tco timer in itial value register .................................................... 429 10.10 general purpose i/o registers (d31:f0) .... ..................................................................... 430 10.10.1 gpio register i/o address map ......................................................................... 430 10.10.2 gpio_use_sel?gpio use select register .................................................... 431 10.10.3 gp_io_sel?gpio input/ output select register .............................................. 431 10.10.4 gp_lvl?gpio leve l for input or output register ............................................ 432 10.10.5 gpo_blink?gpo blink enable regist er ......................................................... 433 10.10.6 gpi_inv?gpio signal invert register............................................................... 434 10.10.7 gpio_use_sel2?gpio us e select 2 register[63:32] . ................................... 435 10.10.8 gp_io_sel2?gpio inpu t/output select 2 register[6 3:32] .............................. 435 10.10.9 gp_lvl2?gpio level for input or output 2 register[63:32] ............................ 436 11 ide controller registers (d31:f1) ................................................................................ 437 11.1 pci configuration registers (ide?d31:f1) .................................................................... 437 11.1.1 vid?vendor identificati on register (ide?d31:f1) ........................................... 438 11.1.2 did?device identification register (ide?d31:f1)............................................ 438 11.1.3 pcicmd?pci command register (ide ?d31:f1) ............................................ 439 11.1.4 pcists ? pci status register (ide ?d31:f1).................................................. 440 11.1.5 rid?revision identificati on register (ide?d31:f1)......................................... 441 11.1.6 pi?programming interface register (ide?d31:f1) .......................................... 441 11.1.7 scc?sub class code register (ide?d 31:f1) ................................................ 441 11.1.8 bcc?base class code register (ide?d31:f1)............................................... 442 11.1.9 cls?cache line size register (ide?d 31:f1)................................................. 442 11.1.10 pmlt?primary master latency timer register (ide?d31:f1) ..................................................................................................... 442
intel ? i/o controller hub 6 (ich6) family datasheet 19 contents 11.1.11 pcmd_bar?primary co mmand block base address register (ide?d31:f1).......................................................................................442 11.1.12 pcnl_bar?primary co ntrol block base address register (ide?d31:f1).......................................................................................443 11.1.13 scmd_bar?secondary co mmand block base address register (ide d31:f1) .........................................................................................443 11.1.14 scnl_bar?secondary control block base address register (ide d31:f1) .........................................................................................443 11.1.15 bm_base ? bus master base address register (ide?d31:f1) .....................................................................................................444 11.1.16 ide_svid ? subsystem vendor identification (ide?d31:f1) .....................................................................................................444 11.1.17 ide_sid ? subsystem identification register (ide?d31:f1) .....................................................................................................444 11.1.18 intr_ln?interrupt line register (ide?d31:f1) ..............................................445 11.1.19 intr_pn?interrupt pin register (i de?d31:f1) ...............................................445 11.1.20 ide_timp ? ide primar y timing register (ide?d31:f1) ................................445 11.1.21 ide_tims ? ide secondary timing register (ide?d31:f1) .....................................................................................................447 11.1.22 slv_idetim?slave (drive 1) ide timing register (ide?d31:f1) .....................................................................................................447 11.1.23 sdma_cnt?synchronous dma control register (ide?d31:f1) .....................................................................................................448 11.1.24 sdma_tim?synchronous dma timing register (ide?d31:f1) .....................................................................................................449 11.1.25 ide_config?ide i/o configuration register (ide?d31:f1) .....................................................................................................450 11.1.26 atc?apm trapping control register (ide?d31:f1) .......................................451 11.1.27 ats?apm trapping status register (ide?d31:f1) .........................................451 11.2 bus master ide i/o registers (ide?d31:f1) ..................................................................451 11.2.1 bmicp?bus master ide command register (ide?d31:f1) .....................................................................................................452 11.2.2 bmisp?bus master ide status regist er (ide?d31:f1)...................................453 11.2.3 bmidp?bus master ide de scriptor table po inter register (ide?d31:f1) .....................................................................................................453 12 sata controller registers (d31:f2) ............................................................................455 12.1 pci configuration register s (sata?d31:f2)...................................................................455 12.1.1 vid?vendor identificat ion register (sata?d31:f2) ........................................456 12.1.2 did?device identification register (sata?d31:f2) ........................................457 12.1.3 pcicmd?pci command register (sata? d31:f2)...........................................457 12.1.4 pcists ? pci status register (sata? d31:f2) ................................................458 12.1.5 rid?revision identification register (sata?d31:f2)......................................458 12.1.6 pi?programming interface register (s ata?d31:f2) ........................................459 12.1.6.1 when sub class code register (d31:f2:offset 0ah) = 01h ...............459 12.1.6.2 when sub class code register (d31:f2:offset 0ah) = 04h ...............459 12.1.6.3 when sub class code register (d31:f2:offset 0ah) = 06h ...............460 12.1.7 scc?sub class code regi ster (sata?d31:f2).......... .....................................460 12.1.8 bcc?base class code register (sata?d31:f2sata?d31:f2) ............................................................................460 12.1.9 pmlt?primary master latency timer register (sata?d31:f2) ...................................................................................................461
20 intel ? i/o controller hub 6 (ich 6) family datasheet contents 12.1.10 pcmd_bar?primary co mmand block base address register (sata?d31:f2)..................................................................................... 461 12.1.11 pcnl_bar?primary contro l block base address register (sata?d31:f2) ................................................................................................... 461 12.1.12 scmd_bar?secondary command block base address register (ide d31:f1) ......................................................................................... 462 12.1.13 scnl_bar?secondary control block base address register (ide d31:f1) ......................................................................................... 462 12.1.14 bar ? legacy bus master base address register (sata?d31:f2) ................................................................................................... 462 12.1.15 abar ? ahci ba se address register (sata?d31:f2) ................................................................................................... 463 12.1.15.1 intel ? ich6 only .................................................................................. 463 12.1.15.2 intel ? ich6r / ich6-m only ................................................................ 463 12.1.16 svid?subsystem vendor identification register (sata?d31:f2) ................................................................................................... 463 12.1.17 sid?subsystem identification regist er (sata?d31:f2) ................................... 464 12.1.18 cap?capabilities pointer register (sat a?d31:f2).......................................... 464 12.1.19 int_ln?inte rrupt line register (sata?d31:f2 )............................................... 464 12.1.20 int_pn?interrupt pin register (sata? d31:f2)................................................ 464 12.1.21 ide_tim ? ide timing register (sat a?d31:f2) .............................................. 465 12.1.22 sidetim?slave ide timing register (sata?d31:f2)...................................... 467 12.1.23 sdma_cnt?synchronous dma control register (sata?d31:f2) ................................................................................................... 468 12.1.24 sdma_tim?synchronous dma timing register (sata?d31:f2) ................................................................................................... 469 12.1.25 ide_config?ide i/o configuration register (sata?d31:f2) ................................................................................................... 470 12.1.26 pid?pci power manageme nt capability identification register (sata?d31:f2)..................................................................................... 471 12.1.27 pc?pci power managem ent capabilities register (sata?d31:f2) ................................................................................................... 471 12.1.28 pmcs?pci power management control and status register (sata?d31:f2)..................................................................................... 472 12.1.29 map?address map regist er (sata?d31:f2) ................................................... 472 12.1.30 pcs?port control and status regist er (sata?d31:f2) ................................... 473 12.1.31 sir - sata initialization register ...... .................................................................. 474 12.1.32 siri?sata indexed registers index .. ............................................................... 475 12.1.33 strd?sata indexed register data ...... ........................................................... 475 12.1.34 sttt1?sata indexed registers index 00h (sata tx termination test register 1) .............................................................. 476 12.1.35 sir18?sata indexed registers index 18h (sata initialization register 18h)........................................................................ 477 12.1.36 stme?sata indexed registers index 1ch (sata test mode enable register) .................................................................... 477 12.1.37 sir28?sata indexed registers index 28h (sata initialization register 28h)........................................................................ 477 12.1.38 sttt2?sata indexed registers index 74h (sata tx termination test register 2) .............................................................. 478 12.1.39 sir84?sata indexed registers index 84h (sata initialization register 84h)........................................................................ 479 12.1.40 atc?apm trapping control register (sata?d31:f2) ..................................... 479
intel ? i/o controller hub 6 (ich6) family datasheet 21 contents 12.1.41 ats?apm trapping status register (sata?d31:f2) ............ ...........................480 12.1.42 sp?scratch pad register (sata?d31: f2) ........................................................480 12.1.43 bfcs?bist fis control/ status register (sata?d31:f2) ................................480 12.1.44 bftd1?bist fis transmit data1 regist er (sata?d31:f2).............................482 12.1.45 bftd2?bist fis transmit data2 regist er (sata?d31:f2).............................482 12.2 bus master ide i/o registers (d31:f2) ...... .....................................................................483 12.2.1 bmic[p,s]?bus master ide command register (d31:f2) ................................484 12.2.2 bmis[p,s]?bus master ide status regi ster (d31:f2).......................................485 12.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) ................................................................................................485 12.3 ahci registers (d31:f2) ..................................................................................................48 6 12.3.1 ahci generic host control registers (d31:f2) ..................................................486 12.3.1.1 cap?host capabilities register (d31:f2) .........................................487 12.3.1.2 ghc?global ich6 control regist er (d31:f2)....................................488 12.3.1.3 is?interrupt status register (d31:f2) ................................................489 12.3.1.4 pi?ports implemented register (d31:f2) ..........................................490 12.3.1.5 vs?ahci version (d31:f2)................................................................490 12.3.2 port registers (d31:f2) .......................................................................................491 12.3.2.1 pxclb?port [3 :0] command list base address register (d31:f2) ...............................................................................................493 12.3.2.2 pxclbu?port [3:0] command list base address upper 32-bits register (d31:f2) ....................................................................493 12.3.2.3 pxfb?port [3:0] fi s base address register (d31:f2) ......................493 12.3.2.4 pxfbu?port [3:0] fi s base address upper 32-bits register (d31:f2) ................................................................................494 12.3.2.5 pxis?port [3:0] inte rrupt status register (d31:f2) ............................494 12.3.2.6 pxie?port [3:0] in terrupt enable register (d 31:f2) ...........................496 12.3.2.7 pxcmd?port [3:0] command regi ster (d31:f2) ...............................497 12.3.2.8 pxtfd?port [3:0] task file data register (d31:f2) ..........................499 12.3.2.9 pxsig?port [3:0] si gnature register (d31:f2) ..................................500 12.3.2.10 pxssts?port [3:0] serial ata status regi ster (d31:f2) ..................501 12.3.2.11 pxsctl?port [3:0] serial ata control re gister (d31:f2) .................502 12.3.2.12 pxserr?port [3:0] serial ata error register (d31:f2) ....................503 12.3.2.13 pxsact?port [3:0] serial ata active (d31:f2) .................................504 12.3.2.14 pxci?port [3:0] command issue register (d31:f2) ..........................505 13 uhci controllers registers .............................................................................................507 13.1 pci configuration registers (usb?d29:f0/f1/f2/f3) .................................................................................................507 13.1.1 vid?vendor identification register (usb?d29:f0/f1/f2/f3) ....................................................................................508 13.1.2 did?device identification register (usb?d29:f0/f1/f2/f3) ....................................................................................508 13.1.3 pcicmd?pci command register (usb?d29:f0/f1/f2/f3) ...........................508 13.1.4 pcists?pci status register (usb?d2 9:f0/f1/f2/f3) ...................................509 13.1.5 rid?revision identification register (usb?d29:f0/f1/f2/f3) ....................................................................................509 13.1.6 pi?programming interface register (usb?d29:f0/f1/f2/f3) ....................................................................................510 13.1.7 scc?sub class code register (usb?d29:f0/f1/f2/f3) ....................................................................................510 13.1.8 bcc?base class code register (usb?d29:f0/f1/f2/f3) ....................................................................................510
22 intel ? i/o controller hub 6 (ich 6) family datasheet contents 13.1.9 mlt?master latency timer register (usb?d29:f0/f1/f2/f3) .................................................................................... 510 13.1.10 headtyp?header type register (usb?d29:f0/f1/f2/f3) .................................................................................... 511 13.1.11 base?base ad dress register (usb?d29:f0/f1/f2/f3) .................................................................................... 511 13.1.12 svid ? subsystem vendo r identification register (usb?d29:f0/f1/f2/f3) .................................................................................... 512 13.1.13 sid ? subsystem id entification register (usb?d29:f0/f1/f2/f3) .................................................................................... 512 13.1.14 int_ln?interr upt line register (usb?d29:f0/f1/f2/f3) .................................................................................... 512 13.1.15 int_pn?interrupt pin register (usb?d29:f0/f1/f2/f3) .................................................................................... 513 13.1.16 usb_relnum?serial bus release number register (usb?d29:f0/f1/f2/f3) .................................................................................... 513 13.1.17 usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2/f3)...................................................................... 514 13.1.18 usb_res?usb resu me enable register (usb?d29:f0/f1/f2/f3) .................................................................................... 515 13.1.19 cwp?core well policy register (usb?d29:f0/f1/f2/f3) .................................................................................... 516 13.2 usb i/o registers .......................................................................................................... .. 516 13.2.1 usbcmd?usb command register .................................................................. 517 13.2.2 usbsts?usb status regi ster............... ................ ................ ................ ........... 520 13.2.3 usbintr?usb interrupt enable register ......................................................... 521 13.2.4 frnum?frame number re gister...................................................................... 521 13.2.5 frbaseadd?frame list ba se address regist er .............. ............. ............ ..... 522 13.2.6 sofmod?start of frame modify regi ster ........................................................ 523 13.2.7 portsc[0,1]?port status and control register ............................................... 524 14 ehci controller registers (d29:f7) ............................................................................. 527 14.1 usb ehci configuration registers (usb ehci?d29:f7) ....................................................................................................... 527 14.1.1 vid?vendor iden tification register (usb ehci?d29:f7) .......................................................................................... 528 14.1.2 did?device identification register (usb ehci?d29:f7) .......................................................................................... 528 14.1.3 pcicmd?pci command register (usb ehci?d29:f7) .......................................................................................... 529 14.1.4 pcists?pci status register (usb ehci?d29:f7) .......................................................................................... 530 14.1.5 rid?revision iden tification register (usb ehci?d29:f7) .......................................................................................... 531 14.1.6 pi?programming interface register (usb ehci?d29:f7) .......................................................................................... 531 14.1.7 scc?sub class code register (usb ehci?d29:f7) .......................................................................................... 531 14.1.8 bcc?base class code register (usb ehci?d29:f7) .......................................................................................... 531 14.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7) .......................................................................................... 532
intel ? i/o controller hub 6 (ich6) family datasheet 23 contents 14.1.10 mem_base?memory ba se address register (usb ehci?d29:f7) ..........................................................................................532 14.1.11 svid?usb ehci sub system vendor id register (usb ehci?d29:f7) ..........................................................................................532 14.1.12 sid?usb ehci subsystem id register (usb ehci?d29:f7) ..........................................................................................533 14.1.13 cap_ptr?capabilit ies pointer register (usb ehci?d29:f7) ..........................................................................................533 14.1.14 int_ln?interrupt line register (usb ehci?d29:f7) ..........................................................................................533 14.1.15 int_pn?interr upt pin register (usb ehci?d29:f7) ..........................................................................................533 14.1.16 pwr_capid?pci powe r management capability id register (usb ehci?d29:f7)............................................................................534 14.1.17 nxt_ptr1?next ite m pointer #1 register (usb ehci?d29:f7) ..........................................................................................534 14.1.18 pwr_cap?power manage ment capabilities register (usb ehci?d29:f7) ..........................................................................................535 14.1.19 pwr_cntl_sts?power management control/status register (usb ehci?d29:f7)............................................................................536 14.1.20 debug_capid?debug po rt capability id register (usb ehci?d29:f7) ..........................................................................................536 14.1.21 nxt_ptr2?next ite m pointer #2 register (usb ehci?d29:f7) ..........................................................................................537 14.1.22 debug_base?debug port base offset register (usb ehci?d29:f7) ..........................................................................................537 14.1.23 usb_relnum?usb rele ase number register (usb ehci?d29:f7) ..........................................................................................537 14.1.24 fl_adj?frame length adjustment register (usb ehci?d29:f7) ..........................................................................................538 14.1.25 pwake_cap?port wa ke capability register (usb ehci?d29:f7) ..........................................................................................539 14.1.26 leg_ext_cap? usb ehci legacy support extended capability register (usb ehci?d29:f7) ...........................................................539 14.1.27 leg_ext_cs? usb ehci legacy support extended control / status register (usb ehci?d29:f7) ..................................................540 14.1.28 special_smi?in tel specific usb 2.0 smi register (usb ehci?d29:f7) ..........................................................................................541 14.1.29 access_cntl?acces s control register (usb ehci?d29:f7) ..........................................................................................543 14.1.30 usb2ir?usb2 init ialization register (usb ehci?d29:f7) ..........................................................................................543 14.2 memory-mapped i/o registers.........................................................................................544 14.2.1 host controller capabilit y registers ....................................................................544 14.2.1.1 caplength?capability register s length register .........................544 14.2.1.2 hciversion?host contro ller interface version number register................................................................................................545 14.2.1.3 hcsparams?host co ntroller structural para meters......... ..............545 14.2.1.4 hccparams?host cont roller capability parameters register................................................................................................546 14.2.2 host controller operatio nal registers .................................................................547 14.2.2.1 usb2.0_cmd?usb 2.0 command register .....................................548
24 intel ? i/o controller hub 6 (ich 6) family datasheet contents 14.2.2.2 usb2.0_sts?usb 2.0 status register ............................................. 550 14.2.2.3 usb2.0_intr?usb 2.0 interrupt enable register ............................ 552 14.2.2.4 frindex?frame index register .. ..................................................... 553 14.2.2.5 ctrldssegme nt?control data structure segment register................................................................................................ 554 14.2.2.6 periodiclistbase?periodic frame list base address register................................................................................................ 554 14.2.2.7 asynclistaddr?current asynchronous list address register................................................................................................ 555 14.2.2.8 configflag?configu re flag register ............................................ 555 14.2.2.9 portsc?port n stat us and control register ................................... 556 14.2.3 usb 2.0-based debug port register ... ............................................................... 560 14.2.3.1 cntl_sts?control/status regist er.................................................. 560 14.2.3.2 usbpid?usb pids re gister ............... ............ ............. ............. ........ 562 14.2.3.3 databuf[7:0]?data buffer bytes[7:0] register ................................ 562 14.2.3.4 config?configuration register ........................................................ 562 15 smbus controller registers (d31:f3) ......................................................................... 563 15.1 pci configuration registers (smbus?d31:f3)............................................................... 563 15.1.1 vid?vendor identifica tion register (smbus?d31:f3)...................................... 563 15.1.2 did?device identification register (smbus?d31:f3) ...................................... 564 15.1.3 pcicmd?pci command register (smb us?d31:f3)....................................... 564 15.1.4 pcists?pci status register (smbus?d31:f3) .............................................. 565 15.1.5 rid?revision identification register (smbus?d31:f3) ................................... 565 15.1.6 pi?programming interface register (smbus?d31:f3) .................................... 566 15.1.7 scc?sub class code register (smb us?d31:f3)........................................... 566 15.1.8 bcc?base class code register (smbus ?d31:f3) ......................................... 566 15.1.9 smb_base?smbus ba se address register (smbus?d31:f3) ............................................................................................... 566 15.1.10 svid?subsystem vendor identification register (smbus?d31:f2/f4) .......................................................................................... 567 15.1.11 sid?subsystem identification register (smbus?d31:f2/f4) .......................................................................................... 567 15.1.12 int_ln?inte rrupt line register (smbus?d31:f 3)........................................... 567 15.1.13 int_pn?interrupt pin register (smb us?d31:f3) ............................................ 567 15.1.14 hostc?host configuration register (smbus?d31:f3) .................................. 568 15.2 smbus i/o registers ........................................................................................................ 569 15.2.1 hst_sts?host status register (smbus?d31:f3).......................................... 570 15.2.2 hst_cnt?host control register (s mbus?d31:f3)........................................ 571 15.2.3 hst_cmd?host command register (smbus?d31:f3) .................................. 573 15.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) ............................................................................................... 573 15.2.5 hst_d0?host data 0 register (smb us?d31:f3)............................................ 573 15.2.6 hst_d1?host data 1 register (smb us?d31:f3)............................................ 573 15.2.7 host_block_db?host block data byte register (smbus?d31:f3) ............................................................................................... 574 15.2.8 pec?packet error check (pec) register (smbus?d31:f3) ............................................................................................... 574 15.2.9 rcv_slva?receive slave address register (smbus?d31:f3) ............................................................................................... 575 15.2.10 slv_data?receive slav e data register (smbus?d 31:f3) .......................... 575 15.2.11 aux_sts?auxiliary status register (smbus?d31:f3) ................................... 575
intel ? i/o controller hub 6 (ich6) family datasheet 25 contents 15.2.12 aux_ctl?auxiliary cont rol register (smbus?d31:f3) ..................................576 15.2.13 smlink_pin_ctl?smlink pin control register (smbus?d31:f3) ...............................................................................................576 15.2.14 smbus_pin_ctl?smb us pin control register (smbus?d31:f3) ...............................................................................................577 15.2.15 slv_sts?slave status register (s mbus?d31:f3).........................................577 15.2.16 slv_cmd?slave comma nd register (smbus?d31:f3) .................................578 15.2.17 notify_daddr?notify device address register (smbus?d31:f3) ...............................................................................................578 15.2.18 notify_dlow?notify data low byte register (smbus?d31:f3) ...............................................................................................579 15.2.19 notify_dhigh?notify data high byte register (smbus?d31:f3) ...............................................................................................579 16 ac ?97 audio controlle r registers (d30:f2) .............................................................581 16.1 ac ?97 audio pci configuration space (audio?d30:f2) ...............................................................................................................58 1 16.1.1 vid?vendor identificat ion register (audio?d30:f2) ........................................582 16.1.2 did?device identification register (audio?d30:f2).........................................582 16.1.3 pcicmd?pci command register (audio ?d30:f2) .........................................583 16.1.4 pcists?pci status register (audio ?d30:f2).................................................584 16.1.5 rid?revision identification register (audio?d30:f2)......................................585 16.1.6 pi?programming interface register (a udio?d30:f2) .......................................585 16.1.7 scc?sub class code register (audio?d 30:f2) .............................................585 16.1.8 bcc?base class code register (audi o?d30:f2)............................................585 16.1.9 headtyp?header type register (a udio?d30:f2) .........................................586 16.1.10 nambar?native audio mixer base address register (audio?d30:f2) ..................................................................................................586 16.1.11 nabmbar?native audio bu s mastering base address register (audio?d30:f2) ........................ ...........................................................587 16.1.12 mmbar?mixer ba se address register (audio?d3 0:f2) .................................587 16.1.13 mbbar?bus master base address register (audio?d30:f2) ..................................................................................................588 16.1.14 svid?subsystem vendor identification register (audio?d30:f2) ..................................................................................................588 16.1.15 sid?subsystem identification register (audio?d30:f2) ..................................589 16.1.16 cap_ptr?capabilities po inter register (audio?d30:f2) ...............................589 16.1.17 int_ln?interrupt line register (aud io?d30:f2) .............................................589 16.1.18 int_pn?interrup t pin register (audio?d30:f2)...............................................590 16.1.19 pcid?programmable codec identification register (audio?d30:f2) ..................................................................................................590 16.1.20 cfg?configuration register (audio?d 30:f2) ..................................................590 16.1.21 pid?pci power manageme nt capability identification register (audio?d30:f2) ........................ ...........................................................591 16.1.22 pc?power management capabilities register (audio?d30:f2) ..................................................................................................591 16.1.23 pcs?power management control and status register (audio?d30:f2) ..................................................................................................592 16.2 ac ?97 audio i/o space (d30:f2).....................................................................................593 16.2.1 x_bdbar?buffer descrip tor base address register (audio?d30:f2) ..................................................................................................596
26 intel ? i/o controller hub 6 (ich 6) family datasheet contents 16.2.2 x_civ?current index va lue register (audio?d30:f2) ..................................... 597 16.2.3 x_lvi?last valid inde x register (audio?d30:f2) ............................................ 597 16.2.4 x_sr?status register (audio?d30:f2) ............................................................ 598 16.2.5 x_picb?position in current buffer register (audio?d30:f2).................................................................................................. 599 16.2.6 x_piv?prefetched index value regist er (audio?d30:f2)................................ 599 16.2.7 x_cr?control register (audio?d30:f2) .......................................................... 600 16.2.8 glob_cnt?global contro l register (audio?d30:f2) .................................... 601 16.2.9 glob_sta?global status register (audio?d30:f2) ...................................... 603 16.2.10 cas?codec access semaphore register (audio?d30:f2)............................. 605 16.2.11 sdm?sdata_in map regi ster (audio?d30:f2) ............................................. 605 17 ac ?97 modem controller registers (d30:f3) .......................................................... 607 17.1 ac ?97 modem pci configuration space (d30:f3) .......................................................... 607 17.1.1 vid?vendor identifica tion register (modem?d30:f3) ..................................... 608 17.1.2 did?device identification register (modem?d30:f3)...................................... 608 17.1.3 pcicmd?pci command register (m odem?d30:f3) ...................................... 608 17.1.4 pcists?pci status register (modem ?d30:f3).............................................. 609 17.1.5 rid?revision identification register (modem?d30:f3)................................... 610 17.1.6 pi?programming interface register (modem?d30:f3) .................................... 610 17.1.7 scc?sub class code register (mode m?d30:f3) .......................................... 610 17.1.8 bcc?base class code register (modem?d30:f3)......................................... 610 17.1.9 headtyp?header type register (modem?d30:f3) ...................................... 611 17.1.10 mmbar?modem mixer base address register (modem?d30:f3) ............................................................................................... 611 17.1.11 mbar?modem base ad dress register (modem?d30 :f3) .............................. 612 17.1.12 svid?subsystem vendor identification register (modem?d30:f3) ............................................................................................... 612 17.1.13 sid?subsystem identification regist er (modem?d30:f3) .... ........................... 613 17.1.14 cap_ptr?capabilities po inter register (modem?d30:f3) ............................ 613 17.1.15 int_ln?inte rrupt line register (modem?d30:f3 ) .......................................... 613 17.1.16 int_pin?interrupt pin register (m odem?d30:f3)........................................... 614 17.1.17 pid?pci power manageme nt capability identification register (modem?d30:f3)......................... ........................................................ 614 17.1.18 pc?power managemen t capabilities register (modem?d30:f3) ............................................................................................... 614 17.1.19 pcs?power management control and status register (modem?d30:f3) ............................................................................................... 615 17.2 ac ?97 modem i/o space (d30:f3).................................................................................. 616 17.2.1 x_bdbar?buffer descriptor list base address register (modem?d30:f3) ............................................................................................... 618 17.2.2 x_civ?current index va lue register (modem?d30:f 3) .................................. 618 17.2.3 x_lvi?last valid inde x register (modem?d30:f3) ......................................... 618 17.2.4 x_sr?status register (modem?d30:f3) ......................................................... 619 17.2.5 x_picb?position in current buffer register (modem?d30:f3) ............................................................................................... 620 17.2.6 x_piv?prefetch index value register (modem?d30:f3) ............................................................................................... 620 17.2.7 x_cr?control register (modem?d30:f3) ....................................................... 621 17.2.8 glob_cnt?global control register (modem?d30:f3).................................. 622 17.2.9 glob_sta?global stat us register (modem?d30:f3) ................................... 623
intel ? i/o controller hub 6 (ich6) family datasheet 27 contents 17.2.10 cas?codec access semaphore register (modem?d30:f3) ...............................................................................................625 18 intel ? high definition audio cont roller registers (d27:f0) ...............................627 18.1 intel ? high definition audio pci configuration space (intel ? high definition audio? d27:f0).............. ..............................................................627 18.1.1 vid?vendor identification register (intel ? high definition audio controller?d27: f0) ...............................................629 18.1.2 did?device identification register (intel ? high definition audio controller?d27: f0) ...............................................629 18.1.3 pcicmd?pci command register (intel ? high definition audio controller?d27: f0) ...............................................629 18.1.4 pcists?pci status register (intel ? high definition audio controller?d27: f0) ...............................................630 18.1.5 rid?revision identification register (intel ? high definition audio controller?d27: f0) ...............................................630 18.1.6 pi?programming interface register (intel ? high definition audio controller?d27: f0) ...............................................631 18.1.7 scc?sub class code register (intel ? high definition audio controller?d27: f0) ...............................................631 18.1.8 bcc?base class code register (intel ? high definition audio controller?d27: f0) ...............................................631 18.1.9 cls?cache line size register (intel ? high definition audio controller?d27: f0) ...............................................631 18.1.10 lt?latency timer register (intel ? high definition audio controller?d27: f0) ...............................................632 18.1.11 headtyp?header type register (intel ? high definition audio controller?d27: f0) ...............................................632 18.1.12 hdbarl?intel ? high definition audio lower base address register (intel ? high definition audio controller?d27: f0) ...............................................632 18.1.13 hdbaru?intel ? high definition audio upper base address register (intel ? high definition audio controller?d27: f0) ...............................................632 18.1.14 svid?subsystem vendor identification register (intel ? high definition audio controller?d27: f0) ...............................................633 18.1.15 sid?subsystem identification register (intel ? high definition audio controller?d27: f0) ...............................................633 18.1.16 capptr?capabilities poin ter register (audio?d30:f2 ) ............. ............ ........633 18.1.17 intln?interrupt line register (intel ? high definition audio controller?d27: f0) ...............................................634 18.1.18 intpn?interrupt pin register (intel ? high definition audio controller?d27: f0) ...............................................634 18.1.19 hdctl?intel ? high definition audio control register (intel ? high definition audio controller?d27: f0) ...............................................635 18.1.20 tcsel?traffic cl ass select register (intel ? high definition audio controller?d27: f0) ...............................................636 18.1.21 pid?pci power manageme nt capability id register (intel ? high definition audio controller?d27: f0) ...............................................637 18.1.22 pc?power management capabilities register (intel ? high definition audio controller?d27: f0) ...............................................637
28 intel ? i/o controller hub 6 (ich 6) family datasheet contents 18.1.23 pcs?power management control and status register (intel ? high definition audio controller?d2 7:f0) ............................................... 638 18.1.24 mid?msi cap ability id register (intel ? high definition audio controller?d2 7:f0) ............................................... 638 18.1.25 mmc?msi message control register (intel ? high definition audio controller?d2 7:f0) ............................................... 639 18.1.26 mmla?msi message lower address register (intel ? high definition audio controller?d2 7:f0) ............................................... 639 18.1.27 mmua?msi message upper address register (intel ? high definition audio controller?d2 7:f0) ............................................... 639 18.1.28 mmd?msi message data register (intel ? high definition audio controller?d2 7:f0) ............................................... 639 18.1.29 pxid?pci express* capability id register (intel ? high definition audio controller?d2 7:f0) ............................................... 640 18.1.30 pxc?pci express* capabilities register (intel ? high definition audio controller?d2 7:f0) ............................................... 640 18.1.31 devcap?device capabilities register (intel ? high definition audio controller?d2 7:f0) ............................................... 641 18.1.32 devc?device control register (intel ? high definition audio controller?d2 7:f0) ............................................... 642 18.1.33 devs?device status register (intel ? high definition audio controller?d2 7:f0) ............................................... 643 18.1.34 vccap?virtual channel enhanced capability header (intel ? high definition audio controller?d2 7:f0) ............................................... 643 18.1.35 pvccap1?port vc capability register 1 (intel ? high definition audio controller?d2 7:f0) ............................................... 644 18.1.36 pvccap2?port vc capability register 2 (intel ? high definition audio controller?d2 7:f0) ............................................... 644 18.1.37 pvcctl?port vc control register (intel ? high definition audio controller?d2 7:f0) ............................................... 644 18.1.38 pvcsts?port vc status register (intel ? high definition audio controller?d2 7:f0) ............................................... 645 18.1.39 vc0cap?vc0 resour ce capability register (intel ? high definition audio controller?d2 7:f0) ............................................... 645 18.1.40 vc0ctl?vc0 resource control register (intel ? high definition audio controller?d2 7:f0) ............................................... 645 18.1.41 vc0sts?vc0 reso urce status register (intel ? high definition audio controller?d2 7:f0) ............................................... 646 18.1.42 vcicap?vci resource capability register (intel ? high definition audio controller?d2 7:f0) ............................................... 646 18.1.43 vcictl?vci resour ce control register (intel ? high definition audio controller?d2 7:f0) ............................................... 647 18.1.44 vcists?vci resour ce status register (intel ? high definition audio controller?d2 7:f0) ............................................... 647 18.1.45 rccap?root complex link declaration enhanced capability header register (intel ? high definition audio controller?d27:f0) ... 647 18.1.46 esd?element self description register (intel ? high definition audio controller?d2 7:f0) ............................................... 648 18.1.47 l1desc?link 1 description register (intel ? high definition audio controller?d2 7:f0) ............................................... 648 18.1.48 l1addl?link 1 lower address register (intel ? high definition audio controller?d2 7:f0) ............................................... 648
intel ? i/o controller hub 6 (ich6) family datasheet 29 contents 18.1.49 l1addu?link 1 upper address register (intel ? high definition audio controller?d27: f0) ...............................................649 18.2 intel ? high definition audio memory mapped configuration registers (intel ? high definition audio? d27:f0).............. ..............................................................649 18.2.1 gcap?global capabilities register (intel ? high definition audio controller?d27: f0) ...............................................653 18.2.2 vmin?minor version register (intel ? high definition audio controller?d27: f0) ...............................................653 18.2.3 vmaj?major version register (intel ? high definition audio controller?d27: f0) ...............................................653 18.2.4 outpay?output payl oad capability register (intel ? high definition audio controller?d27: f0) ...............................................654 18.2.5 inpay?input payload capability register (intel ? high definition audio controller?d27: f0) ...............................................654 18.2.6 gctl?global control register (intel ? high definition audio controller?d27: f0) ...............................................655 18.2.7 wakeen?wake enable register (intel ? high definition audio controller?d27: f0) ...............................................656 18.2.8 statests?state change status register (intel ? high definition audio controller?d27: f0) ...............................................656 18.2.9 gsts?global status register (intel ? high definition audio controller?d27: f0) ...............................................656 18.2.10 intctl?interrupt control register (intel ? high definition audio controller?d27: f0) ...............................................657 18.2.11 intsts? interrupt status register (intel ? high definition audio controller?d27: f0) ...............................................658 18.2.12 walclk?wall clock counter register (intel ? high definition audio controller?d27: f0) ...............................................658 18.2.13 ssync?stream sync hronization register (intel ? high definition audio controller?d27: f0) ...............................................659 18.2.14 corblbase?corb lower base address register (intel ? high definition audio controller?d27: f0) ...............................................660 18.2.15 corbubase?corb uppe r base address register (intel ? high definition audio controller?d27: f0) ...............................................660 18.2.16 corbrp?corb wr ite pointer register (intel ? high definition audio controller?d27: f0) ...............................................660 18.2.17 corbrp?corb read pointer register (intel ? high definition audio controller?d27: f0) ...............................................661 18.2.18 corbctl?corb control register (intel ? high definition audio controller?d27: f0) ...............................................661 18.2.19 corbst?corb status register (intel ? high definition audio controller?d27: f0) ...............................................662 18.2.20 corbsize?corb size register (intel ? high definition audio controller?d27: f0) ...............................................662 18.2.21 rirblbase?rirb lowe r base addres s register (intel ? high definition audio controller?d27: f0) ...............................................662 18.2.22 rirbubase?rirb upper base address register (intel ? high definition audio controller?d27: f0) ...............................................663 18.2.23 rirbwp?rirb write pointer register (intel ? high definition audio controller?d27: f0) ...............................................663 18.2.24 rintcnt?response in terrupt count register (intel ? high definition audio controller?d27: f0) ...............................................663
30 intel ? i/o controller hub 6 (ich 6) family datasheet contents 18.2.25 rirbctl?rirb control register (intel ? high definition audio controller?d2 7:f0) ............................................... 664 18.2.26 rirbsts?rirb status register (intel ? high definition audio controller?d2 7:f0) ............................................... 664 18.2.27 rirbsize?rirb size register (intel ? high definition audio controller?d2 7:f0) ............................................... 665 18.2.28 ic?immediate command register (intel ? high definition audio controller?d2 7:f0) ............................................... 665 18.2.29 ir?immediate response register (intel ? high definition audio controller?d2 7:f0) ............................................... 665 18.2.30 irs?immediate command status register (intel ? high definition audio controller?d2 7:f0) ............................................... 666 18.2.31 dplbase?dma position lowe r base address register (intel ? high definition audio controller?d2 7:f0) ............................................... 666 18.2.32 dpubase?dma position up per base address register (intel ? high definition audio controller?d2 7:f0) ............................................... 667 18.2.33 sdctl?stream descri ptor control register (intel ? high definition audio controller?d2 7:f0) ............................................... 667 18.2.34 sdsts?stream descriptor status register (intel ? high definition audio controller?d2 7:f0) ............................................... 669 18.2.35 sdlpib?stream descripto r link position in buffer register (intel ? high definition audio controller?d27:f0) ................................ 670 18.2.36 sdcbl?stream descriptor cy clic buffer length register (intel ? high definition audio controller?d2 7:f0) ............................................... 670 18.2.37 sdlvi?stream descriptor last valid index register (intel ? high definition audio controller?d2 7:f0) ............................................... 671 18.2.38 sdfifow?stream descript or fifo watermark register (intel ? high definition audio controller?d2 7:f0) ............................................... 671 18.2.39 sdfifos?stream descri ptor fifo size register (intel ? high definition audio controller?d2 7:f0) ............................................... 672 18.2.40 sdfmt?stream descr iptor format register (intel ? high definition audio controller?d2 7:f0) ............................................... 673 18.2.41 sdbdpl?stream descriptor buffer descr iptor list pointer lower base address register (intel ? high definition audio controller?d2 7:f0) ............................................... 674 18.2.42 sdbdpu?stream descriptor buffer descriptor list pointer upper base address register (intel ? high definition audio controller ?d27:f0) ............................................................................................................ 674 19 pci express* configuration registers ....................................................................... 675 19.1 pci express* configuration registers (pci express?d28:f0/f1/f2/f3) .................................................................................... 675 19.1.1 vid?vendor iden tification register (pci express?d28:f0/f1/f2/f3) ....................................................................... 678 19.1.2 did?device identification register (pci express?d28:f0/f1/f2/f3) ....................................................................... 678 19.1.3 pcicmd?pci command register (pci express?d28:f0/f1/f2/f3) ....................................................................... 679 19.1.4 pcists?pci status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 680 19.1.5 rid?revision iden tification register (pci express?d28:f0/f1/f2/f3) ....................................................................... 681
intel ? i/o controller hub 6 (ich6) family datasheet 31 contents 19.1.6 pi?programming interface register (pci express?d28:f0/f1/f2/f3)................ ........................................................681 19.1.7 scc?sub class code register (pci express?d28:f0/f1/f2/f3)................ ........................................................681 19.1.8 bcc?base class code register (pci express?d28:f0/f1/f2/f3)................ ........................................................681 19.1.9 cls?cache line size register (pci express?d28:f0/f1/f2/f3)................ ........................................................682 19.1.10 plt?primary latency timer register (pci express?d28:f0/f1/f2/f3)................ ........................................................682 19.1.11 headtyp?header type register (pci express?d28:f0/f1/f2/f3)................ ........................................................682 19.1.12 bnum?bus nu mber register (pci express?d28:f0/f1/f2/f3)................ ........................................................682 19.1.13 iobl?i/o base and limit register (pci express?d28:f0/f1/f2/f3)................ ........................................................683 19.1.14 ssts?secondar y status register (pci express?d28:f0/f1/f2/f3)................ ........................................................684 19.1.15 mbl?memory base and limit register (pci express?d28:f0/f1/f2/f3)................ ........................................................685 19.1.16 pmbl?prefetchable memory base and limit register (pci express?d28:f0/f1/f2/f3)................ ........................................................685 19.1.17 pmbu32?prefetchable memory base upper 32 bits register (pci express?d28:f0/f1/f2/f3) .........................................................686 19.1.18 pmlu32?prefetchable memory limit upper 32 bits register (pci express?d28:f0/f1/f2/f3) .........................................................686 19.1.19 capp?capabilities li st pointer register (pci express?d28:f0/f1/f2/f3)................ ........................................................686 19.1.20 intr?interrupt information register (pci express?d28:f0/f1/f2/f3)................ ........................................................686 19.1.21 bctrl?bridge control register (pci express?d28:f0/f1/f2/f3)................ ........................................................687 19.1.22 clist?capabilities list register (pci express?d28:f0/f1/f2/f3)................ ........................................................688 19.1.23 xcap?pci express* capabilities register (pci express?d28:f0/f1/f2/f3)................ ........................................................688 19.1.24 dcap?device capabilities register (pci express?d28:f0/f1/f2/f3)................ ........................................................689 19.1.25 dctl?device control register (pci express?d28:f0/f1/f2/f3)................ ........................................................690 19.1.26 dsts?device status register (pci express?d28:f0/f1/f2/f3)................ ........................................................691 19.1.27 lcap?link capabilities register (pci express?d28:f0/f1/f2/f3)................ ........................................................692 19.1.28 lctl?link control register (pci express?d28:f0/f1/f2/f3)................ ........................................................693 19.1.29 lsts?link status register (pci express?d28:f0/f1/f2/f3)................ ........................................................694 19.1.30 slcap?slot capabilities register (pci express?d28:f0/f1/f2/f3)................ ........................................................695 19.1.31 slctl?slot control register (pci express?d28:f0/f1/f2/f3)................ ........................................................696
32 intel ? i/o controller hub 6 (ich 6) family datasheet contents 19.1.32 slsts?slot status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 697 19.1.33 rctl?root control register (pci express?d28:f0/f1/f2/f3) ....................................................................... 698 19.1.34 rsts?root status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 698 19.1.35 mid?message signaled in terrupt identifiers register (pci express?d28:f0/f1/f2/f3) ....................................................................... 699 19.1.36 mc?message signaled interrupt message control register (pci express?d28:f0/f1/f2/f3) ....................................................................... 699 19.1.37 ma?message signaled interrupt message address register (pci express?d28:f0/f1/f2/f3) ......................................................... 699 19.1.38 md?message signaled interrupt message data register (pci express?d28:f0/f1/f2/f3) ....................................................................... 700 19.1.39 svcap?subsystem vendor capability register (pci express?d28:f0/f1/f2/f3) ....................................................................... 700 19.1.40 svid?subsystem vendor identification register (pci express?d28:f0/f1/f2/f3) ....................................................................... 700 19.1.41 pmcap?power managem ent capability register (pci express?d28:f0/f1/f2/f3) ....................................................................... 700 19.1.42 pmc?pci power managem ent capabilities register (pci express?d28:f0/f1/f2/f3) ....................................................................... 701 19.1.43 pmcs?pci power management control and status register (pci express?d28:f0/f1/f2/f3) ......................................................... 702 19.1.44 mpc?miscellaneous port configuration register (pci express?d28:f0/f1/f2/f3) ....................................................................... 703 19.1.45 smscs?smi/sci status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 704 19.1.46 vch?virtual channel capability header register (pci express?d28:f0/f1/f2/f3) ....................................................................... 704 19.1.47 vcap2?virtual chan nel capability 2 register (pci express?d28:f0/f1/f2/f3) ....................................................................... 704 19.1.48 pvc?port virtual channel control register (pci express?d28:f0/f1/f2/f3) ....................................................................... 705 19.1.49 pvs ? port virtual channel status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 705 19.1.50 v0cap ? virtual channel 0 resource capab ility register (pci express?d28:f0/f1/f2/f3) ....................................................................... 705 19.1.51 v0ctl ? virtual channel 0 resource control register (pci express?d28:f0/f1/f2/f3) ....................................................................... 706 19.1.52 v0sts ? virtual channel 0 resource status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 706 19.1.53 ues ? uncorrectable error status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 707 19.1.54 uem ? uncorr ectable error mask (pci express?d28:f0/f1/f2/f3) ....................................................................... 708 19.1.55 uev ? uncorrecta ble error severity (pci express?d28:f0/f1/f2/f3) ....................................................................... 709 19.1.56 ces ? correctable error status register (pci express?d28:f0/f1/f2/f3) ....................................................................... 710 19.1.57 cem ? correctable error mask register (pci express?d28:f0/f1/f2/f3) ....................................................................... 710
intel ? i/o controller hub 6 (ich6) family datasheet 33 contents 19.1.58 aecc ? advanced error ca pabilities and control register (pci express?d28:f0/f1/f2/f3)................ ........................................................711 19.1.59 res ? root error status register (pci express?d28:f0/f1/f2/f3)................ ........................................................711 19.1.60 rctcl ? root complex to pology capability list register (pci express?d28:f0/f1/f2/f3)................ ........................................................711 19.1.61 esd ? element self description register (pci express?d28:f0/f1/f2/f3)................ ........................................................712 19.1.62 uld ? upstream link description register (pci express?d28:f0/f1/f2/f3)................ ........................................................712 19.1.63 ulba ? upstream link base address register (pci express?d28:f0/f1/f2/f3)................ ........................................................713 19.1.64 pciecr1 ? pci expres s configuration register 1 (pci express?d28:f0/f1/f2/f3)................ ........................................................713 19.1.65 pciecr2 ? pci expres s configuration register 2 (pci express?d28:f0/f1/f2/f3)................ ........................................................713 20 high precision even t timer registers ........................................................................715 20.1 memory mapped registers...............................................................................................716 20.1.1 gcap_id?general capabilities and identification register...............................717 20.1.2 gen_conf?general conf iguration register....................................................717 20.1.3 gintr_sta?genera l interrupt status register ................................................718 20.1.4 main_cnt?main counter value register .........................................................718 20.1.5 timn_conf?timer n configuration and capabilities register .........................719 20.1.6 timn_comp?timer n comp arator value register............................................721 21 ballout definition .................................................................................................................723 22 electrical characteristics .................................................................................................733 22.1 thermal specifications ..................................................................................................... 733 22.2 absolute maximum ratings ... ...........................................................................................733 22.3 dc characteristics .................................... ..................................................................... ...734 22.4 ac characteristics ......................................................................................................... ...743 22.5 timing diagrams.......................................... .................................................................. ...759 23 package information ..........................................................................................................777 24 testability ............................................................................................................................... 779 24.1 xor chain test mode description...................................................................................779 24.1.1 xor chain testability algorithm exampl e ..........................................................780 24.2 xor chain tables ........................................................................................................... .781
34 intel ? i/o controller hub 6 (ich 6) family datasheet contents figures 1 desktop configuration ......................................................................................................... ....... 42 2 mobile configuration.......................................................................................................... ......... 42 2-1 intel ? ich6 interface signals blo ck diagram (desktop)............................................................. 54 2-2 intel ? ich6-m interface signals block diagram (mob ile only)................................................... 55 2-3 example external rtc circuit ................................................................................................ .... 76 4-1 desktop conceptual system clock diagram....... ....................................................................... 96 4-2 mobile conceptual clo ck diagram ............................................................................................. 96 5-1 generation of serr# to platform ............................................................................................ 1 03 5-2 64-word eeprom read instruct ion waveform............ ................ ................ ................ ........... 110 5-3 lpc interface diagram ....................................................................................................... ...... 116 5-4 intel ? ich6 dma controller ...................................................................................................... 121 5-5 dma request assertion through ldrq# ............ ..................................................................... 124 5-6 coprocessor error timing diagram ..................... ..................................................................... 14 8 5-7 physical region descriptor table entry ........... ........................................................................ 181 5-8 sata power states........................................................................................................... ....... 189 5-9 usb legacy keyboard flow di agram ...................................................................................... 199 5-10 intel ? ich6-usb port connections ......................................................................................... 206 5-11intel ? ich6-based audio codec ?97 specification, version 2.3 ............................................... 227 5-12 ac ?97 2.3 controller-codec connection ................................................................................. 229 5-13 ac-link protocol........................................................................................................... ............ 230 5-14 ac-link powerdown timing ................................................................................................... .. 231 5-15 sdin wake signaling ........................................................................................................ ....... 232 5-16intel ? high definition audio link protocol example ................................................................. 234 21-1intel ? ich6 preliminary ballo ut (topview?left side)................................................................ 724 21-2intel ? ich6 preliminary ballo ut (topview?right side) ............................................................. 725 22-1 clock timing............................................................................................................... .............. 759 22-2valid delay from rising clock edge ......................................................................................... 759 22-3 setup and hold times ....................................................................................................... ....... 759 22-4 float delay ................................................................................................................ ............... 760 22-5 pulse width ................................................................................................................ .............. 760 22-6 output enable delay ................................. ....................................................................... ........ 760 22-7 ide pio mode ............................................................................................................... ........... 761 22-8 ide multiword dma .......................................................................................................... ........ 761 22-9 ultra ata mode (drive initiating a burst read) ........................................................................ 762 22-10ultra ata mode (sustained burst).......................................................................................... 762 22-11ultra ata mode (pausing a dma burst)......... ........................................................................ 763 22-12ultra ata mode (terminating a dma burst)........................................................................... 763 22-13usb rise and fall times................................................................................................... ..... 764 22-14usb jitter................................................................................................................ ................ 764 22-15usb eop width............................................................................................................. ......... 764 22-16smbus transaction......................................................................................................... ........ 765 22-17smbus timeout ............................................................................................................. ......... 765 22-18power sequencing and reset signal timings (desktop only)............................................... 766 22-19power sequencing and reset signal timings (mobile only) ................................................. 767 22-20g3 (mechanical off) to s0 timings (desktop only)................................................................ 768 22-21g3 (mechanical off) to s0 timings (mobile only) .................................................................. 769 22-22s0 to s1 to s0 timing . .................................................................................................... ........ 769 22-23s0 to s5 to s0 timings, s3 cold (desktop only)..................................................................... 770 22-24s0 to s5 to s0 timings, s3 hot (desktop only)...................................................................... 771
intel ? i/o controller hub 6 (ich6) family datasheet 35 contents 22-25s0 to s5 to s0 timings, s3 cold (mobile only).......................................................................772 22-26s0 to s5 to s0 timings, s3 hot (mobile only) ........................................................................773 22-27c0 to c2 to c0 timings (m obile only) ....................................................................................77 3 22-28c0 to c3 to c0 timings (m obile only) ....................................................................................77 4 22-29c0 to c4 to c0 timings (m obile only) ....................................................................................77 4 22-30ac ?97 data input and output timings ...................................................................................775 22-31intel ? high definition audio input and output timings ...........................................................775 23-1intel ? ich6 package (top and side views) .............................................................................777 23-2intel ? ich6 package (bottom view) .........................................................................................778 24-1xor chain test mode selection, entry and te sting................................................................779 24-2 example xor chain circuitry ................................................................................................ ..780 tables 1-1 industry specifications..................................................................................................... ........... 43 1-2 pci devices and functions ................................................................................................... ..... 47 2-1 direct media interface signals.............................................................................................. ...... 56 2-2 pci express* signals........................................................................................................ .......... 56 2-3 lan connect interface signals............................................................................................... .... 57 2-4 eeprom interface signals .... ................ ................ ................. ................ ................ ............... .... 57 2-5 firmware hub interface signals .............................................................................................. ... 57 2-6 pci interface signals ....................................................................................................... ........... 58 2-7 serial ata interface signals................................................................................................ ....... 60 2-8 ide interface signals ....................................................................................................... ........... 61 2-9 lpc interface signals ....................................................................................................... .......... 62 2-10 interrupt signals.......................................................................................................... ................ 63 2-11 usb interface signals...................................................................................................... ........... 64 2-12power management interface signals........................................................................................ 6 5 2-13 processor interface signals................................................................................................ ........ 67 2-14 sm bus interface signals ................................................................................................... ........68 2-15 system management interface signals ...................................................................................... 68 2-16 real time clock interface .................................................................................................. ........ 69 2-17 other clocks ............................................................................................................... ................ 69 2-18 miscellaneous signals ...................................................................................................... .......... 69 2-19ac ?97/intel ? high definition audio link signals ........................................................................ 70 2-20 general purpose i/o signals ................................................................................................ ...... 71 2-21 power and ground signals................................................................................................... ...... 73 2-22 functional strap definitions............................................................................................... ......... 74 3-1 integrated pull-up and pull-down resistors .............................................................................. 79 3-2 ide series termination resistors.............. .............................................................................. ... 80 3-3 power plane and states for output and i/o signals for desktop configurations .......................81 3-4 power plane and states for output and i/o signals for mobile configurations.......................... 85 3-5 power plane for input signals for desktop configurations......................................................... 89 3-6 power plane for input signals for mobile configurations ........................................................... 91 4-1 intel ? ich6 and system clock domains ................ .................................................................... 95 5-1 pci bridge initiator cycle types............................................................................................ ..... 97 5-2 msi vs. pci irq actions..................................................................................................... ......101 5-3 advanced tco functionality .................................................................................................. ..112 5-4 lpc cycle types supported ................................................................................................... .117
36 intel ? i/o controller hub 6 (ich 6) family datasheet contents 5-5 start field bit definitions ................................................................................................. ......... 117 5-6 cycle type bit definitions.................................................................................................. ....... 118 5-7 transfer size bit definition ................................................................................................ ....... 118 5-8 sync bit definition ......................................................................................................... ......... 119 5-9 dma transfer size ........................................................................................................... ........ 123 5-10address shifting in 16-bit i/ o dma transfers .......................................................................... 123 5-11counter operating mo des .................................................................................................... .... 129 5-12interrupt controller core connections...................................................................................... 131 5-13interrupt status registers ................................................................................................. ........ 132 5-14content of inte rrupt vector byte ........................................................................................... .... 132 5-15apic interrupt mapping ....... .............................................................................................. ....... 138 5-16interrupt message address fo rmat .......................................................................................... 1 40 5-17interrupt message data form at.............................................................................................. .. 141 5-18 stop frame explanation ..................................................................................................... ...... 142 5-19data frame format .......................................................................................................... ........ 143 5-20configuration bits reset by rtcrst# assertio n .................................................................... 146 5-21 init# going active ......................................................................................................... .......... 148 5-22 nmi sources................................................................................................................ ............. 149 5-23 dp signal differences ...................................................................................................... ........ 149 5-24general power states for systems using intel ? ich6 ............................................................. 151 5-25state transition rules for intel ? ich6 ...................................................................................... 152 5-26 system power plane ......................................................................................................... ....... 153 5-27 causes of smi# and sci ..................................................................................................... ..... 154 5-28 break events (mobile only) ................................................................................................. ..... 156 5-29 sleep types................................................................................................................ .............. 160 5-30 causes of wake events ...... ................................................................................................ ..... 161 5-31 gpi wake events ............................................................................................................ ......... 161 5-32transitions due to power failure ................. .......................................................................... .. 162 5-33 transitions due to power button .................. .......................................................................... .. 164 5-34 transitions due to ri# signal.............................................................................................. ..... 165 5-35write only registers with re ad paths in alt access mode ..... .............................................. 168 5-36pic reserved bits return va lues ............................................................................................ 169 5-37register write accesses in alt access mode ........................................................................ 170 5-38intel ? ich6 clock inputs........................................................................................................... 17 2 5-39heartbeat mess age data..................................................................................................... ..... 178 5-40 ide transaction timings (pci clocks) .................................................................................... 18 0 5-41interrupt/active bit interaction definition ................................................................................ .. 183 5-42 legacy replacement routing ................................................................................................. .191 5-43 bits maintained in low power states ....................................................................................... 1 98 5-44usb legacy keyboard state transitions ................................................................................. 200 5-45 uhci vs. ehci.............................................................................................................. ............ 201 5-46 debug port behavior ........................................................................................................ ........ 210 5-47 i 2 c block read ................................................................................................................... ...... 217 5-48 enable for smbalert# ............................... ........................................................................ .... 220 5-49enables for smbus slave writ e and smbus host events ....................................................... 220 5-50 enables for the host notify command ............. ........................................................................ 220 5-51 slave write registers ...................................................................................................... ......... 222 5-52 command types .............................................................................................................. ........ 222 5-53 read cycle format.......................................................................................................... ......... 223 5-54data values for slave read registers ......... ............................................................................ 22 4
intel ? i/o controller hub 6 (ich6) family datasheet 37 contents 5-55 host notify format......................................................................................................... ...........225 5-56 features supported by intel ? ich6 ..........................................................................................226 5-57 output tag slot 0.......................................................................................................... ............231 6-1 pci devices and functions ................................................................................................... ...238 6-2 fixed i/o ranges decoded by intel ? ich6 ..............................................................................240 6-3 variable i/o decode ranges .................................................................................................. ..242 6-4 memory decode ranges from processor perspe ctive.............................................................243 7-1 chipset configuration regist er memory map (memory space) . ..............................................247 8-1 lan controller pci register address map (lan controller?b1:d8:f0).................................281 8-2 configuration of subsystem id and subsystem vendor id via eeprom................................288 8-3 data register structure ..................................................................................................... .......292 8-4 intel ? ich6 integrated lan controller csr space register address map .............................293 8-5 self-test results format ........................... ......................................................................... ......299 8-6 statistical counters........................................................................................................ ...........306 8-7 asf pci configuration register address map (lan controller?b1:d8:f0) ...........................308 9-1 pci bridge register address map (pci-pci?d30:f0)............................................................325 10-1 lpc interface pci register address map (lpc i/f?d31:f0) .................................................343 10-2 dma registers.............................................................................................................. ............361 10-3 pic registers (lpc i/f?d31:f0)............................................................................................. 372 10-4 apic direct registers (lpc i/f?d31:f0)................................................................................380 10-5 apic indirect registers (lpc i/f?d31:f0) .............................................................................380 10-6 rtc i/o registers (lpc i/f?d31:f0) .....................................................................................385 10-7 rtc (standard) ram bank (lpc i/f?d31:f0) .......................................................................386 10-8processor interface pci register address m ap (lpc i/f?d31:f0) ........................................390 10-9power management pci regist er address map (pm?d31:f0)..............................................393 10-10apm register map .......................................................................................................... ........402 10-11acpi and legacy i/o register map ........................................................................................40 3 10-12tco i/o register address map .............................................................................................. 423 10-13registers to control gpio address map ........ ........................................................................430 11-1ide controller pci register address map (ide -d31:f1) .........................................................437 11-2 bus master ide i/o registers............................................................................................... ....451 12-1sata controller pci register address map (sata?d31:f2)..................................................455 12-1 sata indexed registers ............................... ...................................................................... .....475 12-2bus master ide i/o register address map ..............................................................................483 12-3 ahci register address map.................................................................................................. ...486 12-4generic host controller register address map ........................................................................486 12-5 port [3:0] dma register address map.............. ........................................................................49 1 13-1uhci controller pci regist er address map (usb?d29:f0/f1/f2/f3) ...................................507 13-2 usb i/o registers .......................................................................................................... ..........516 13-3run/stop, debug bit interaction swdbg (bit 5), run/stop (bit 0) operation..........................519 14-1 usb ehci pci register address map (usb ehci?d29:f7) .................................................527 14-2 enhanced host controller capability registers........................................................................544 14-3enhanced host contro ller operational register address map ................................................547 14-4 debug port register address map ...........................................................................................5 60 15-1smbus controller pci register address map (smbus?d31:f3)............................................563 15-2smbus i/o register address map.................... ........................................................................5 69 16-1ac ?97 audio pci register address map (audi o?d30:f2) .....................................................581 16-2 intel ? ich6 audio mixer register configuration.... ..................................................................593 16-3native audio bus master cont rol registers .............................................................................594 17-1ac ?97 modem pci register address map (modem?d30:f3)................................................607
38 intel ? i/o controller hub 6 (ich 6) family datasheet contents 17-2intel ? ich6 modem mixer register configuration .................................................................... 616 17-3 modem registers ............................................................................................................ ......... 617 18-1intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) ....................................................................................... 627 18-2intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) ....................................................................................... 649 19-1pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3) ............................................................................................ 675 20-1 memory-mapped registers .................................................................................................... .. 716 21-1intel ? ich6 ballout by signal name ......................................................................................... 726 22-1intel ? ich6 absolute maximum ratings................. .................................................................. 733 22-2 dc current characteristics................................................................................................. ...... 734 22-3dc current characteristics (mobile only) ........ ........................................................................ 735 22-4dc characteristic input signal association .. ............................................................................ 736 22-5 dc input characteristics................................................................................................... ........ 738 22-6dc characteristic output sign al association ........................................................................... 740 22-7 dc output characteristics ......................... ......................................................................... ...... 741 22-8 other dc characteristics................................................................................................... ....... 742 22-9 clock timings .............................................................................................................. ............. 743 22-10pci interface timing ...................................................................................................... ......... 745 22-11ide pio mode timings ...................................................................................................... ..... 745 22-12ide multiword dma timings ....................... .......................................................................... .. 746 22-13ultra ata timing (mode 0, mode 1, mode 2) ......................................................................... 747 22-14ultra ata timing (mode 3, mode 4, mode 5) ......................................................................... 749 22-15universal serial bus timing..................... .......................................................................... ..... 751 22-16sata interface timings ..... ............................................................................................... ...... 752 22-17smbus timing.............................................................................................................. ........... 752 22-19lpc timing ................................................................................................................ ............. 753 22-20miscellaneous timings................................ ..................................................................... ....... 753 22-18ac ?97 / intel ? high definition audio timing ........................................................................... 753 22-21(power sequencing and reset signal timings....................................................................... 754 22-22power management timings .................................................................................................. 756 24-1 xor test pattern example ................................................................................................... ... 780 24-2 xor chain #1 (req[4:1]# = 0000) .......................................................................................... 78 1 24-3 xor chain #2 (req[4:1]# = 0001) .......................................................................................... 78 2 24-4 xor chain #3 (req[4:1]# = 0010) .......................................................................................... 78 3 24-5 xor chain #4-1 (req[4:1]# = 0011) ....................................................................................... 784 24-6 xor chain #4-2 (req[4:1]# = 0011) ....................................................................................... 785 24-7 xor chain #5 (req[4:1]# = 0100) .......................................................................................... 78 6
intel ? i/o controller hub 6 (ich6) family datasheet 39 contents revision history revision description date -001 initial release. june 2004 -002 ? added ich6-m content ? removed support for wireless skus. ? added all specification clarific ations, changes and document changes from specification updates. january 2005
40 intel ? i/o controller hub 6 (ich 6) family datasheet contents intel ? ich6 family features ? new: direct me dia interface ? 10 gb/s each direction, full duplex ? transparent to software ? new: pci express* ? 4 pci express root ports ? fully pci express 1.0a compliant ? can be statically configured as 4x1, or 1x4 (enterprise applications only) ? two virtual channel support for full isochronous data transfers ? support for full 2.5 gb/s bandwidth in each direction per x1 lane ? module based hot-plug supported (e.g., expresscard*) ? pci bus interface ? supports pci rev 2.3 specification at 33 mhz ? new: seven available pci req/gnt pairs ? support for 64-bit addressing on pci using dac protocol ? new: integrated serial ata host controller ? four ports (desktop only) or two ports (mobile only). ? data transfer rates up to 1.5 gb/s (150 mb/s). ? integrated ahci controller (ich6-m / ich6r only) ? integrated ide controller ? independent timing of up to two drives ? ultra ata/100/66/33, bmide and pio modes ? tri-state modes to enable swap bay ? new: intel ? high definition audio interface ? pci express endpoint ? independent bus master logic for eight general purpose streams: four input and four output ? support three external codecs ? supports variable length stream slots ? supports multichannel, 32-bit sample depth, 192 khz sample rate output ? provides mic array support ? supports memory-based command/response transport ? allows for non-48 khz sampling output ? support for acpi device states ? ac-link for audio and telephony codecs ? support for three ac ?97 2.3 codecs. ? independent bus master logic for 8 channels (pcm in/out, pcm 2 in, mic 1 input, mic 2 input, modem in/out, s/pdif out) ? support for up to six channels of pcm audio output (full ac3 decode) ? supports wake-up events ? usb 2.0 ? includes four uhci host controllers, supporting eight external ports ? includes one ehci host controller that supports all eight ports ? includes one usb 2.0 high-speed debug port ? supports wake-up from sleeping states s1? s5 ? supports legacy keyboa rd/mouse software ? integrated lan controller ? integrated asf mana gement controller ? efm 2.0 ? lan connect interface (lci) ? 10/100 mb/s ethernet support ? power management logic ? acpi 2.0 compliant ? acpi-defined power states (c1, s1, s3?s5 for desktop and c1-c4, s1, s3?s5 for mobile) ? acpi power management timer ? (mobile only) support for ?intel speedstep ? technology? processor power control and ?deeper sleep? power state ? pci clkrun# and pme# support ? smi# generation ? all registers readable/restorable for proper resume from 0 v suspend states ? support for apm-based legacy power management for non-acpi desktop and mobile implementations ? external glue integration ? integrated pull-up, pull-down and series termination resistors on ide, processor i/f ? integrated pull-down and series resistors on usb ? enhanced dma controller ? two cascaded 8237 dma controllers ? supports lpc dma
intel ? i/o controller hub 6 (ich6) family datasheet 41 contents ? smbus ? new: flexible smbus/smlink architecture to optimize for asf ? provides independent manageability bus through smlink interface ? supports smbus 2.0 specification ? host interface allows processor to communicate via smbus ? slave interface allows an internal or external microcontroller to access system resources ? compatible with most two-wire components that are also i 2 c compatible ? high precision event timers ? advanced operating system interrupt scheduling ? timers based on 82c54 ? system timer, refresh request, speaker tone output ? real-time clock ? 256-byte battery-backed cmos ram ? integrated oscillator components ? lower power dc/dc converter implementation ? system tco reduction circuits ? timers to generate smi# and reset upon detection of system hang ? timers to detect im proper processor reset ? integrated processor frequency strap logic ? supports ability to disa ble external devices ? interrupt controller ? supports up to eight pci interrupt pins ? supports pci 2.3 message signaled interrupts ? two cascaded 82c59 with 15 interrupts ? integrated i/o apic capability with 24 interrupts ? supports processor system bus interrupt delivery ? 1.5 v operation with 3.3 v i/o ? 5 v tolerant buffers on ide, pci, and legacy signals ? integrated 1.5 v voltage regulator (intvr) for the suspend and lan wells ? integrated 2.5 v regulator for vcc2_5 ? firmware hub i/f suppor ts bios memory size up to 8 mbytes ? low pin count (lpc) i/f ? supports two master/dma devices. ? support for security device (trusted platform module) connected to lpc. ? gpio ? ttl, open-drain, inversion ? package 31x31 mm 609 mbga
42 intel ? i/o controller hub 6 (ich 6) family datasheet contents figure 1. desktop configuration figure 2. mobile configuration intel ? pci ex p r e s s gigabit ethernet intel ? ich6 system management (tco) ide smbus 2.0/i 2 c pow er management pci bu s ... clock generators s l o t s l o t ac ?97/intel ? high def inition audio codec(s) flas h bios lpc i/f super i/o sata (4 ports) pci express* x1 dmi (to (g)mch) tpm (optional) usb 2.0 (supports 8 usb ports) lan connect gpio other a sics (optional) in te l ? ich6 system management (tco) ide smbus 2.0/i 2 c pow er management pci bu s clock generators ac ?97/intel ? high definition audio codec(s) flash bios lpc i/f super i/o sata (2 ports) pci express* x1 dmi (to (g)mch) tpm (optional) usb 2.0 (supports 8 usb ports) lan connect gpio other a sics (optional) car dbus controller (& attached slots doc king station
intel ? i/o controller hub 6 (ich6) family datasheet 43 introduction 1 introduction this document is intended for original equi pment manufacturers and bios vendors creating intel ? i/o controller hub 6 (ich6) family (ich6, ich6r, and ich6-m) based products. this document is the datasheet for the following: ? intel ? 82801fb ich6 (ich6) ? intel ? 82801FR ich6 raid (ich6r) ? intel ? 82801fbm ich6 mobile (ich6-m) note: throughout this datasheet, ich6 is used as a ge neral ich6 term and refers to the 82801fb ich6, 82801FR ich6r, and 82801fbm ich6-m components, unless specifically noted otherwise. note: throughout this datasheet, the te rm ?desktop? refers to any impl ementation other than mobile, be it in a desktop, server, workstat ion, etc., unless specifically note d otherwise. the term ?mobile? refers to implementations using the intel 82801fbm ich6 mobile (ich6-m). this datasheet assumes a working knowledge of the vocabulary and princi ples of pci express*, usb, ide, ahci, sata, intel ? high definition audio, ac ?97, smbus, pci, acpi and lpc. although some details of these features are descri bed within this datasheet, refer to the individual industry specificat ions listed in table 1-1 for the complete details. table 1-1. industry specifications (sheet 1 of 2) specification location pci express* base specification, revision 1.0a http://www.pcisig.com/specifications low pin count interface specification, revision 1.1 (lpc) http://developer.intel.com/design/chipsets/ industry/lpc.htm audio codec ?97 component specif ication, version 2.3 (ac ?97) http://www.intel.com/labs/media/audio/ index.htm system management bus specific ation, version 2.0 (smbus) http://www.smbus.org/specs/ pci local bus specification, revision 2.3 (pci) http://www.pcisig.com/specifications pci mobile design guide, revision 1.1 http://www.pcisig.com/specifications pci power management specification, revision 1.1 http://www.pcisig.com/specifications universal serial bus revision 2.0 specification (usb) http://www.usb.org advanced configuration and power interface, version 2.0 (acpi) http://www.acpi.info/spec.htm universal host controller interface, revision 1.1 (uhci) http://developer.intel.com/design/usb/ uhci11d.htm enhanced host controller interfac e specification for universal serial bus, revision 1.0 (ehci) http://developer.intel.com/technology/usb/ ehcispec.htm serial ata specification, revision 1.0a http://www.serialata.org serial ata ii: extensions to serial ata 1.0, revision 1.0 http://www.serialata.org
44 intel ? i/o controller hub 6 (i ch6) family datasheet introduction chapter 1. introduction chapter 1 introduces the ich6 and provides information on manual organization and gives a general overview of the ich6. chapter 2. signal description chapter 2 provides a block diagram of the ich6/ich6- m and a detailed description of each signal. signals are arranged according to interface and details are provided as to the drive characteristics (input/output, open drain, etc.) of all signals. chapter 3. ich6 pin states chapter 3 provides a complete list of signals, their associated power well, their logic level in each suspend state, and their logic level before and after reset. chapter 4. system clock domains chapter 4 provides a list of each clock domain associat ed with the ich6 in an ich6 based system. chapter 5. functional description chapter 5 provides a detailed description of the func tions in the ich6. all pci buses, devices and functions in this document are abbrev iated using the following nomenclature; bus:device:function. this document abbreviates buses as b0 and b1, devices as d8, d27, d28, d29, d30 and d31 and functions as f0, f1, f2, f3, f4, f5, f6 and f7. for example device 31 function 0 is abbreviated as d31:f0, bus 1 device 8 function 0 is abbreviated as b1:d8:f0. generally, the bus number will not be used, and can be considered to be bus 0. note that the ich6?s external pci bus is typically bus 1, but may be assigned a different number depending upon system configuration. chapter 6. register and memory mappings chapter 6 provides an overview of the registers, fixe d i/o ranges, variable i/o ranges and memory ranges decoded by the ich6. chapter 7. chipset co nfiguration registers chapter 7 provides a detailed description of all regist ers and base functionality that is related to chipset configuration and not a sp ecific interface (such as lpc, pci, or pci express). it contains the root complex register block, which describe s the behavior of the upstream internal link. chapter 8. lan controller registers chapter 8 provides a detailed description of all register s that reside in the ich6?s integrated lan controller. the integrated lan controller resides on the ich6?s external pc i bus (typically bus 1) at device 8, function 0 (b1:d8:f0). chapter 9. pci-to-p ci bridge registers chapter 9 provides a detailed description of all register s that reside in the pci-to-pci bridge. this bridge resides at device 30, function 0 (d30:f0). alert standard format specification, version 1.03 http://www.dmtf.org/standards/asf at attachment - 6 with packet interface (ata/atapi - 6) http://t13.org (t13 1410d) ia-pc hpet (high precision ev ent timers) specification, revision 0.98a http://www.intel.com/labs/platcomp/hpet/ hpetspec.htm table 1-1. industry specifications (sheet 2 of 2) specification location
intel ? i/o controller hub 6 (ich6) family datasheet 45 introduction chapter 10. lpc bridge registers chapter 10 provides a detailed description of all register s that reside in the lpc bridge. this bridge resides at device 31, function 0 (d31:f0). this func tion contains registers for many different units within the ich6 including dma, timers, inte rrupts, processor interface, gpio, power management, system management and rtc. chapter 11. ide controller registers chapter 11 provides a detailed description of all regist ers that reside in the ide controller. this controller resides at device 31, function 1 (d31:f1). chapter 12. sata controller registers chapter 12 provides a detailed description of all registers that reside in the sata controller. this controller resides at device 31, function 2 (d31:f2). chapter 13. uhci controller registers chapter 13 provides a detailed description of all registers that reside in the four uhci host controllers. these controllers reside at device 29, functions 0, 1, 2, and 3 (d29:f0/f1/f2/f3). chapter 14. ehci controller registers chapter 14 provides a detailed description of all registers that reside in the ehci host controller. this controller resides at device 29, function 7 (d29:f7). chapter 15. smbus controller registers chapter 15 provides a detailed description of all regist ers that reside in the smbus controller. this controller resides at device 31, function 3 (d31:f3). chapter 16. ac ?97 a udio controller registers chapter 16 provides a detailed description of all registers that reside in the audio controller. this controller resides at device 30, function 2 (d30:f2). note that this section of the eds does not include the native audio mixer registers. accesse s to the mixer registers are forwarded over the ac-link to the codec where the registers reside. chapter 17. ac ?97 modem controller registers chapter 17 provides a detailed description of all register s that reside in the modem controller. this controller resides at device 30, function 3 (d30:f3). note that this section of the eds does not include the modem mixer registers. accesses to th e mixer registers are forw arded over the ac-link to the codec where the registers reside. chapter 18. intel? high defini tion audio controller registers chapter 18 provides a detailed description of all registers that reside in the intel ? high definition audio controller. this controller resides at device 27, function 0 (d27:f0). chapter 19. pci express* port controller registers chapter 19 provides a detailed description of all regist ers that reside in the pci express controller. this controller resides at device 28, functions 0 to 3 (d30:f0-f3). chapter 20. high precision event timers registers chapter 20 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. chapter 21. ballout definition chapter 21 provides a table of each signal and it s ball assignment in the 609-mbga package. chapter 22. electrica l characteristics chapter 22 provides all ac and dc characteristics including detailed timing diagrams.
46 intel ? i/o controller hub 6 (i ch6) family datasheet introduction chapter 23. package information chapter 23 provides drawings of the physical dime nsions and characteristics of the 609-mbga package. chapter 24. testability chapter 24 provides detail about the implementation of test modes provided in the ich6. 1.2 overview the ich6 provides extensive i/o support. functions and capabilities include: ? pci express* base speci fication, revision 1.0a -compliant ? pci local bus specification , revision 2.3-compliant with support for 33 mhz pci operations ( supports up to seven req/gnt pairs). ? acpi power management logic support ? enhanced dma controller, interrupt controller, and timer functions ? integrated serial ata host controller with independent dma operation on four ports (ich6/ich6r only) or two ports (ich6-m only) and ahci support (ich6r/ich6-m only). ? integrated ide controller supports ultra ata100/66/33 ? usb host interface with su pport for eight us b ports; four uhci host controllers; one ehci high-speed usb 2.0 host controller ? integrated lan controller ? system management bus (smbus) specification , version 2.0 with additional support for i 2 c devices ? supports audio codec ?97, revision 2.3 specification (a.k.a., ac ?97 component specification , revision 2.3 ) which provides a link for audio and telephony codecs (up to 7 channels) ? supports intel high definition audio ? low pin count (lpc) interface ? firmware hub (fwh) interface support the ich6 incorporates a variety of pci functions th at are divided into six logical devices (b0:d27, b0:d28, b0:d29, b0:d30, b0:d31 and b1:d8). d30 is the dmi-to-pci bridge and the ac ?97 audio and modem controller functions, d31 contains the pci-to-lpc bridge, ide controller, sata controller, and smbus controller, d29 contains the four usb uhci controllers and one usb ehci controller, and d27 contains the pci e xpress root ports. b1:d8 is the integrated lan controller.
intel ? i/o controller hub 6 (ich6) family datasheet 47 introduction the following sub-sections provide an overview of the ich6 capabilities. direct media interface (dmi) direct media interface (dmi) is the chip-to-chip connection between the memory controller hub / graphics memory controller hub ((g)mch) and i/o controller hub 6 (ich6). this high-speed interface integrates advanced priority-based serv icing allowing for concur rent traffic and true isochronous transfer capabilities. base functionality is completely software-transparent, permitting current and legacy software to operate normally. pci express* interface the ich6 provides 4 pci express root ports that are compliant to the pci express base specification, revision 1.0a . the pci express root ports can be statically configur ed as four x1 ports or ganged together to form one x4 port (enterprise applications only). each root port supports 2.5 gb/s bandwidth in each direction (5 gb /s concurrent) and two virtual channels for full isochronous data support. table 1-2. pci devices and functions bus:device:function function description bus 0:device 30:function 0 pci-to-pci bridge bus 0:device 30:function 2 ac ?97 audio controller bus 0:device 30:function 3 ac ?97 modem controller bus 0:device 31:function 0 lpc controller 1 notes: 1. the pci-to-lpc bridge contains register s that control lpc, power management, system management, gpio, processor interface, rtc, interrupts, timers, and dma. bus 0:device 31:function 1 ide controller bus 0:device 31:function 2 sata controller bus 0:device 31:functi on 3 smbus controller bus 0:device 29:function 0 usb uhci controller 1 bus 0:device 29:function 1 usb uhci controller 2 bus 0:device 29:function 2 usb uhci controller 3 bus 0:device 29:function 3 usb uhci controller 4 bus 0:device 29:function 7 usb 2.0 ehci controller bus 0:device 28:function 0 pci express* port 1 bus 0:device 28:function 1 pci express port 2 bus 0:device 28:function 2 pci express port 3 bus 0:device 28:function 3 pci express port 4 bus 0:device 27:function 0 intel high definition audio controller bus n:device 8:function 0 lan controller
48 intel ? i/o controller hub 6 (i ch6) family datasheet introduction serial ata (sata) controller the ich6 has an integrated sata host controller that supports independent dma operation on four ports (desktop only) or two ports (mobile on ly) and supports data transfer rates of up to 1.5 gb/s (150 mb/s). the sata controller contains two modes of operation; a legacy mode using i/o space, and an ahci mode usin g memory space (ich6r/ich6-m only). sata and pata can also be used in a combined function mode (where the sata function is used with pata). in this combined function mode, ahci mode is not used. software that uses legacy mode will not have ahci capabilities. the ich6 supports the serial ata specification, revision 1.0a . the ich6 also supports several optional sections of the serial ata ii: extensions to serial ata 1.0 specification, revision 1.0 (ahci support is required for some elements). ahci (intel ? ich6r/ich6-m only) the ich6r/ich6-m provide hardware support for advanced host controller interface (ahci), a new programming interface for sata host cont rollers. platforms supporting ahci may take advantage of performance features such as no master/slave designation for sata devices?each device is treated as a master?and hardware -assisted native command queuing. ahci also provides usability enhancements (e.g., hot-plug ). ahci requires appropriate software support (e.g., an ahci driver) and for some features, ha rdware support in the sata device or additional platform hardware. pci interface the ich6 pci interface provides a 33 mhz, revisi on 2.3 implementation. all pci signals are 5 v tolerant, except pme#. the ich6 in tegrates a pci arbiter that supp orts up to seven external pci bus masters in addition to the internal ich6 requests. this allows for combinations of up to seven pci down devices and pci slots. ide interface (bus master capability and synchronous dma mode) the fast ide interface supports up to two ide devi ces providing an interface for ide hard disks and atapi devices. each ide device can have independent timings. the ide interface supports pio ide transfers up to 16 mb/sec and ultra ata transfers up 100 mb/sec. it does not consume any legacy dma resources. the ide interface integrates 16x32- bit buffers for optimal transfers. the ich6?s ide system contains a single, independent ide signal channel that can be electrically isolated. there are integrated series resistors on the data and control lines (see section 5.16 for details). low pin count (lpc) interface the ich6 implements an lpc in terface as described in the lpc 1.1 specification. the low pin count (lpc) bridge function of the ich6 resides in pci device 31:function 0. in addition to the lpc bridge interface function, d 31:f0 contains other functional units incl uding dma, interrupt controllers, timers, power management, system management, gpio, and rtc.
intel ? i/o controller hub 6 (ich6) family datasheet 49 introduction compatibility modules (dma controller, timer/counters, interrupt controller) the dma controller incorporat es the logic of two 82c37 dma controllers, with seven independently programmable channels. channels 0?3 are hardwired to 8-bit, count-by-byte transfers, and channels 5?7 are hardwi red to 16-bit, count-by-word transfers. any two of the seven dma channels can be programmed to support fast type-f transfers. the ich6 supports lpc dma, which is similar to isa dma, through the ich6?s dma controller. lpc dma is handled through the use of the ldrq # lines from peripherals and special encoding on lad[3:0] from the host. single, demand, veri fy, and increment modes are supported on the lpc interface. channels 0?3 are 8-bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. the timer/counter block contains three counters that are equivalent in function to those found in one 82c54 programmable interval timer. these three counters are combined to provide the system timer function, and speaker tone. the 14.31818 mhz oscillator input provides the clock source for these three counters. the ich6 provides an isa-compatible programmable interrupt controller (p ic) that incorporates the functionality of two, 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. in addition, the ich6 supports a serial interrupt scheme. all of the registers in these m odules can be read and restored. this is required to save and restore system state after power has been re moved and restored to the platform. advanced programmable interrupt controller (apic) in addition to the standard isa compatible prog rammable interrupt controller (pic) described in the previous section, the ich6 incorporates the advanced pr ogrammable interrupt controller (apic). universal serial bus (usb) controller the ich6 contains an enhanced host controller interface (ehci) compliant host controller that supports usb high-speed signaling. high-speed us b 2.0 allows data transfers up to 480 mb/s which is 40 times faster than full-speed usb. the ich6 also contains four universal host controller interface (uhci) controllers that support usb full-speed a nd low-speed signaling. the ich6 supports eight usb 2.0 ports. all eight ports are high-speed, fu ll-speed, a nd low-speed capable. ich6?s port-routing logic determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. see section 5.19 and section 5.20 for details. lan controller the ich6?s integrated lan cont roller includes a 32-bit pci controller that provides enhanced scatter-gather bus mastering capabilities and enab les the lan controller to perform high speed data transfers over the pci bus. its bus master cap abilities enable the comp onent to process high- level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the pro cessor. two large transmit and r eceive fifos of 3 kb each help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs).
50 intel ? i/o controller hub 6 (i ch6) family datasheet introduction the lan controller can operate in either full duplex or half duplex mode. in full duplex mode the lan controller adheres with the ieee 802.3x flow control specificat ion. half duplex performance is enhanced by a proprietary collision reduction mechanism. see section 5.3 for details. alert standard format (asf) management controller ich6 integrates an alert stand format controller in addition to the integrated lan controller, allowing interface system-monitoring devices to communicate through the integrated lan controller to the network. this means remote manageability and system hardware monitoring are made possible using asf. the asf controller can collect and send various information from sy stem components such as the processor, chipset, bios and sensors on the moth erboard to a remote serv er running a management console. the controller can also be programmed to accept commands back from the management console and execute those comm ands on the local system. rtc the ich6 contains a motorola mc146818a-compatib le real-time clock with 256 bytes of battery- backed ram. the real-time clock performs two key functions: keeping track of the time of day and storing system data, even wh en the system is powered down. the rtc operates on a 32.768 khz crystal and a 3 v battery. the rtc also supports two lockable memory ranges. by setting bits in the configuration space, two 8-byte ranges can be lock ed to read and write accesses. this prevents unauth orized reading of passwords or other system security information. the rtc also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than ju st 24 hours in advance. gpio various general purpose inputs and outputs are provided for custom system design. the number of inputs and outputs varies depending on ich6 configuration. enhanced power management the ich6?s power management functions include enhanced clock control and various low-power (suspend) states (e.g., suspend-to-ram and suspend-to-disk). a hardware-based thermal management circuit permits software-ind ependent entrance to low-power states. the ich6 contains full support for the advanced configuration and power interface (acpi) specification, revision 2.0 . manageability the ich6 integrates several functions designed to manage the system and lower the total cost of ownership (tco) of the system. th ese system management functions are designed to report errors, diagnose the system, and rec over from system lockups withou t the aid of an external microcontroller.
intel ? i/o controller hub 6 (ich6) family datasheet 51 introduction ? tco timer. the ich6?s integrated programmable tco tim er is used to detect system locks. the first expiration of the timer generates an sm i# that the system can use to recover from a software lock. the second expiration of the tim er causes a system reset to recover from a hardware lock. ? processor present indicator. the ich6 looks for the processor to fetch the first instruction after reset. if the processor does not fetch the first instruction, the ich6 will reboot the system. ? ecc error reporting. when detecting an ecc error, the host controller has the ability to send one of several messages to the ich6. th e host controller can instruct the ich6 to generate either an smi#, nmi, serr#, or tco interrupt. ? function disable. the ich6 provides the ability to disable the following integrated functions: ac ?97 modem, ac ?97 audio, ide, lan, usb, lpc, intel high definition audio, sata, or smbus. once disabled, these functions no longe r decode i/o, memory, or pci configuration space. also, no interrupts or power management events are generated from the disable functions. ? intruder detect. the ich6 provides an input signal (intruder#) that can be attached to a switch that is activated by th e system case being opened. the ich6 can be programmed to generate an smi# or tco interrup t due to an active intruder# signal. ? smbus 2.0. the ich6 integrates an smbus controller that provides an interface to manage peripherals (e.g., serial pres ence detection (spd) and therma l sensors) with host notify capabilities. system management bus (smbus 2.0) the ich6 contains an smbus ho st interface that allows the pr ocessor to communicate with smbus slaves. this interface is compatible with most i 2 c devices. special i 2 c commands are implemented. the ich6?s smbus host controller provides a mechanism for the processor to initiate communications with smbus peripherals (slaves) . also, the ich6 supports slave functionality, including the host notify protocol. hence, the hos t controller supports eight command protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/w ord, read byte/word, process call, block read/write, and host notify. ich6?s smbus also implements hardware-based packet error ch ecking for data robustness and the address resolution protocol (arp) to dynam ically provide address to all smbus devices. intel high definition audio controller the intel high definition audi o specification defines a digital inte rface that can be used to attach different types of codecs, such as au dio and modem codecs. the ich6 intel high definition audio digital link shares pins with the ac-link. concurrent operation of intel high definition audio and ac ?97 functionality is not supported. the ich6 intel high definition audio controller supports up to 3 codecs. with the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 khz, the intel high definition audio controller provides audio quality that can deliver ce levels of audio experience. on the input side, the ich6 adds support for an arrays of microphones.
52 intel ? i/o controller hub 6 (i ch6) family datasheet introduction the intel high definition audio controller utilizes multi-purpose dma engines, as opposed to dedicated dma engines in ac ?97, to effec tively manage the link bandwidth and support simultaneous independent streams on the link. the capability enables new exciting usage models with intel high definition audio (e.g., listening to music while playing multi-player game on the internet.) the intel high definition audio controller also supports isochronous data transfers allowing glitch-free audio to the system. note: users interested in providing feedback on the intel high definition audio specification or planning to implement the intel high definition audio specification in to a future product will need to execute the intel high definition audio specification developer?s agreement. for more information, contact nextgenaudio@intel.com. ac ?97 2.3 controller the ich6 integrates an audio codec '97 component specification, version 2.3 controller that can be used to attach an audio co dec (ac), a modem codec (mc), an audio/modem codec (amc) or a combination of acs and a single mc. the ich6 supports up to six channels of pcm audio output (full ac3 decode). for a complete surround-sound e xperience, six-channel audio consists of: front left, front right, back left, back right, center, and subwoofer. ich6 has expanded support for up to three audio codecs on the ac-link. in addition, an ac '97 soft modem can be impl emented with the use of a modem codec. several system options exist when implementing ac '97. th e ich6-integrated ac '97 controller allows up to three external codecs to be connected to the ich6. the syst em designer can provide ac '97 modem with a modem codec, or both audio and modem with up to two audio codecs with a modem codec.
intel ? i/o controller hub 6 (ich6) family datasheet 53 signal description 2 signal description this chapter provides a detailed description of eac h signal. the signals are arranged in functional groups according to thei r associated interface. the ?#? symbol at the end of the si gnal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is no t present, the signal is as serted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin od o open drain output pin. od i open drain input pin. od i/o open drain input/output pin. oc o open collector output pin. i/o bi-directional input / output pin.
54 intel ? i/o controller hub 6 (i ch6) family datasheet signal description figure 2-1. intel ? ich6 interface signals block diagram (desktop) thrm# thrmtrip# sys_reset# rsmrst# mch_sync# slp_s3# slp_s4# slp_s5# pwrok pwrbtn# ri# wake# sus_stat# / lpcpd# susclk lan_rst# vrmpwrgd pltrst# ad[31:0] c/be[3:0]# devsel# frame# irdy# trdy# stop# par perr# req[3:0]# req[4]# / gpi[40] req[5]# / gpi[1] req[6]# / gpi[0] gnt[3:0]# gnt[4]# / gpo[48] gnt[5]# / gpo[17] gnt[6]# / gpo[16] pciclk pcirst# plock# serr# pme# pci interface dcs1# dcs3# da[2:0] dd[15:0] ddreq ddack# dior# (dwstb / rdmardy#) diow# (dstop) iordy (drstb / wdmardy#) ide interface power mgnt. interrupt interface a20m# cpuslp# ferr# ignne# init# init3_3v# intr nmi smi# stpclk# rcin# a20gate cpupwrgd / gpo[49] processor interface usb serirq pirq[d:a]# pirq[h:e]# / gpio[5:2] ideirq usbp[7:0]p usbp[7:0]n oc[3:0]# oc[4]# / gpi[9] oc[5]# / gpi[10] oc[6]# / gpi[14] oc[7]# / gpi[15] usbrbias# usbrbias rtcx1 rtcx2 clk14 clk48 sata_clkp, sata_clkn dmi_clkp, dmi_clkn rtc clocks misc. signals intvrmen spkr rtcrst# tp[4:0] general purpose i/o gpio[34:24] gpi[41:40, 15:0] gpo[49:48, 23, 21:16] eeprom interface ee_shclk ee_din ee_dout ee_cs intruder# smlink[1:0] linkalert# dmi[3:0]txp, dmi[3:0]txn dmi[3:0]rxp, dmi[3:0]rxn dmi_zcomp dmi_ircomp direct media interface lpc interface smbus interface acz_rst# acz_sync acz_bit_clk acz_sdout acz_sdin[2:0] ac '97/ intel ? high definition audio firmware hub system mgnt. fwh[3:0] / lad[3:0] fwh[4] / lframe# lad[3:0] / fwh[3:0] lframe# / fwh[4] ldrq[0]# ldrq[1]# / gpi[41] smbdata smbclk smbalert# / gpi[11] lan_clk lan_rxd[2:0] lan_txd[2:0] lan_rstsync lan link sata[3:0]txp, sata[3:0]txn sata[3:0]rxp, sata[3:0]rxn satarbias satarbias# sata[3:0]gp / gpi[31:29, 26] sataled# serial ata interface pci express* interface petp[4:1], petn[4:1] perp[4:1], pern[4:1]
intel ? i/o controller hub 6 (ich6) family datasheet 55 signal description figure 2-2. intel ? ich6-m interface signals bl ock diagram (mobile only) thrm# thrmtrip# sys_reset# rsmrst# mch_sync# dprstp# slp_s3# slp_s4# slp_s5# pwrok pwrbtn# ri# wake# sus_stat# / lpcpd# susclk lan_rst# vrmpwrgd bmbusy# stp_pci# stp_cpu# batlow# dprslpvr pltrst# ad[31:0] c/be[3:0]# devsel# frame# irdy# trdy# stop# par perr# req[3:0]# req[4]# / gpi[40] req[5]# / gpi[1] req[6]# / gpi[0] gnt[3:0]# gnt[4]# / gpo[48] gnt[5]# / gpo[17] gnt[6]# / gpo[16] pciclk pcirst# plock# serr# pme# clkrun# pci interface dcs1# dcs3# da[2:0] dd[15:0] ddreq ddack# dior# (dwstb / rdmardy#) diow# (dstop) iordy (drstb / wdmardy#) ide interface power mgnt. interrupt interface a20m# cpuslp# ferr# ignne# init# init3_3# intr nmi smi# stpclk# rcin# a20gate cpupwrgd / gpo[49] dpslp# processor interface usb serirq pirq[d:a]# pirq[h:e]# / gpi[5:2] ideirq usbp[7:0]p usbp[7:0]n oc[3:0]# oc[4]# / gpi[9] oc[5]# / gpi[10] oc[6]# / gpi[14] oc[7]# / gpi[15] usbrbias# usbrbias rtcx1 rtcx2 clk14 clk48 sata_clkp, sata_clkn dmi_clkp, dmi_clkn rtc clocks misc. signals intvrmen spkr rtcrst# tp[3] general purpose i/o gpio[34:33, 28:27, 25:24] gpi[41:40, 31:29, 26, 15:7, 5:0] gpo[49:48, 23, 21, 19, 17:16] eeprom interface ee_shclk ee_din ee_dout ee_cs intruder# smlink[1:0] linkalert# dmi[3:0]txp, dmi[3:0]txn dmi[3:0]rxp, dmi[3:0]rxn dmi_zcomp dmi_ircomp direct media interface lpc interface smbus interface acz_rst# acz_sync acz_bit_clk acz_sdout acz_sdin[2:0] ac '97/ intel ? high definition audio firmware hub system mgnt. fwh[3:0] / lad[3:0] fwh[4] / lframe# lad[3:0] / fwh[3:0] lframe# / fwh[4] ldrq[0]# ldrq[1]# / gpi[41] smbdata smbclk smbalert# / gpi[11] lan_clk lan_rxd[2:0] lan_txd[2:0] lan_rstsync lan link sata[2,0]txp, sata[2,0]txn sata[2,0]rxp, sata[2,0]rxn satarbias satarbias# sata[2,0]gp / gpi[30, 26] sataled# serial ata interface pci express* interface petp[4:1], petn[4:1] perp[4:1], pern[4:1]
56 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.1 direct media interface (dmi) to host controller 2.2 pci express* table 2-1. direct media interface signals name type description dmi[0]txp, dmi[0]txn o direct media interface differential transmit pair 0 dmi[0]rxp, dmi[0]rxn i direct media interface differential receive pair 0 dmi[1]txp, dmi[1]txn o direct media interface differential transmit pair 1 dmi[1]rxp, dmi[1]rxn i direct media interface differential receive pair 1 dmi[2]txp, dmi[2]txn o direct media interface differential transmit pair 2 dmi[2]rxp, dmi[2]rxn i direct media interface differential receive pair 2 dmi[3]txp, dmi[3]txn o direct media interface differential transmit pair 3 dmi[3]rxp, dmi[3]rxn i direct media interface differential receive pair 3 dmi_zcomp i impedance compensation input: determines dmi input impedance. dmi_ircomp o impedance/current compensation output: determines dmi output impedance and bias current. table 2-2. pci express* signals name type description petp[1], petn[1] o pci express* differential transmit pair 1 perp[1], pern[1] i pci express differential receive pair 1 petp[2], petn[2] o pci express differential transmit pair 2 perp[2], pern[2] i pci express differential receive pair 2 petp[3], petn[3] o pci express differential transmit pair 3 perp[3], pern[3] i pci express differential receive pair 3 petp[4], petn[4] o pci express differential transmit pair 4 perp[4], pern[4] i pci express differential receive pair 4
intel ? i/o controller hub 6 (ich6) family datasheet 57 signal description 2.3 link to lan connect 2.4 eeprom interface 2.5 firmware hub interface table 2-3. lan connect interface signals name type description lan_clk i lan i/f clock: this signal is driven by the lan connect component. the frequency range is 5 mhz to 50 mhz. lan_rxd[2:0] i received data: the lan connect component uses these signals to transfer data and control information to the integrated lan controller. these signals have integrated weak pull-up resistors. lan_txd[2:0] o transmit data : the integrated lan controller uses these signals to transfer data and control information to the lan connect component. lan_rstsync o lan reset/sync: the lan connect component?s reset and sync signals are multiplexed onto this pin. table 2-4. eeprom interface signals name type description ee_shclk o eeprom shift clock : serial shift clock output to the eeprom. ee_din i eeprom data in : transfers data from the eeprom to the intel ? ich6. this signal has an integrated pull-up resistor. ee_dout o eeprom data out : transfers data from the ich6 to the eeprom. ee_cs o eeprom chip select : chip select signal to the eeprom. table 2-5. firmware hub interface signals name type description fwh[3:0] / lad[3:0] i/o firmware hub signals. these signals are multiplexed with the lpc address signals. fwh[4] / lframe# o firmware hub signals. this signal is multiplexed with the lpc lframe# signal.
58 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.6 pci interface table 2-6. pci interface signals (sheet 1 of 3) name type description ad[31:0] i/o pci address/data : ad[31:0] is a multiplexed address and data bus. during the first clock of a transaction, ad[31:0] c ontain a physical address (32 bits). during subsequent clocks, ad[31:0] contain data. the intel ? ich6 will drive all 0?s on ad[31:0] during the address phase of all pci special cycles. c/be[3:0]# i/o bus command and byte enables : the command and byte enable signals are multiplexed on the same pci pins. duri ng the address phase of a transaction, c/be[3:0]# define the bus command. during the data phase c/be[3:0]# define the byte enables. all command encodings not shown are reserved. the ich6 does not decode reserved values, and therefore will not re spond if a pci master generates a cycle using one of the reserved values. devsel# i/o device select : the ich6 asserts devsel# to claim a pci transaction. as an output, the ich6 asserts devsel# when a pci master peripheral attempts an access to an internal ich6 address or an address destined dmi (main memory or graphics). as an input, devsel# indica tes the response to an ich6-initiated transaction on the pci bus. devsel# is tri-stated from the leading edge of pltrst#. devsel# remains tri-stated by the ich6 until driven by a target device. frame# i/o cycle frame: the current initiator drives frame# to indicate the beginning and duration of a pci transaction. while the initiator asserts frame#, data transfers continue. when the initiator negates fram e#, the transaction is in the final data phase. frame# is an input to the ich6 when the ich6 is the target, and frame# is an output from the ich6 when the ich6 is the initiator. frame# remains tri- stated by the ich6 until driven by an initiator. irdy# i/o initiator ready : irdy# indicates the ich6's ability, as an initiator, to complete the current data phase of the transaction. it is used in conjunction with trdy#. a data phase is completed on any clock both irdy# and trdy# are sampled asserted. during a write, irdy# indicates the ich6 has valid data present on ad[31:0]. during a read, it indicates the ich6 is prepared to latch data. irdy# is an input to the ich6 when the ich6 is the target and an output from the ich6 when the ich6 is an initiator. irdy# remains tri-stated by the ich6 until driven by an initiator. c/be[3:0]# command type 0000b interrupt acknowledge 0001b special cycle 0010b i/o read 0011b i/o write 0110b memory read 0111b memory write 1010b configuration read 1011b configuration write 1100b memory read multiple 1110b memory read line 1111b memory write and invalidate
intel ? i/o controller hub 6 (ich6) family datasheet 59 signal description trdy# i/o target ready : trdy# indicates the ich6's ability as a target to complete the current data phase of the transaction. trdy # is used in conjunction with irdy#. a data phase is completed when both trdy# and irdy# are sampled asserted. during a read, trdy# indicates that the ich6, as a target, has placed valid data on ad[31:0]. during a write, trdy# indicates the ich6, as a target is prepared to latch data. trdy# is an input to the ich6 when the ich6 is the initiator and an output from the ich6 when the ich6 is a target. trdy# is tri-stated from the leading edge of pltrst#. trdy# remains tri- stated by the ich6 until driven by a target. stop# i/o stop : stop# indicates that the ich6, as a target, is requesting the initiator to stop the current transaction. stop# causes the ich6, as an initiator, to stop the current transaction. stop# is an output when the ich6 is a target and an input when the ich6 is an initiator. par i/o calculated/checked parity: par uses ?even? parity calculated on 36 bits, ad[31:0] plus c/be[3:0]#. ?even? parity means that the ich6 counts the number of one within the 36 bits plus par and the su m is always even. the ich6 always calculates par on 36 bits regardless of the valid byte enables. the ich6 generates par for address and data phases and only guarantees par to be valid one pci clock after the corresponding address or data phase. the ich6 drives and tri- states par identically to the ad[31:0] lines except that the ich6 delays par by exactly one pci clock. par is an out put during the address phase (delayed one clock) for all ich6 initiated transacti ons. par is an output during the data phase (delayed one clock) when the ich6 is the initiator of a pci write transaction, and when it is the target of a read transaction. ich6 checks parity when it is the target of a pci write transaction. if a parity er ror is detected, the ich6 will set the appropriate internal status bits, and has the option to generate an nmi# or smi#. perr# i/o parity error : an external pci device drives pe rr# when it receives data that has a parity error. the ich6 drives perr# when it detects a parity error. the ich6 can either generate an nmi# or smi# upon detecting a parity error (either detected internally or reported via the perr# signal). req[0:3]# req[4]# / gpi[40] req[5]# / gpi[1] req[6]# / gpi[0] i pci requests : the ich6 supports up to 7 masters on the pci bus. the req[4]#, req[5]#, and req[6]# pins can instead be used as a gpi. gnt[0:3]# gnt[4]# / gpo[48] gnt[5]# / gpo[17]# gnt[6]# / gpo[16]# o pci grants : the ich6 supports up to 7 masters on the pci bus. the gnt[4]# pin can instead be used as a gpo. pull-up resistors are not required on these signals. if pull-ups are used, they should be tied to the vcc3_3 power rail. gnt[5]#/gpo[17] and gnt[6]#/gpo[17] both have an internal pull-up. note: gnt[6] is sampled at the rising edge of pwrok as a functional strap. see section 2.22.1 for more details. there is a weak, integrated pull-up resistor on the gnt[6] pin. pciclk i pci clock : this is a 33 mhz clock. pciclk pr ovides timing for all transactions on the pci bus. note: (mobile only) this clock does not stop based on stp_pci# signal. pci clock only stops based on slp_s3#. pcirst# o pci reset: this is the secondary pci bus rese t signal. it is a logical or of the primary interface pltrst# signal and the st ate of the secondary bus reset bit of the bridge control register (d30:f0:3eh, bit 6). note: pcirst# is in the vccsus3_3 well. table 2-6. pci interface signals (sheet 2 of 3) name type description
60 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.7 serial ata interface plock# i/o pci lock : this signal indicates an exclus ive bus operation and may require multiple transactions to complete. ich6 asserts plock# when it performs non- exclusive transactions on the pci bus. pl ock# is ignored when pci masters are granted the bus in desktop configurations. devices on the pci bus (other than the ich6) are not permitted to assert the pl ock# signal in mobile configurations. serr# od i/o system error : serr# can be pulsed active by any pci device that detects a system error condition. upon sampling serr# active, the ich6 has the ability to generate an nmi, smi#, or interrupt. pme# od i pci power management event : pci peripherals drive pme# to wake the system from low-power states s1?s5. pme# assertion can also be enabled to generate an sci from the s0 state. in some cases the ich6 may drive pme# active due to an internal wake event. the ich6 will not dr ive pme# high, but it will be pulled up to vccsus3_3 by an internal pull-up resistor. clkrun# (mobile only) / gpio[32] (desktop only) i/o pci clock run: this signal is used to support pc i clock run protocol. it connects to pci devices that need to request clock re -start, or prevention of clock stopping. note: an external pull-up to vcc3_3 is required. table 2-7. serial ata interface signals (sheet 1 of 2) name type description sata[0]txp sata[0]txn o serial ata 0 differential transmit pair: these are outbound high-speed differential signals to port 0. sata[0]rxp sata[0]rxn i serial ata 0 differential receive pair: these are inbound high-speed differential signals from port 0. sata[1]txp sata[1]txn o serial ata 1 differential transmit pair: these are outbound high-speed differential signals to port 1. (desktop only) sata[1]rxp sata[1]rxn i serial ata 1 differential receive pair: these are inbound high-speed differential signals from port 1. (desktop only) sata[2]txp sata[2]txn o serial ata 2 differential transmit pair: these are outbound high-speed differential signals to port 2. sata[2]rxp sata[2]rxn i serial ata 2 differential receive pair: these are inbound high-speed differential signals from port 2. sata[3]txp sata[3]txn o serial ata 3 differential transmit pair: these are outbound high-speed differential signals to port 3. (desktop only) sata[3]rxp sata[3]rxn i serial ata 3 differential receive pair: these are inbound high-speed differential signals from port 3. (desktop only) satarbias o serial ata resistor bias: these are analog connection points for an external resistor to ground. satarbias# i serial ata resistor bias complement: these are analog connection points for an external resistor to ground. table 2-6. pci interface signals (sheet 3 of 3) name type description
intel ? i/o controller hub 6 (ich6) family datasheet 61 signal description 2.8 ide interface sata[0]gp / gpi[26] i serial ata 0 general purpose: this is an input pin t hat can be configured as an interlock switch corresponding to sa ta port 0. when used as an interlock switch status indication, this signal s hould be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open. if interlock switches are not required, this pin can be configured as gpi[26]. note: all sataxgp pins must be configured with the same function: as either sataxgp pins or gpi pins. sata[1]gp (desktop only) / gpi[29] i serial ata 1 general purpose: same function as sata[0]gp, except for sata port 1. if interlock switches are not required, this pin can be configured as gpi[29]. sata[2]gp / gpi[30] i serial ata 2 general purpose: same function as sata[0]gp, except for sata port 2. if interlock switches are not required, this pin can be configured as gpi[30]. sata[3]gp (desktop only) / gpi[31] i serial ata 3 general purpose: same function as sata[0]gp, except for sata port 3. if interlock switches are not required, this pin can be configured as gpi[31]. sataled# oc o serial ata led: this is an open-collector output pin driven during sata command activity. it is to be connected to external circuitry that can provide the current to drive a platform led. when active, the led is on. when tri-stated, the led is off. an external pull- up resistor to vcc3_3 is required. note: an internal pull-up is enabled only during pltrst# assertion. table 2-8. ide interface signals (sheet 1 of 2) name type description dcs1# o ide device chip selects for 100 range: for ata command register block. this output signal is connected to the co rresponding signal on the ide connector. dcs3# o ide device chip select for 300 range: for ata control register block. this output signal is connected to the corr esponding signal on the ide connector. da[2:0] o ide device address: these output signals are c onnected to the corresponding signals on the ide connector. they are used to indicate which byte in either the ata command block or contro l block is being addressed. dd[15:0] i/o ide device data: these signals directly drive t he corresponding signals on the ide connector. there is a weak inte rnal pull-down resistor on dd7. ddreq i ide device dma request: this input signal is direct ly driven from the drq signal on the ide connector. it is asserted by the ide device to request a data transfer, and used in conjunction with the pc i bus master ide function and are not associated with any at compatible dma channel. there is a weak internal pull- down resistor on this signal. ddack# o ide device dma acknowledge: this signal directly drives the dak# signal on the ide connector. ddack# is asserted by the intel ? ich6 to indicate to ide dma slave devices that a given data transfer cy cle (assertion of dior# or diow#) is a dma data transfer cycle. this signal is used in conjunction with the pci bus master ide function and are not associated wi th any at-compatible dma channel. table 2-7. serial ata interface signals (sheet 2 of 2) name type description
62 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.9 lpc interface dior# / (dwstb / rdmardy#) o disk i/o read (pio and non-ultra dma) : this is the command to the ide device that it may drive data onto the dd lines. data is latched by the ich6 on the de- assertion edge of dior#. the ide device is selected either by the ata register file chip selects (dcs1# or dcs3#) and the da lines, or the ide dma acknowledge (ddak#). disk write strobe (ultra dma writes to disk ): this is the data write strobe for writes to disk. when writing to disk, ich6 driv es valid data on rising and falling edges of dwstb. disk dma ready (ultra dma reads from di sk): this is the dma ready for reads from disk. when reading from disk, ich6 de-asserts rdmardy# to pause burst data transfers. diow# / (dstop) o disk i/o write (pio and non-ultra dma) : this is the command to the ide device that it may latch data from the dd lines. data is latched by the ide device on the de-assertion edge of diow#. the ide device is selected either by the ata register file chip selects (dcs1# or dcs3#) and the da lines, or the ide dma acknowledge (ddak#). disk stop (ultra dma): ich6 asserts this signal to terminate a burst. iordy / (drstb / wdmardy#) i i/o channel ready (pio) : this signal will keep the st robe active (dior# on reads, diow# on writes) longer than the minimum width. it adds wait-states to pio transfers. disk read strobe (ultra dma reads from disk): when reading from disk, ich6 latches data on rising and falling edges of this signal from the disk. disk dma ready (ultra dma writes to disk): when writing to disk, this is de- asserted by the disk to pause burst data transfers. table 2-9. lpc interface signals name type description lad[3:0] / fwh[3:0] i/o lpc multiplexed command, address, data: for lad[3:0], internal pull-ups are provided. lframe# / fwh[4] o lpc frame: lframe# indicates the start of an lpc cycle, or an abort. ldrq[0]# ldrq[1]# / gpi[41] i lpc serial dma/master request inputs: ldrq[1:0]# are used to request dma or bus master access. these signals are typically connect ed to external super i/o device. an internal pull-up resi stor is provided on these signals. ldrq[1]# may optionally be used as gpi. table 2-8. ide interface signals (sheet 2 of 2) name type description
intel ? i/o controller hub 6 (ich6) family datasheet 63 signal description 2.10 interrupt interface table 2-10. interrupt signals name type description serirq i/o serial interrupt request: this pin implements the se rial interrupt protocol. pirq[d:a]# od i pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqa# is connected to irq16, pi rqb# to irq17, pirqc# to irq18, and pirqd# to irq19. this frees the legacy interrupts. pirq[h:e]# / gpi[5:2] od i pci interrupt requests: in non-apic mode the pirqx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the interrupt steering section. each pirqx# line has a separate route control register. in apic mode, these signals are connected to the internal i/o apic in the following fashion: pirqe# is connected to irq20, pi rqf# to irq21, pirqg# to irq22, and pirqh# to irq23. this frees the legacy interrupts. if not needed for interrupts, these signals can be used as gpi. ideirq i ide interrupt request: this interrupt input is connected to the ide drive.
64 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.11 usb interface table 2-11. usb interface signals name type description usbp[0]p, usbp[0]n, usbp[1]p, usbp[1]n i/o universal serial bus port [1:0] differential : these differential pairs are used to transmit data/address/command signals for ports 0 and 1. these ports can be routed to uhci controller #1 or the ehci controller. note: no external resistors are required on these signals. the ich6 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp[2]p, usbp[2]n, usbp[3]p, usbp[3]n i/o universal serial bus port [3:2] differential : these differential pairs are used to transmit data/address/command signals for ports 2 and 3. these ports can be routed to uhci controller #2 or the ehci controller. note: no external resistors are required on these signals. the ich6 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp[4]p, usbp[4]n, usbp[5]p, usbp[5]n i/o universal serial bus port [5:4] differential : these differential pairs are used to transmit data/address/command signals for ports 4 and 5. these ports can be routed to uhci controller #3 or the ehci controller. note: no external resistors are required on these signals. the ich6 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor usbp[6]p, usbp[6]n, usbp[7]p, usbp[7]n i/o universal serial bus port [7:6] differential : these differential pairs are used to transmit data/address/command signals for ports 6 and 7. these ports can be routed to uhci controller #4 or the ehci controller. note: no external resistors are required on these signals. the ich6 integrates 15 k ? pull-downs and provides an output driver impedance of 45 ? which requires no external series resistor oc[3:0]# oc[4]# / gpi[9] oc[5]# / gpi[10] oc[6]# / gpi[14] oc[7]# / gpi[15] i overcurrent indicators : these signals set corresponding bits in the usb controllers to indicate that an overcurrent condition has occurred. oc[7:4]# may optionally be used as gpis. note: oc[7:0]# are not 5 v tolerant. usbrbias o usb resistor bias: analog connection point for an external resistor. this signal is used to set transmit curre nts and internal load resistors. usbrbias# i usb resistor bias complement: analog connection point for an external resistor. this signal is used to set transmit currents and internal load resistors.
intel ? i/o controller hub 6 (ich6) family datasheet 65 signal description 2.12 power management interface table 2-12. power management interface signals (sheet 1 of 2) name type description pltrst# o platform reset: the ich6 asserts pltrst# to reset devices on the platform (e.g., sio, fwh, lan, (g)mch, ide, tpm, etc.). the ich6 asserts pltrst# during power-up and when s/w initiates a hard reset sequence through the reset control register (i/o register cf9h). the ich6 dr ives pltrst# inactive a minimum of 1 ms after both pwrok and vrmpwrgd are driv en high. the ich6 drives pltrst# active a minimum of 1 ms when initiated through the reset control register (i/o register cf9h). note: pltrst# is in the vccsus3_3 well. thrm# i thermal alarm: active low signal generated by external hardware to generate an smi# or sci. thrmtrip# i thermal trip : when low, this signal indicates that a thermal trip from the processor occurred, and the ich6 will immediately trans ition to a s5 state. the ich6 will not wait for the processor stop grant cy cle since the processor has overheated. slp_s3# o s3 sleep control: slp_s3# is for power plane control. this signal shuts off power to all non-critical systems when in s3 (suspend to ram), s4 (suspend to disk), or s5 (soft off) states. slp_s4# o s4 sleep control : slp_s4# is for power plane control. this signal shuts power to all non-critical systems when in the s4 (s uspend to disk) or s5 (soft off) state. note: this pin must be used to control the dram power to use the ich6?s dram power-cycling feature. refer to chapter 5.14.11.2 for details. slp_s5# o s5 sleep control: slp_s5# is for power plane contro l. this signal is used to shut power off to all non-critical systems when in the s5 (soft off) states. pwrok i power ok: when asserted, pwrok is an indication to the ich6 that core power has been stable for at least 99 ms and pciclk has been stable for at least 1 ms. an exception to this rule is if the system is in s3 hot , in which pwrok may or may not stay asserted even though pciclk ma y be inactive. pwrok can be driven asynchronously. when pwrok is negated, the ich6 asserts pltrst#. note: pwrok must de-assert for a minimum of three rtc clock periods in order for the ich6 to fully reset the power and properly generate the pltrst# output pwrbtn# i power button: the power button will cause smi# or sci to indicate a system request to go to a sleep state. if the system is already in a sleep state, this signal will cause a wake event. if pwrbtn# is press ed for more than 4 seconds, this will cause an unconditional transition (power butt on override) to the s5 state. override will occur even if the system is in the s1-s 4 states. this signal has an internal pull- up resistor and has an internal 16 ms de-bounce on the input. ri# i ring indicate: this signal is an input from a modem. it can be enabled as a wake event, and this is preserved across power failures. sys_reset# i system reset : this pin forces an internal reset after being debounced. the ich6 will reset immediately if the smbus is idle; otherwise, it will wait up to 25 ms 2 ms for the smbus to idle before forcing a reset on the system. rsmrst# i resume well reset: this signal is used for resetting the resume power plane logic.
66 intel ? i/o controller hub 6 (i ch6) family datasheet signal description lan_rst# i lan reset: when asserted, the internal lan cont roller will be put into reset. this signal must be asserted for at least 10 ms after the resume well power (vccsus3_3 and vccsus1_5 in desktop and vcclan3_3 and vcclan1_5 in mobile) is valid. when de-asserted, this signal is an indicati on that the resume (lan for mobile) well power is stable. note: lan_rst# must de-assert at some point to complete ich6 power up sequencing. wake# i pci express* wake event: sideband wake signal on pci express asserted by components requesting wakeup. mch_sync# i mch sync: this input is internally anded with the pwrok input. desktop: connected to the ich_sync# output of (g)mch. mobile: refer to the platform design guide. sus_stat# / lpcpd# o suspend status: this signal is asserted by the ich6 to indicate that the system will be entering a low power state soon. this ca n be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. it can also be used by other peripherals as an indication t hat they should isolate their outputs that may be going to powered-off planes. this signal is called lpcpd# on the lpc i/f. susclk o suspend clock: this clock is an output of the rtc generator circuit to be used by other chips for refresh clock. vrmpwrgd i vrm power good: this should be connected to be the processor?s vrm power good signifying the vrm is stable. this signal is internally anded with the pwrok input. bmbusy# (mobile only) / gpi[6] (desktop only) i bus master busy: to support the c3 state. indication that a bus master device is busy. when this signal is asserted, the bm_sts bit will be set. if this signal goes active in a c3 state, it is treated as a break event. notes: 1. this signal is internally synchron ized using the pciclk and a two-stage synchronizer. it does not need to meet any particular setup or hold time. 2. in desktop configurations , this signal is a gpi. stp_pci# (mobile only) / gpo[18] (desktop only) o stop pci clock: this signal is an output to the exte rnal clock generator for it to turn off the pci clock. it is used to support pc i clkrun# protocol. if this functionality is not needed, this signal can be configured as a gpo. stp_cpu# (mobile only) / gpo[20] (desktop only) o stop processor clock: this signal is an output to the external clock generator for it to turn off the processor clock. it is used to support the c3 state. if this functionality is not needed, this signal can be configured as a gpo. batlow# (mobile only) / tp[0] (desktop only) i battery low: this signal is an input from battery to indicate that there is insufficient power to boot the system. assertion will pr event wake from s3?s5 state. this signal can also be enabled to cause an smi# when asserted. dprslpvr (mobile only) / tp[1] (desktop only) o deeper sleep - voltage regulator: this signal is used to lower the voltage of vrm during the c4 state. when the signal is high , the voltage regulator outputs the lower ?deeper sleep? voltage. when low (default), the voltage regulator outputs the higher ?normal? voltage. dprstp# (mobile only) / tp[4] (desktop only) o deeper sleep: this is a copy of the dprslpvr and it is active low. table 2-12. power management interface signals (sheet 2 of 2) name type description
intel ? i/o controller hub 6 (ich6) family datasheet 67 signal description 2.13 processor interface table 2-13. processor interface signals (sheet 1 of 2) name type description a20m# o mask a20: a20m# will go active based on either setting the appropriate bit in the port 92h register, or based on the a20gate input being active. cpuslp# o processor sleep: this signal puts the processor into a state that saves substantial power compared to stop-grant state. however, during that time, no snoops occur. the intel ? ich6 can optionally assert the cpuslp# signal when going to the s1 state, and will always assert it when going to c3 or c4. ferr# i numeric coprocessor error: this signal is tied to t he coprocessor error signal on the processor. ferr# is only used if the i ch6 coprocessor error reporting function is enabled in the oic.cen register (chipset configurationregisters:offset 31ffh: bit 1). if ferr# is asserted, the ich6 generates an internal irq13 to its interrupt controller unit. it is also used to gate the ignne# signal to ensure that ignne# is not asserted to the processor unless ferr# is active. ferr# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. note: ferr# can be used in some states fo r notification by the processor of pending interrupt events. this functionality is independent of the oic register bit setting. ignne# o ignore numeric error: this signal is connected to the ignore error pin on the processor. ignne# is only used if the i ch6 coprocessor error reporting function is enabled in the oic.cen register (chipset configuration registers:offset 31ffh: bit 1). if ferr# is active, indicating a copr ocessor error, a write to the coprocessor error register (i/o register f0h) causes the ignne# to be asserted. ignne# remains asserted until ferr# is negated. if ferr# is not asserted when the coprocessor error register is written, the ignne# signal is not asserted. init# o initialization: init# is asserted by the ich6 for 16 pci clocks to reset the processor. ich6 can be configured to support processor built in self test (bist). init3_3v# o initialization 3.3 v: this is the identical 3.3 v copy of init# intended for the firmware hub. intr o processor interrupt: intr is asserted by the ich6 to signal the processor that an interrupt request is pending and needs to be serviced. it is an asynchronous output and normally driven low. nmi o non-maskable interrupt: nmi is used to force a non-maskable interrupt to the processor. the ich6 can generate an nm i when either serr# is asserted or iochk# goes active via the serirq# stream. the processor detects an nmi when it detects a rising edge on nmi. nmi is rese t by setting the corresponding nmi source enable/disable bit in the nmi status and control register (i/o register 61h). smi# o system management interrupt: smi# is an active low output synchronous to pciclk. it is asserted by the ich6 in re sponse to one of many enabled hardware or software events. stpclk# o stop clock request: stpclk# is an active low output synchronous to pciclk. it is asserted by the ich6 in response to one of many hardware or software events. when the processor samples stpclk# asserted, it responds by stopping its internal clock. rcin# i keyboard controller reset cpu: the keyboard controller can generate init# to the processor. this saves the external or gate with the ich6?s other sources of init#. when the ich6 detects the assertion of this signal, init# is generated for 16 pci clocks. note: the ich6 will ignore rcin# assertion during transitions to the s1, s3, s4, and s5 states.
68 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.14 smbus interface 2.15 system management interface a20gate i a20 gate: a20gate is from the keyboard controller. the signal acts as an alternative method to force the a20m# signal active. it saves the external or gate needed with various other chipsets. cpupwrgd / gpo[49] od o processor power good: this signal should be connected to the processor?s pwrgood input to indicate when the processor power is valid. this is an open- drain output signal (external pull-up resistor required) that represents a logical and of the ich6?s pwrok and vrmpwrgd signals. this signal may optionally be configured as a gpo. dpslp# (mobile only) / tp[2] (desktop only) o deeper sleep: dpslp# is asserted by the ich6 to the processor. when the signal is low, the processor enters the deep sleep state by gating off the processor core clock inside the processor. when the signal is high (default), the processor is not in the deep sleep state. table 2-14. sm bus interface signals name type description smbdata od i/o smbus data: external pull-up resistor is required. smbclk od i/o smbus clock: external pull-up resistor is required. smbalert# / gpi[11] i smbus alert: this signal is used to wake t he system or generate smi#. if not used for smbalert#, it can be used as a gpi. table 2-15. system management interface signals name type description intruder# i intruder detect: this signal can be set to dis able system if box detected open. this signal?s status is readable, so it can be used like a gpi if the intruder detection is not needed. smlink[1:0] od i/o system management link: smbus link to optional external system management asic or lan controller. external pull-ups are required. note that smlink0 corresponds to an smbus clock signal, and smlink1 corresponds to an smbus data signal. linkalert# od i/o smlink alert: output of the integrated lan and input to either the integrated asf or an external management controller in order for the lan?s smlink slave to be serviced. table 2-13. processor interface signals (sheet 2 of 2) name type description
intel ? i/o controller hub 6 (ich6) family datasheet 69 signal description 2.16 real time clock interface 2.17 other clocks 2.18 miscellaneous signals table 2-16. real time clock interface name type description rtcx1 special crystal input 1: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rtcx1 can be driven with the desired clock rate. rtcx2 special crystal input 2: this signal is connected to the 32.768 khz crystal. if no external crystal is used, then rt cx2 should be left floating. table 2-17. other clocks name type description clk14 i oscillator clock: used for 8254 timers. runs at 14.31818 mhz. this clock is permitted to stop during s3 (or lower) states. clk48 i 48 mhz clock: used to run the usb controller. r uns at 48.000 mhz. this clock is permitted to stop during s3 (or lower) states. sata_clkp sata_clkn i 100 mhz differential clock: these signals are used to run the sata controller. runs at 100 mhz. this clock is permitted to stop during s3 (or lower) states in desktop configurations or s1 (or lower) states. dmi_clkp, dmi_clkn i 100 mhz differential clock: these signals are used to run the direct media interface. runs at 100 mhz. table 2-18. miscellaneous signals (sheet 1 of 2) name type description intvrmen i internal voltage regulator enable: this signal enables the internal 1.5 v suspend regulator when connected to vccrtc. when connected to vss, the internal regulator is disabled spkr o speaker: the spkr signal is the output of counter 2 and is internally ?anded? with port 61h bit 1 to provide speaker da ta enable. this signal drives an external speaker driver device, which in turn dr ives the system speaker. upon pltrst#, its output state is 0. note: spkr is sampled at the rising edge of pwrok as a functional strap. see section 2.22.1 for more details. there is a weak integrated pull-down resistor on spkr pin. rtcrst# i rtc reset: when asserted, this signal resets register bits in the rtc well. notes: 1. unless cmos is being cleared (only to be done in the g3 power state), the rtcrst# input must always be high when all other rtc power planes are on. 2. in the case where the rtc battery is dead or missing on the platform, the rtcrst# pin must rise before the rsmrst# pin.
70 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.19 ac ?97/intel ? high definition audio link notes: 1. some signals have integrated pull-up s or pull-downs. consult table in section 3.1 for details. 2. intel high definition audio mode is selected through d30:f1 :40h, bit 0: az/ac97#. this bit selects the mode of the shared intel high definition audio/ac ?97 si gnals. when set to 0 ac ?97 mode is selected. when set to 1 intel high definition audio mode is selected. the bit defaults to 0 (ac ?97 mode). tp[0] (desktop only) / batlow# (mobile only) i test point 0: this signal must have an external pull-up to vccsus3_3. tp[1] (desktop only) / dprslpvr# (mobile only) o test point 1: route signal to a test point. tp[2] (desktop only) / dpslp# (mobile only) o test point 2: route signal to a test point. tp[3] i test point 3: route signal to a test point. tp[4] (desktop only) / dprstp# (mobile only) o test point 4: route signal to a test point. table 2-19. ac ?97/intel ? high definition a udio link signals name type description acz_rst# o ac ?97/intel high definition audio reset: this signal is a master hardware reset to external codec(s). acz_sync o ac ?97/intel high definition audio sync: this signal is a 48 khz fixed rate sample sync to the codec(s). also used to encode the stream number. acz_bit_clk i/o ac ?97 bit clock input: this signal is a 12.288 mhz serial data clock generated by the external codec(s). this signal has an integrated pull-down resistor (see note below). intel high definition audio bit clock output: this signal is a 24.000 mhz serial data clock generated by the intel high definition audio controller (the intel ? ich6). this signal has an integrated pull-down resistor so that acz_bit_clk does not float when an intel high definition audio codec (or no codec) is connected but the signals are tem porarily configured as ac ?97. acz_sdout o ac ?97/intel high definition audio serial data out: this signal is a serial tdm data output to the codec(s). this serial output is double-pumped for a bit rate of 48 mb/s for intel high definition audio note: acz_sdout is sampled at the risi ng edge of pwrok as a functional strap. see section 2.22.1 for more details. there is a weak integrated pull-down resistor on the acz_sdout pin. acz_sdin[2:0] i ac ?97/intel high definition audio serial data in [2:0] : this signal is a serial tdm data inputs from the three codecs. th e serial input is single-pumped for a bit rate of 24 mb/s for intel high definition audio. these signals have integrated pull- down resistors, which are always enabled. table 2-18. miscellaneous signals (sheet 2 of 2) name type description
intel ? i/o controller hub 6 (ich6) family datasheet 71 signal description 2.20 general purpose i/o table 2-20. general purpose i/o signals 1,2 (sheet 1 of 2) name type tolerance power well description gpo[49] od o v_cpu_io core this signal is fixed as output only and can instead be used as cpupwrgd. gpo[48] o 3.3 v core this signal is fixed as output only and can instead be used as gnt4#. gpio[47:42] n/a n/a n/a this signal is not implemented. gpi[41] i 3.3 v core this signal is fixed as input only and can be used instead as ldrq1#. gpi[40] i5 v core this signal is fixed as input only and can be used instead as req4#. gpio[39:35] n/a n/a n/a this signal is not implemented. gpio[34:33] i/o 3.3 v core this signal can be input or output and is unmultiplexed gpio[32] (desktop only) i/o 3.3 v core this signal can be input or out put. in mobile, this gpio is not implemented and is used instead as clkrun#. gpi[31] i 3.3 v core this signal is fixed as input only and can instead be used for sata[3]gp. this signal is used only as gpi[31] in mobile. gpi[30] i 3.3 v core this signal is fixed as input only and can instead be used for sata[2]gp. gpi[29] i 3.3 v core this signal is fixed as input only and can instead be used for sata[1]gp. it is used only as gpi[29] in mobile. gpio[28:27] i/o 3.3 v resume this signal can be input or output and is unmultiplexed. gpi[26] i 3.3 v core this signal is fixed as input only and can instead be used for sata[0]gp. gpio[25] i/o 3.3 v resume this signal can be input or output and is unmultiplexed. it is a strap for internal vcc2_5 regulator. see section 2.22.1 . gpio[24] i/o 3.3 v resume this signal can be input or output and is unmultiplexed. gpo[23] o 3.3 v core this signal is fixed as output only. gpio[22] n/a n/a n/a this signal is not implemented gpo[21] o 3.3 v core this signal is fixed as output only and is unmultiplexed gpo[20] (desktop only) o 3.3 v core this signal is fixed as output only. in mobile, this gpo is not implemented and is used instead as stp_cpu#. gpo[19] o 3.3 v core this signal is fixed as output only. note: gpo[19] may be programmed to blink (controllable by gpo_blink (d31:f0:offset gpiobase+18h:bit 19)).
72 intel ? i/o controller hub 6 (i ch6) family datasheet signal description notes: 1. all inputs are sticky. the status bit remains set as lo ng as the input was asserted for two clocks. gpis are sampled on pci clocks in s0/s1 for desktop and s0 fo r mobile configurations. gpis are sampled on rtc clocks in s3/s4/s5 for desktop and s1 /s3/s4/s5 in mobile configurations. 2. some gpios exist in the vccsus3_3 power plane. care must be taken to make sure gpio signals are not driven high into powered-down planes. some ich6 gpios may be connected to pins on devices that exist in the core well. if these gpios are outputs, there is a danger that a loss of core power (pwrok low) or a power button override event will result in the intel ich6 driving a pin to a logic 1 to another device that is powered down. 3. gpi[15:0] can be configured to cause a smi# or sci. no te that a gpi can be routed to either an smi# or an sci, but not both. gpo[18] (desktop only) o 3.3 v core this signal is fixed as output only. in mobile configurations this gpo is not implemented and is used instead as stp_pci#. note: gpo[18] will blink by default immediately after reset (controllable by gpo_blink (d31:f0:offset gpiobase+18h:bit 18)). gpo[17] o 3.3 v core this signal is fixed as output only and can be used instead as pci gnt[5]#. gpo[16] o 3.3 v core this signal is fixed as output only and can be used instead as pci gnt[6]#. gpi[15:14] 3 i 3.3 v resume this signal is fixed as input only and can be used instead as oc[7:6]# gpi[13] 3 i 3.3 v resume this signal is fixed as input only and is unmultiplexed. gpi[12] 3 i 3.3 v core this signal is fixed as input only and is unmultiplexed. gpi[11] 3 i 3.3 v resume this signal is fixed as input only and can be used instead as smbalert#. gpi[10:9] 3 i 3.3 v resume this signal is fixed as input only and can be used instead as oc[5:4]#. gpi[8] 3 i 3.3 v resume this signal is fixed as input only and is unmultiplexed. gpi[7] 3 i 3.3 v core this signal is fixed as input only and is unmultiplexed. gpi[6] 3 (desktop only) i 3.3 v core this signal is fixed as input only. in mobile this gpi is not implemented and is used instead as bmbusy#. gpi[5:2] 3 i5 v core this signal is fixed as input only and can be used instead as pirq[h:e]#. gpi[1:0] 3 i5 v core this signal is fixed as input only and can be used instead as pci req[6:5]#. table 2-20. general purpose i/o signals 1,2 (sheet 2 of 2) name type tolerance power well description
intel ? i/o controller hub 6 (ich6) family datasheet 73 signal description 2.21 power and ground table 2-21. power and ground signals (sheet 1 of 2) name description vcc3_3 3.3 v supply for core well i/o buffers (22 pins). this power may be shut off in s3, s4, s5 or g3 states. vcc1_5_a 1.5 v supply for core well logic, group a (52 pi ns). this power may be shut off in s3, s4, s5 or g3 states. vcc1_5_b 1.5 v supply for core well logic, group b (45 pi ns). this power may be shut off in s3, s4, s5 or g3 states. vcc2_5 2.5 v supply for internal logic (2 pins). this power may be shut off in s3, s4, s5 or g3 states. note: this voltage may be generated internally (see section 2.22.1 for strapping option). if generated internally, these pins should not be connected to an external supply. v5ref reference for 5 v tolerance on core well inputs (2 pins). this power may be shut off in s3, s4, s5 or g3 states. vccsus3_3 3.3 v supply for resume well i/o buffers (20 pi ns). this power is not expected to be shut off unless the system is unplugged in desktop configur ations or the main battery is removed or completely drained and ac power is not available in mobile configurations. vccsus1_5 1.5 v supply for resume well logic (3 pin). th is power is not expected to be shut off unless the system is unplugged in desktop configurat ions or the main battery is removed or completely drained and ac power is not available in mobile configurations. this voltage may be generated internally (see section 2.22.1 for strapping option). if generated internally, these pins should not be connected to an external supply. v5ref_sus reference for 5 v tolerance on resume well inputs (1 pin). this power is not expected to be shut off unless the system is unplugged in de sktop configurations or the main battery is removed or completely drained and ac power is not available in m obile configurations. vcclan3_3 (mobile only) 3.3 v supply for lan connect interface buffers (4 pins). this is a separate power plane that may or may not be powered in s3?s5 states depending upon the presence or absence of ac power and network connectivity. this plane must be on in s0 and s1. note: in desktop mode these signals are added to the vccsus3_3 group. vcclan1_5 (mobile only) 1.5 v supply for lan controller logic (2 pins). this is a separate power plane that may or may not be powered in s3?s5 states dependi ng upon the presence or absence of ac power and network connectivity. this plane must be on in s0 and s1. notes: 1. this voltage will be generated internally if vccsus1_5 is generated internally (see section 2.22.1 for strapping option). if generated internally, these pins should not be connected to an external supply. 2. in desktop mode these signals are added to the vccsus1_5 group. vccrtc 3.3 v (can drop to 2.0 v min. in g3 state) supply for the rtc well (1 pin). this power is not expected to be shut off unless the rtc battery is removed or completely drained. note: implementations should not attempt to cl ear cmos by using a jumper to pull vccrtc low. clearing cmos in an ich6 -based platform can be done by using a jumper on rtcrst# or gpi. vccusbpll 1.5 v supply for core well logic (1 pin). this si gnal is used for the usb pll. this power may be shut off in s3, s4, s5 or g3 states. must be powered even if usb not used. vccdmipll 1.5 v supply for core well logic (1 pins). this signal is used fo r the dmi pll. this power may be shut off in s3, s4, s5 or g3 states.
74 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.22 pin straps 2.22.1 functional straps the following signals are used fo r static configuration. they ar e sampled at the rising edge of pwrok to select configurations (except as noted), and then revert later to their normal usage. to invoke the associated mode, the sign al should be driven at least four pci clocks prior to the time it is sampled. vccsatapll 1.5 v supply for core well logic (1 pins). this signal is used for the sata pll. this power may be shut off in s3, s4, s5 or g3 states. must be powered even if sata not used. v_cpu_io powered by the same supply as the processor i/ o voltage (3 pins). this supply is used to drive the processor interface signals listed in table 2-13 . vss grounds (172 pins). table 2-21. power and ground signals (sheet 2 of 2) name description table 2-22. functional strap definitions (sheet 1 of 2) signal usage when sampled comment gnt[6]#/ gpo[16] top-block swap override rising edge of pwrok the signal has a weak inter nal pull-up. if the signal is sampled low, this indicates that the system is strapped to the ?top-block swap? mode (ich6 inverts a16 for all cycles targeting fwh bios space). the status of this strap is readable via the top swap bit (chipset configuration registers:offset 3414h:bit 0). note that software will not be able to clear the top-swap bit until the system is rebooted without gnt6# being pulled down. linkalert# reserved this signal requires an external pull-up resistor. spkr no reboot rising edge of pwrok the signal has a weak internal pull-down. if the signal is sampled high, this indicates that the system is strapped to the ?no reboot? mode (ich6 will disable the tco timer system reboot feature). the status of this strap is readable via the no reboot bit (chipset configuration registers:offset 3410h:bit 5). intvrmen integrated vccsus1_5 vrm enable/ disable always this signal enables integrated vccsus1_5 vrm when sampled high. gpio[25] integrated vcc2_5 vrm enable/ disable rising edge of rsmrst# this signal enables integrated vcc2_5 vrm when sampled low. this signal has a weak internal pull-up during rsmrst# and is disabled within 100 ms after rsmrst# de-asserts. ee_cs reserved this signal has a weak internal pull-down. note: this signal should not be pulled high.
intel ? i/o controller hub 6 (ich6) family datasheet 75 signal description note: see section 3.1 for full details on pull-up/pull-down resistors. gnt[5]#/ gpo[17] boot bios destination selection rising edge of pwrok signal has a weak internal pull-up. allows for select memory ranges to be forwarded out the pci interface as opposed to the firmware hub. when sampled high, destination is lpc. also c ontrollable via boot bios destination bit (chipset configuration registers:offset 3410h:bit 3). note: this functionality intended for debug/testing only. ee_dout reserved this signal has a w eak internal pull-up. note: this signal should not be pulled low. acz_sdout xor chain entrance / pci express* port configu- ration bit 1 rising edge of pwrok allows entrance to xor chai n testing when tp[3] pulled low at rising edge of pwrok. see chapter 24 for xor chain functionality information. when tp[3] not pulled low at rising edge of pwrok, sets bit 1 of rpc.pc (chipset configuration registers:offset 224h). see section 7.1.30 for details. this signal has a weak internal pull-down. acz_sync pci express port configu- ration bit 0 rising edge of pwrok this signal has a weak internal pull-down. sets bit 0 of rpc.pc (chipset configuration registers:offset 224h). see section 7.1.30 for details. tp[1] (desktop only) / dprslpvr (mobile only) reserved this signal has a weak internal pull-down. note: this signal should not be pulled high. sataled# reserved this signal has a weak in ternal pull-up enabled only when pltrst# is asserted. note: this signal should not be pulled low. req[4:1]# xor chain selection rising edge of pwrok see chapter 24 for functionality information. tp[3] xor chain entrance rising edge of pwrok see chapter 24 for functionality information. this signal has a weak internal pull-up. note: this signal should not be pulled low unless using xor chain testing. table 2-22. functional strap definitions (sheet 2 of 2) signal usage when sampled comment
76 intel ? i/o controller hub 6 (i ch6) family datasheet signal description 2.22.2 external rtc circuitry to reduce rtc well power consumption, the ich6 impl ements an internal oscillator circuit that is sensitive to step voltage changes in vccrtc. figure 2-3 shows an example schematic recommended to ensure correct operation of the ich6 rtc. note: c1 and c2 depend on crystal load. 2.22.3 power sequencing requirements 2.22.3.1 v5ref / vcc3_3 se quencing requirements v5ref is the reference voltage for 5 v tolerance on inputs to the ich6. v5ref must be powered up before vcc3_3, or after vcc3_3 within 0.7 v. also, v5ref must power down after vcc3_3, or before vcc3_3 within 0.7 v. the rule must be follow ed in order to ensure the safety of the ich6. if the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the vcc3_3 rail. this rule also applies to v5re f_sus and vccsus3_3. however, in most platforms, the vccsus3_3 rail is derived from the 5 vsb on the power suppl y through a voltage regula tor and therefore, the vccsus3_3 rail will always come up after the v ccsus5 rail. as a result, v5ref_sus (which is derived directly from vccsus5) will always be pow ered up before vccsus3_3 and thus circuitry to satisfy the sequence requirement is not needed. however, in platforms that do not derive the vccsus3_3 rail from the vccsus5 rail, this rule must be observed in the platform design as described above. 2.22.3.2 3.3 v/1.5 v standby power sequencing requirements for platforms that use the integrated 1.5 v standby regulator, there are no power sequencing requirements for associated 3.3 v/1.5 v (standby or core) rails of the ich6. for platforms that use an external 1.5 v standby regulator to power vccsus1_5 of the ich6 (the internal voltage regulator is disabled), the platform must ensure that vccsus3_3 ramps up before vccsus1_5 or after vccsus1_5 within 0.7 v. vccsus1_5 must power down before vccsus3_3 or after vccsus3_3 within 0.7 v. figure 2-3. example external rtc circuit 32.768 khz xtal 1.0 f (20% tolerance) c2 15 pf (5% tolerance) vccrtc rtcx2 rtcx1 vbatt 1 f (20% tolerance) 1 k ? vccsus3_3 c1 15 pf (5% tolerance) + r1 10 m ? ? rtcrst# 20 k ? schottky diodes
intel ? i/o controller hub 6 (ich6) family datasheet 77 signal description vcclan3_3 (mobile only) must power up before vcclan1_5 (mobile only) or after vcclan1_5 within 0.7 v. vcclan1_5 must power down before vcclan3_3 or after vcclan3_3 within 0.7 v. 2.22.3.3 3.3 v/2.5 v powe r sequencing requirements for platforms that use the integrat ed 2.5 v regulator, there are no power sequencing requirements for associated 3.3 v/2.5 v rails of the ich6. for platforms that use an external 2.5 v regulato r to power vcc2_5 of the ich6 (the internal voltage regulator is disabled), the platform must ensure that vcc3_3 must power up before vcc2_5 or after vcc2_5 within 0.7 v. 2.22.3.4 vcc1_5/v_processor_io power sequencing requirements vcc1_5 must power up before v_cpu_io or after v_cpu_io within 0.3 v. v_cpu_io must power down before vcc1_5 or after vcc1_5 within 0.7 v. note: loaded from eeprom. if eeprom contains either 0000h or ffffh in the device id location, then 266ch is used. refer to the ich6 eeprom map and programming guide for lan device ids.
78 intel ? i/o controller hub 6 (i ch6) family datasheet signal description
intel ? i/o controller hub 6 (ich6) family datasheet 79 pin states 3 pin states 3.1 integrated pull-ups and pull-downs notes: 1. the pull-down resistors on acz_bit_clk (ac ?97) and acz_rst# are enabled when either: - the lso bit (bit 3) in the ac ?97 global c ontrol register (d30:f2:2c) is set to 1, or - both function 2 and function 3 of device 30 are disabled. otherwise, the integrated pu ll-down resistor is disabled. 2. the ac ?97/intel high definition audio link signal s may either all be configured to be an ac-link or an intel high definition audio link. table 3-1. integrated pull-up and pull-down resistors signal resistor type nominal value notes acz_bit_clk, ac ?97 pull-down 20k 1, 2, 3 acz_rst#, ac ?97 pull-down 20k 1, 2, 4 acz_sdin[2:0], ac ?97 pull-down 20k 2, 4 acz_sdout, ac ?97 pull-down 20k 2, 4, 5 acz_sync, ac ?97 pull-down 20k 2, 4, 5 acz_bit_clk, intel high definition audio pull-down 20k 2, 6, 7 acz_rst#, intel high definition audio none n/a 2 acz_sdin[2:0], intel high definition audio pull-down 20k 2, 4 acz_sdout, intel high definition audio pull-down 20k 1, 2 acz_sync, intel high definition audio pull-down 20k 2, 4 dd[7] pull-down 11.5k 8 ddreq pull-down 11.5k 8 dprslpvr / tp[1] pull-down 20k 4, 9 ee_cs pull-down 20k 10, 11 ee_din pull-up 20k 10 ee_dout pull-up 20k 10 gnt[3:0] pull-up 20k 10, 12 gnt[4]# / gpo[48] pull-up 20k 10, 12 gnt[5]# / gpo[17] pull-up 20k 10 gnt[6]# / gpo[16] pull-up 20k 10 gpio[25] pull-up 20k 10, 11 lad[3:0]# / fhw[3:0]# pull-up 20k 10 lan_rxd[2:0] pull-up 20k 13 lan_clk pull-down 100k 14 ldrq[0] pull-up 20k 10 ldrq[1] / gpi[41] pull-up 20k 10 pme# pull-up 20k 10 pwrbtn# pull-up 20k 10 sataled# pull-up 15k 15 spkr pull-down 20k 4 tp[3] pull-up 20k 16 usb[7:0] [p,n] pull-down 15k 17
80 intel ? i/o controller hub 6 (i ch6) family datasheet pin states 3. simulation data shows that these re sistor values can range from 10 k ? to 20 k ?. 4. simulation data shows that these resistor values can range from 9 k ? to 50 k ? . 5. the pull-down resistors on acz_sync (ac ?97) and acz_sdout (ac ?97) are enabled during reset and also enabled when either: - the lso bit (bit 3) in the ac ?97 global control register (d30:f2:2c) is set to 1, or - both function 2 and function 3 of device 30 are disabled. otherwise, the integrated pull-down resistor is disabled. 6. simulation data shows that these re sistor values can range from 10 k ? to 40 k ? . 7. the pull-down on this signal (in intel high definition audio mode) is only enabled when in s3 cold . 8. simulation data shows that these re sistor values can range from 5.7 k ? to 28.3 k ? . 9. the pull-up or pull-down on this signal is onl y enabled at boot/reset for strapping function. 10.simulation data shows that these resistor values can range from 15 k ? to 35 k ?. 11.the pull-down on this signal is onl y enabled when lan_rst# is asserted. 12.the internal pull-up is enabled only when the pcirst# pin is driven low and the pwrok indication is high. 13.simulation data shows that these re sistor values can range from 15 k ? to 30 k ?. 14.simulation data shows that these resistor values can range from 45 k ? to 170 k ?. 15.simulation data shows that these re sistor values can range from 10 k ? to 20 k ?. the internal pull-up is only enabled only during pltrst# assertion. 16. simulation data shows that these re sistor values can range from 10 k ? to 30 k ?. 17.simulation data shows that these re sistor values can range from 14.25 k ? to 24.8 k ? 3.2 ide integrated series termination resistors table 3-2 shows the ich6 ide signals that have integrated series termination resistors. note: simulation data indicates that the integrated series termination resistors are a nominal 33 ? but can range from 21 ? to 75 ? . 3.3 output and i/o signals planes and states table 3-3 and table 3-4 shows the power plane associated with the output and i/o signals, as well as the state at various times. within th e table, the following terms are used: ?high-z? tri-state. ich6 not driving the signal high or low. ?high? ich6 is driving the signal to a logic 1 ?low? ich6 is driving the signal to a logic 0 ?defined? driven to a level that is defined by the function (will be high or low) ?undefined? ich6 is driving the signa l, but the value is indeterminate. ?running? clock is toggling or signal is transitioning because function not stopping ?off? the power plane is off, so ich6 is not driving note that the signal levels are the same in s4 and s5, except as noted. table 3-2. ide series termination resistors signal integrated series termination resistor value dd[15:0], diow#, dior#, dreq, ddack#, iordy, da[2:0], dcs1#, dcs3#, ideirq approximately 33 ? (see note)
intel ? i/o controller hub 6 (ich6) family datasheet 81 pin states table 3-3. power plane and states for output and i/o signals for desktop configurations (sheet 1 of 4) signal name power plane during pltrst# 1 / rsmrst# 2 immediately after pltrst# 1 / rsmrst# 2 s1 s3 cold 3 s4/s5 pci express* petp[1], petn[1] petp[2], petn[2] petp[3], petn[3] petp[4], petn[4] vcc3_3 high high 4 defined off off pci bus ad[31:0] vcc3_3 low undefined defined off off c/be[3:0]# vcc3_3 low undefined defined off off devsel# vcc3_3 high-z high-z high-z off off frame# vcc3_3 high-z high-z high-z off off gnt[4:0]# vcc3_3 high with internal pull- ups high high off off gnt[5]# vcc3_3 high-z with internal pull- up high high off off gnt[6]# vcc3_3 high-z with internal pull- up high high off off irdy#, trdy# vcc3_3 high-z high-z high-z off off par vcc3_3 low undefined defined off off pcirst# vccsus3_3 low high high low low perr# vcc3_3 high-z high-z high-z off off plock# vcc3_3 high-z high-z high-z off off stop# vcc3_3 high-z high-z high-z off off lpc interface lad[3:0] / fwh[3:0] vcc3_3 high high high off off lframe# / fwh[4] vcc3_3 high high high off off lan connect and eeprom interface ee_cs vccsus3_3 low running defined defined defined ee_dout vccsus3_3 high high defined defined defined ee_shclk vccsus3_3 high-z running defined defined defined lan_rstsync vccsus3_3 high low defined defined defined lan_txd[2:0] vccsus3_3 low low defined defined defined
82 intel ? i/o controller hub 6 (i ch6) family datasheet pin states ide interface da[2:0] vcc3_3 undefined undefined undefined off off dcs1#, dcs3# vcc3_3 high high high off off dd[15:8], dd[6:0] vcc3_3 high-z high-z high-z off off dd[7] vcc3_3 low low low off off ddack# vcc3_3 high high high off off dior#, diow# vcc3_3 high high high off off sata interface sata[0]txp, sata[0]txn sata[1]txp, sata[1]txn sata[2]txp, sata[2]txn sata[3]txp, sata[3]txn vcc3_3 high-z high-z defined off off sataled# vcc3_3 high-z high-z defined off off satarbias vcc3_3 high-z high-z high-z off off interrupts pirq[a:h]# vcc3_3 high-z high-z high-z off off serirq vcc3_3 high-z high-z high-z off off usb interface usbp[7:0][p,n] vccsus3_3 low low low low low usbrbias vccsus3_3 high-z high-z defined defined defined power management pltrst# vccsus3_3 low high high low low slp_s3# vccsus3_3 low high high low low slp_s4# vccsus3_3 low high high high low slp_s5# vccsus3_3 low high high high low 5 sus_stat# vccsus3_3 low high high low low susclk vccsus3_3 low running table 3-3. power plane and states for output and i/o signals for desktop configurations (sheet 2 of 4) signal name power plane during pltrst# 1 / rsmrst# 2 immediately after pltrst# 1 / rsmrst# 2 s1 s3 cold 3 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 83 pin states processor interface a20m# v_cpu_io note 6 note 6 high off off cpupwrgd v_cpu_io note 7 high-z high-z off off cpuslp# v_cpu_io high high defined off off ignne# v_cpu_io note 6 note 6 high off off init# v_cpu_io high high high off off init3_3v# vcc3_3 high high high off off intr v_cpu_io note 8 note 8 low off off nmi v_cpu_io note 8 note 8 low off off smi# v_cpu_io high high high off off stpclk# v_cpu_io high high low off off smbus interface smbclk, smbdata vccsus3_3 high-z high-z defined defined defined system management interface smlink[1:0] vccsus3_3 high-z high-z defined defined defined linkalert# vccsus3_3 high-z high-z defined defined defined miscellaneous signals spkr vcc3_3 high-z with internal pull- down low defined off off ac ?97 interface acz_rst# vccsus3_3 low low cold reset bit (high) low low acz_sdout vcc3_3 low running low off off acz_sync vcc3_3 low running low off off intel high definition audio interface acz_rst# vccsus3_3 low low 9 low low low acz_sdout vcc3_3 high-z with internal pull- down running low off off acz_sync vcc3_3 high-z with internal pull- down running low off off acz_bit_clk vcc3_3 high-z with internal pull- down low 9 low off off table 3-3. power plane and states for output and i/o signals for desktop configurations (sheet 3 of 4) signal name power plane during pltrst# 1 / rsmrst# 2 immediately after pltrst# 1 / rsmrst# 2 s1 s3 cold 3 s4/s5
84 intel ? i/o controller hub 6 (i ch6) family datasheet pin states notes: 1. the states of vcc3_3 signals are taken at the times during pltrst# and immediately after pltrst#. 2. the states of vccsus3_3 signals are taken at the times during rsmrst# and immediately after rsmrst#. 3. in s3 hot , signal states are platform impl ementation specific, as some ex ternal components and interfaces may be powered when the ich6 is in the s3 hot state. 4. petp/n[4:1] high until port is enabled by software. 5. slp_s5# signals will be high in the s4 state. 6. ich6 drives these signals low before pwrok rising and high after the processor reset 7. cpupwrgd is an open-drain output that represents a logical and of the ich6?s vrmpwrgd and pwrok signals, and thus will be driven low by ich6 when ei ther vrmpwrgd or pwrok are inactive. during boot, or during a hard reset with power cycling, cpupwrgd will be expected to transi tion from low to high-z. 8. ich6 drives these signals low before pwro k rising and low after the processor reset. 9. low until intel high definition audio controller reset bit set (d 27:f0:offset hdbar+08h:bit 0), at which time acz_rst# will be high and acz_bit_clk will be running. 10.gpo[18] will toggle at a frequency of approximat ely 1 hz when the ich6 comes out of reset 11.gpio[25] transitions from pulled high internally to acti vely driven following the de-assertion of the rsmrst# pin. unmultiplexed gpio signals gpo[18] vcc3_3 high note 10 defined off off gpo[21:19] vcc3_3 high high defined off off gpo[23] vcc3_3 low low defined off off gpio[24] vccsus3_3 high high 11 defined defined defined gpio[25] vccsus3_3 high high defined defined defined gpio[28:27] vccsus3_3 high hi gh defined defined defined gpio[34:32] vcc3_3 high high defined off off table 3-3. power plane and states for output and i/o signals for desktop configurations (sheet 4 of 4) signal name power plane during pltrst# 1 / rsmrst# 2 immediately after pltrst# 1 / rsmrst# 2 s1 s3 cold 3 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 85 pin states table 3-4. power plane and states for output and i/o signals for mobile configurations (sheet 1 of 4) signal name power plane during pltrst# 6 / rsmrst# 7 immediately after pltrst# 6 / rsmrst# 7 c3/c4 s1 s3 cold 13 s4/s5 pci express* petp[1], petn[1] petp[2], petn[2] petp[3], petn[3] petp[4], petn[4] vcc3_3 high high 12 defined defined off off pci bus ad[31:0] vcc3_3 low undefined defined defined off off c/be[3:0]# vcc3_3 low undefined defined defined off off clkrun# vcc3_3 low low defined off off devsel# vcc3_3 high-z high-z high-z high-z off off frame# vcc3_3 high-z high-z high-z high-z off off gnt[4:0]# vcc3_3 high with internal pull- ups high high high off off gnt[5]# vcc3_3 high-z with internal pull- up high high high off off gnt[6]# vcc3_3 high-z with internal pull- up high high high off off irdy#, trdy# vcc3_3 high-z high-z high-z high-z off off par vcc3_3 low undefined defined defined off off pcirst# vccsus3_3 low high high high low low perr# vcc3_3 high-z high-z high-z high-z off off plock# vcc3_3 high-z high-z high-z high-z off off stop# vcc3_3 high-z high-z high-z high-z off off lpc interface lad[3:0] / fwh[3:0] vcc3_3 high high high high off off lframe# / fwh[4] vcc3_3 high high high high off off
86 intel ? i/o controller hub 6 (i ch6) family datasheet pin states lan connect and eeprom interface ee_cs vcclan3_3 low running defined defined note 4 note 4 ee_dout vcclan3_3 high high defined defined note 4 note 4 ee_shclk vcclan3_3 low running defined defined note 4 note 4 lan_rstsync vcclan3_3 high low defined defined note 4 note 4 lan_txd[2:0] vcclan3_3 low low defined defined note 4 note 4 ide interface da[2:0] vcc3_3 undefined undefined undefined undefined off off dcs1#, dcs3# vcc3_3 high high high high off off dd[15:8], dd[6:0] vcc3_3 high-z high-z defined high-z off off dd[7] vcc3_3 low low defined low off off ddack# vcc3_3 high high high high off off dior#, diow# vcc3_3 high high high high off off sata interface sata[0]txp, sata[0]txn sata[2]txp, sata[2]txn vcc3_3 high-z high-z defined defined off off sataled# vcc3_3 high-z high-z defined defined off off satarbias vcc3_3 high-z high-z defined defined off off interrupts pirq[a:h]# vcc3_3 high-z high-z defined high-z off off serirq vcc3_3 high-z high-z running high-z off off usb interface usbp[7:0][p,n] vccsus3_3 low low low low low low usbrbias vccsus3_3 high-z high-z defined defined defined defined power management pltrst# vccsus3_3 low high high high low low slp_s3# vccsus3_3 low high high high low low slp_s4# vccsus3_3 low high high high high low slp_s5# vccsus3_3 low high high high high low 10 stp_pci# vcc3_3 high high defined high low low stp_cpu# vcc3_3 high high low high low low sus_stat# vccsus3_3 low high high high low low dprslpvr vcc3_3 low low low/high 5 high off off table 3-4. power plane and states for output and i/o signals for mobile configurations (sheet 2 of 4) signal name power plane during pltrst# 6 / rsmrst# 7 immediately after pltrst# 6 / rsmrst# 7 c3/c4 s1 s3 cold 13 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 87 pin states dprstp# vcc3_3 high high low/high 5 high off off susclk vccsus3_3 low running processor interface a20m# v_cpu_io see note 1 see note 1 defined high off off cpupwrgd vcc3_3 see note 3 high-z high-z high-z off off cpuslp# v_cpu_io high high high defined off off ignne# v_cpu_io see note 1 see note 1 high high off off init# v_cpu_io high high high high off off init3_3v# vcc3_3 high high high high off off intr v_cpu_io see note 8 see note 8 defined low off off nmi v_cpu_io see note 8 see note 8 defined low off off smi# v_cpu_io high high defined high off off stpclk# v_cpu_io high high low low off off dpslp# v_cpu_io high high high/low high off off smbus interface smbclk, smbdata vccsus3_3 high-z high-z def ined defined defined defined system management interface smlink[1:0] vccsus3_3 high-z hi gh-z defined defined defined defined linkalert# vccsus3_3 high-z high- z defined defined defined defined miscellaneous signals spkr vcc3_3 high-z with internal pull- down low defined defined off off ac ?97 interface acz_rst# vccsus3_3 low low high cold reset bit (high) low low acz_sdout vcc3_3 low running running low off off acz_sync vcc3_3 low running running low off off table 3-4. power plane and states for output and i/o signals for mobile configurations (sheet 3 of 4) signal name power plane during pltrst# 6 / rsmrst# 7 immediately after pltrst# 6 / rsmrst# 7 c3/c4 s1 s3 cold 13 s4/s5
88 intel ? i/o controller hub 6 (i ch6) family datasheet pin states notes: 1. ich6 drives these signals low before pwrok rising and high after the processor reset. 2. gpio[18] will toggle at a frequency of approximat ely 1 hz when the ich6 comes out of reset 3. cpupwrgd is an open-drain output that represents a logical and of the ich6?s vrmpwrgd and pwrok signals, and thus will be driven low by ich6 when ei ther vrmpwrgd or pwrok are inactive. during boot, or during a hard reset with power cycling, cpupwrgd will be expected to transi tion from low to high-z. 4. lan connect and eeprom signals will either be ?defined? or ?off? in s3-s5 states depending upon whether or not the lan power planes are active. 5. the state of the dprslpvr and dprstp# signals in c4 are high if deeper sleep is enabled or low if it is disabled. 6. the states of vcc3_3 signals are taken at the times during pltrst# and immediately after pltrst#. 7. the states of vccsus3_3 signals are taken at the ti mes during rsmrst# and immediately after rsmrst#. 8. ich6 drives these signals low before pwro k rising and low after the processor reset. 9. gpio[25] transitions from pulled high internally to actively driven follow ing the de-assertion of the rsmrst# pin. 10.slp_s5# signals will be high in the s4 state. 11.low until intel high definition audio controller reset bit set (d 27:f0:offset hdbar+08h:bit 0), at which time acz_rst# will be high and acz_bit_clk will be running. 12.petp/n[4:1] high until port is enabled by software. 13.in s3 hot , signal states are platform impl ementation specific, as some ex ternal components and interfaces may be powered when the ich6 is in the s3 hot state. intel high definition audio interface acz_rst# vccsus3_3 low low 11 high tbd low low acz_sdout vcc3_3 high-z with internal pull- down running running low off off acz_sync vcc3_3 high-z with internal pull- down running running low off off acz_bit_clk vcc3_3 high-z with internal pull- down low 11 running low off off unmultiplexed gpio signals gpo[19] vcc3_3 high high defined defined off off gpo[21] vcc3_3 high high defined defined off off gpo[23] vcc3_3 low low defined defined off off gpio[24] vccsus3_3 high high defined defined defined defined gpio[25] vccsus3_3 high high9 defined defined defined defined gpio[28:27] vccsus3_3 high high de fined defined defined defined gpio[34:33] vcc3_3 high hi gh defined defined off off table 3-4. power plane and states for output and i/o signals for mobile configurations (sheet 4 of 4) signal name power plane during pltrst# 6 / rsmrst# 7 immediately after pltrst# 6 / rsmrst# 7 c3/c4 s1 s3 cold 13 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 89 pin states 3.4 power planes for input signals table 3-5 and table 3-6 shows the power plane associated with each input signal, as well as what device drives the signal at various times. valid states include: high low static: will be high or low, but will not change driven: will be high or low, and is allowed to change running: for input clocks table 3-5. power plane for input signals for desktop configurations (sheet 1 of 3) signal name power well driver during reset s1 s3 cold 1 s4/s5 a20gate vcc3_3 external microcontroller static low low acz_bit_clk (ac ?97 mode) vcc3_3 ac ?97 codec low low low acz_sdin[2:0] (ac ?97 mode) vccsus3_3 ac ?97 codec low low low acz_sdin[2:0] (intel high definition audio mode) vccsus3_3 intel high definition audio codec low low low clk14 vcc3_3 clock generator running low low clk48 vcc3_3 clock generator running low low ddreq vcc3_3 ide device static low low dmi_clkp, dmi_clkn vcc3_3 clock generator running low low ee_din vccsus3_3 eeprom component driven driven driven ferr# v_cpu_io processor static low low gpi[6] vcc3_3 external device or external pull-up/pull-down driven off off gpi[7] vcc3_3 external device or external pull-up/pull-down driven off off gpi[8] vccsus3_3 external device or external pull-up/pull-down driven driven driven gpi[12] vcc3_3 external device or external pull-up/pull-down driven driven driven gpi[13] vccsus3_3 external device or external pull-up/pull-down driven driven driven perp[1], pern[1] perp[2], pern[2] perp[3], pern[3] perp[4], pern[4] vcc3_3 pci express* device driven driven driven
90 intel ? i/o controller hub 6 (i ch6) family datasheet pin states dmi[0]rxp, dmi[0]rxn dmi[1]rxp, dmi[1]rxn dmi[2]rxp, dmi[2]rxn dmi[3]rxp, dmi[3]rxn vcc3_3 (g)mch driven low low ideirq vcc3_3 ide static low low intruder# vccrtc external switch driven driven driven intvrmen vccrtc external pull-up or pull-down driven driven driven iordy vcc3_3 ide device static low low lan_clk vccsus3_3 lan connect component driven driven driven lan_rst# vccsus3_3 external rc circuit high high high lan_rxd[2:0] vccsus3_3 lan connec t component driven driven driven ldrq0# vcc3_3 lpc devices high low low ldrq1# vcc3_3 lpc devices high low low mch_sync# vcc3_3 (g)mch driven low low oc[7:0]# vccsus3_3 external pull-ups driven driven driven pciclk vcc3_3 clock generator running low low pme# vccsus3_3 internal pull-up driven driven driven pwrbtn# vccsus3_3 internal pull-up driven driven driven pwrok vccrtc system power supply driven low low rcin# vcc3_3 external microcontroller high low low req[6:0]# vcc3_3 pci master driven low low ri# vccsus3_3 serial port buffer driven driven driven rsmrst# vccrtc external rc circuit high high high rtcrst# vccrtc external rc circuit high high high sata_clkp, sata_clkn vcc3_3 clock generator running low low sata[0]rxp, sata[0]rxn sata[1]rxp, sata[1]rxn sata[2]rxp, sata[2]rxn sata[3]rxp, sata[3]rxn vcc3_3 sata drive driven driven driven satarbias# vcc3_3 external pull-down driven driven driven sata[3:0]gp / gpi[31:29,26] vcc3_3 external device or external pull-up/pull-down driven driven driven serr# vcc3_3 pci bus peripherals high low low table 3-5. power plane for input signals fo r desktop configurations (sheet 2 of 3) signal name power well driver during reset s1 s3 cold 1 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 91 pin states notes: 1. in s3 hot , signal states are platform implementation spec ific, as some external components and interfaces may be powered when the ich6 is in the s3 hot state. smbalert# vccsus3_3 external pull-up driven driven driven sys_reset# vccsus3_3 external circuit driven driven driven thrm# vcc3_3 thermal sensor driven low low thrmtrip# v_cpu_io thermal sensor driven low low tp[0] vccsus3_3 external pull-up high high high tp[3] vccsus3_3 internal pull-up high high high usbrbias# vccsus3_3 external pull-down driven driven driven vrmpwrgd vcc3_3 processor voltage regulator high low low wake# vccsus3_3 external pull-up driven driven driven table 3-5. power plane for input signals for desktop configurations (sheet 3 of 3) signal name power well driver during reset s1 s3 cold 1 s4/s5 table 3-6. power plane for input signals fo r mobile configurations (sheet 1 of 3) signal name power well driver during reset c3/c4 s1 s3 cold 1 s4/s5 a20gate vcc3_3 external micr ocontroller static static low low acz_bit_clk (ac ?97 mode) vcc3_3 ac ?97 codec driven low low low acz_sdin[2:0] (ac ?97 mode) vccsus3_3 ac ?97 codec driven low low low acz_sdin[2:0] (intel high definition audio mode) vccsus3_3 intel high definition audio codec driven low low low bmbusy# vcc3_3 graphics component [(g)mch] driven high low low batlow# vccsus3_3 power supply high high high high clk14 vcc3_3 clock generator running running low low clk48 vcc3_3 clock generator running running low low ddreq vcc3_3 ide device driven static low low dmi_clkp dmi_clkn vcc3_3 clock generator running running low low ee_din vcclan3_3 eeprom component driven driven note 2 note 2 ferr# v_cpu_io processor static static low low gpi[7] vcc3_3 external device or external pull-up/pull-down driven driven off off gpi[8] vccsus3_3 external device or external pull-up/pull-down driven driven driven driven gpi[12] vcc3_3 external device or external pull-up/pull-down driven driven driven driven
92 intel ? i/o controller hub 6 (i ch6) family datasheet pin states gpi[13] vccsus3_3 external device or external pull-up/pull-down driven driven driven driven gpi[29] vcc3_3 external device or external pull-up/pull-down driven driven driven driven gpi[31] vcc3_3 external device or external pull-up/pull-down driven driven driven driven perp[1], pern[1] perp[2], pern[2] perp[3], pern[3] perp[4], pern[4] vcc3_3 pci express* device driven driven driven driven dmi[0]rxp, dmi[0]rxn dmi[1]rxp, dmi[1]rxn dmi[2]rxp, dmi[2]rxn dmi[3]rxp, dmi[3]rxn vcc3_3 (g)mch driven driven low low ideirq vcc3_3 ide driven static low low intruder# vccrtc external swit ch driven driven driven driven intvrmen vccrtc external pull-up or pull- down driven driven driven driven iordy vcc3_3 ide device static static low low lan_clk vcclan3_3 lan connect component driven driven note 2 note 2 lan_rst# vccsus3_3 power supply high high static static lan_rxd[2:0] vcclan3_3 lan connect component driven driven note 2 note 2 ldrq0# vcc3_3 lpc devices driven high low low ldrq1# vcc3_3 lpc devices driven high low low mch_sync# vcc3_3 (g)mch driven driven low low oc[7:0]# vccsus3_3 external pull- ups driven driven driven driven pciclk vcc3_3 clock generator running running low low pme# vccsus3_3 internal pull-up driven driven driven driven pwrbtn# vccsus3_3 internal pull-up driven driven driven driven pwrok vccrtc system power supply driven driven low low rcin# vcc3_3 external microcontroller high high low low req[6:0]# vcc3_3 pci master driven driven low low ri# vccsus3_3 serial port bu ffer driven driven driven driven rsmrst# vccrtc external rc circuit high high high high rtcrst# vccrtc external rc circuit high high high high table 3-6. power plane for input signals for mobile configurations (sheet 2 of 3) signal name power well driver during reset c3/c4 s1 s3 cold 1 s4/s5
intel ? i/o controller hub 6 (ich6) family datasheet 93 pin states notes: 1. in s3 hot , signal states are platform implementation specific, as some some external components and interfaces may be powered when the ich6 is in the s3 hot state. 2. lan connect and eeprom signals will either be ?driv en? or ?low? in s3?s5 states depending upon whether or not the lan power planes are active. sata_clkp, sata_clkn vcc3_3 clock generator running running low low sata[0]rxp, sata[0]rxn sata[2]rxp, sata[2]rxn vcc3_3 sata drive driven driven driven driven satarbias# vcc3_3 external pull -down driven driven driven driven sata[2,0]gp vcc3_3 external device or external pull-up/pull-down driven driven driven driven serr# vcc3_3 pci bus peripherals driven high low low smbalert# vccsus3_3 external pull -up driven driven driven driven sys_reset# vccsus3_3 external circ uit driven driven driven driven thrm# vcc3_3 thermal sensor driven driven low low thrmtrip# v_cpu_io thermal sensor driven driven low low tp[3] vccsus3_3 internal pull-up high high high high usbrbias# vccsus3_3 external pull -down driven driven driven driven vrmpwrgd vcc3_3 processor voltage regulator driven driven low low wake# vccsus3_3 external pull-up driven driven driven driven table 3-6. power plane for input signals fo r mobile configurations (sheet 3 of 3) signal name power well driver during reset c3/c4 s1 s3 cold 1 s4/s5
94 intel ? i/o controller hub 6 (i ch6) family datasheet pin states
intel ? i/o controller hub 6 (ich6) family datasheet 95 system clock domains 4 system clock domains table 4-1 shows the ich6 and system clock domains. figure 4-1 and figure 4-2 shows the assumed connection of the various system comp onents, including the clock generator in both desktop and mobile systems. for complete details of the system clocking solution, refer to the system?s clock generato r component specification. table 4-1. intel ? ich6 and system clock domains clock domain frequency source usage intel ? ich6 sata_clkp, sata_clkn 100 mhz main clock generator differential clock pair used for sata. ich6 dmi_clkp, dmi_clkn 100 mhz main clock generator differential clock pair used for dmi. ich6 pciclk 33 mhz main clock generator free-running pci clock to intel ? ich6. this clock remains on during s0 and s1 (in desktop) state, and is expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. system pci 33 mhz main clock generator pci bus, lpc i/f. these only go to external pci and lpc devices. will stop based on clkrun# (and stp_pci#) in mobile configurations. ich6 clk48 48.000 mhz main clock generator super i/o, usb controllers. expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. ich6 clk14 14.31818 mhz main clock generator used for acpi timer and multimedia timers. expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. ich6 acz_bit_clk 12.288 mhz ac ?97 codec ac-link. generated by ac ?97 codec. can be shut by codec in d3. expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations. note: for use only in ac ?97 mode. lan_clk 5 to 50 mhz lan connect component generated by the lan connect component. expected to be shut off during s3 or below in desktop configurations or s1 or below in mobile configurations.
96 intel ? i/o controller hub 6 (i ch6) family datasheet system clock domains figure 4-1. desktop conceptual system clock diagram intel ? ich6 pci clocks (33 mhz) clock gen. 14.31818 mhz 48.000 mhz 32 khz xtal susclk# (32 khz) lan connect 50 mhz ac ?97 codec(s) 12.288 mhz 33 mhz 14.31818 mhz 100 mhz diff. pair 1 to 6 differential clock fan out device sata 100 mhz diff. pair dmi 100 mhz diff. pair pci express 100 mhz diff. pairs high definition audio codec(s) 24 mhz 48.000 mhz figure 4-2. mobile conceptual clock diagram intel ? ich6-m 32 khz xtal susclk# (32 khz) 14.31818 mhz stp_cpu# stp_pci# pci clocks (33 mhz) clock gen. 14.31818 mhz 48 mhz lan connect 100 mhz diff. pair 1 to 6 differential clock fan out device sata 100 mhz diff. pair dmi 100 mhz diff. pair pci express 100 mhz diff. pairs ac ?97 codec(s) 12.288 mhz intel ? hd audio codec(s) 24 mhz 50 mhz 48.000 mhz 33 mhz
intel ? i/o controller hub 6 (ich6) family datasheet 97 functional description 5 functional description this chapter describes the functions and interfaces of the ich6 family. 5.1 pci-to-pci bridge (d30:f0) the pci-to-pci bridge resides in pci device 30, function 0 on bus #0. this portion of the ich6 implements the buffering and control logic between pci and direct media interface (dmi). the arbitration for the pci bus is handled by this pci device. the pci decoder in this device must decode the ranges for the dmi. all register cont ents are lost when core well power is removed. direct media interface (dmi) is the chip-to-chip connection between the memory controller hub / graphics and memory controller hub ((g)mch) and i/o controller hub 6 (ich6). this high- speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. base func tionality is completely software transparent permitting current and legacy software to operate normally. in order to provide for true isochronous transf ers and configurable quality of service (qos) transactions, the ich6 supports two virtual channe ls on dmi: vc0 and vc1. these two channels provide a fixed arbitration scheme where vc1 is always the highes t priority. vc0 is the default conduit of traffic for dmi and is always enabled. vc1 must be specifically enabled and configured at both ends of the dmi link (i.e., the ich6 and (g)mch). configuration registers for dmi, virtual channel support, and dmi active state power management (aspm) are in the rcrb space in the chipset configuration registers ( section 7 ). 5.1.1 pci bus interface the ich6 pci interface provides a 33 mhz, pci local bus specification, revision 2.3 -compliant implementation. all pci signals are 5 v tolerant (e xcept pme#). the ich6 in tegrates a pci arbiter that supports up to seven external pci bus masters in addition to the internal ich6 requests. 5.1.2 pci bridge as an initiator the bridge initiates cycles on the pci bus when granted by the pci arbiter. the bridge generates the cycle types shown in table 5-1 . table 5-1. pci bridge initiator cycle types command c/be# notes i/o read/write 2h/3h non-posted memory read/write 6h/7h writes are posted configuration read/write ah/bh non-posted special cycles 1h posted
98 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.1.2.1 memory reads and writes the bridge bursts memory writes on pci that are received as a singl e packet from dmi. the bridge will perform write combining if bpc.wce (d30:f0:offset 4ch:bit 31) is set. 5.1.2.2 i/o reads and writes the bridge generates single dw i/o read and write cycles. when the cycle completes on pci bus, the bridge generates a corresponding completion on dmi. if the cycle is retried, the cycle is kept in the downbound queue and may be passed by a postable cycle. 5.1.2.3 configuratio n reads and writes the bridge generates single dw configuration read and write cycles. when the cycle completes on pci bus, the bridge generates a corresponding completion . if the cycle is retried, the cycle is kept in the downbound queue and may be passed by a postable cycle. 5.1.2.4 locked cycles the bridge propagates locks from dmi per the pc i specification. the pci bridge implements bus lock, which means the arbite r will not grant to any agen t except dmi while locked. if a locked read results in a target or master abort, the lock is not established (as per the pci specification). agents north of the ich6 must not fo rward a subsequent locked read to the bridge if they see the first one finish with a failed completion. 5.1.2.5 target / master aborts when a cycle initiated by the bri dge is master/target aborted, th e bridge will not re-attempt the same cycle. for multiple dw cycles, the bridge in crements the address and attempts the next dw of the transaction. for all non-postable cycles, a ta rget abort response pack et is returned for each dw that was master or target aborted on pci. the bridge drops post ed writes that abort. 5.1.2.6 secondary master latency timer the bridge implements a master latency timer via the slt register which, upon expiration, causes the de-assertion of frame# at the next legal clock edge when there is another active request to use the pci bus. 5.1.2.7 dual addr ess cycle (dac) the bridge will issue full 64-bit dual address cy cles for device memory-mapped registers above 4gb.
intel ? i/o controller hub 6 (ich6) family datasheet 99 functional description 5.1.2.8 memory and i/o decode to pci the pci bridge in the ich6 is a subtractive decode agent , which follows the following rules when forwarding a cycle from dmi to the pci interface: ? the pci bridge will positively decode any memory i/o address within its window registers, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set for memory windows and pcicmd.iose (d30:f0:offset 04h:bit 0) is set for i/o windows. ? the pci bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming pcicmd.mse (d30:f0:offset 04h:bit 1) is set. ? the pci bridge will subtractively decode any 16-bit i/o address not claimed by another agent assuming pcicmd.iose (d30:f0:offset 04h:bit 0) set ? if bctrl.ie (d30:f0:offset 3eh:bit 2) is set, the pci bridge will not positively forward from primary to secondary called out ranges in the i/o window per pci specification (i/o transactions addressing the last 768 bytes in each, 1- kb block: offsets 100h to 3ffh). the pci bridge will still take them subtractively assuming the above rules. ? if bctrl.vgae (d30:f0:offset 3eh:bit 3) is set, the pci bridge will positively forward from primary to secondary i/o and memory ranges as called out in the pci bridge specification, assuming the above rules are met. 5.1.3 parity error det ection and generation pci parity errors can be detected and reported. the following behavioral rules apply: ? when a parity error is detected on pci, th e bridge sets the secsts.dpe (d30:f0:offset 1eh:bit 15). ? if the bridge is a master and bctrl.pere (d30:f 0:offset 3eh:bit 0) and one of the parity errors defined below is detected on pci, then the bridge will set secsts.dpd (d30:f0:offset 1eh:bit 8) and will also generate an internal serr#. ? during a write cycle, the perr# signal is active, or ? a data parity error is detected while performing a read cycle ? if an address or command parity error is det ected on pci and pcicmd.see (d30:f0:offset 04h:bit 8), bctrl.pere, and bctrl.see (d30:f0:o ffset 3eh:bit 1) are all set, the bridge will set the psts.sse (d30:f0:offset 06h: bit 14) and generate an internal serr#. ? if the psts.sse is set because of an address parity error and the pcicmd.see is set, the bridge will generate an internal serr#. ? when bad parity is detected from dmi, bad parity will be driven on all data the bridge. ? when an address parity error is detected on pci, the pci bridge will never claim the cycle. this is a slight deviation from the pci bridge spec, which says that a cycle should be claimed if bctrl.pere is not set. however, dmi does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction.
100 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.1.4 pcirst# the pcirst# pin is generated under two conditions: ? pltrst# active ? bctrl.sbr (d30:f0:offset 3eh:bit 6) set to 1 the pcirst# pin is in the resume well. pcirst# should be tied to pci bus agents, but not other agents in the system. 5.1.5 peer cycles the following peer cycles are su pported: pci express to pci express graphics (writes only), pci to pci express graphics (writes only) and pci to pci. note: the ich6?s ac ?97, ide and usb controll ers cannot perform p eer-to-peer traffic. 5.1.6 pci-to-pci bridge model from a software perspective, th e ich6 contains a pci-to-pci bridge. this bridge connects dmi to the pci bus. by using the pci-to-pci bridge soft ware model, the ich6 can have its decode ranges programmed by existing plug-and-play software such that pci ranges do not conflict with graphics aperture ranges in the host controller. 5.1.7 idsel to device number mapping when addressing devices on the ex ternal pci bus (with the pci slots), the ich6 asserts one address signal as an idsel. when accessing device 0, th e ich6 asserts ad16. when accessing device 1, the ich6 asserts ad17. this mapping continues all the way up to device 15 where the ich6 asserts ad31. note that the ich6?s internal functions (ac ?97, intel high definition audio, ide, usb, sata and pci bridge) are e numerated like they are off of a separate pci bus (dmi) from the external pci bus. the integrated lan controller is device 8 on the ich6?s pci bus, and hence it uses ad[24] for idsel. 5.1.8 standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci local bus specification, revision 2.3 defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mech anism implemente d within the ich6. the pci local bus specification, revision 2.3 defines two mechanisms to access configuration space, mechanism 1 and mechan ism 2. the ich6 only supports mechanism 1. warning: configuration writes to internal devices, when th e devices are disabled, are illegal and may cause undefined results.
intel ? i/o controller hub 6 (ich6) family datasheet 101 functional description 5.2 pci express* root ports (d28:f0,f1,f2,f3) pci express is the next generation high performance general input/output architecture. pci express is a high speed, low voltage, serial pathway for two devices to communicate simultaneously by implementing dual unidirectio nal paths between two devices. pci express has been defined to be 100-percent compatible with conventional pci compliant operating systems and their corresponding bus enumeration and configuration software. all pci express hardware elements have been defined with a pci-co mpatible configuration space representation. pci express replaces the device-base d arbitration process of conven tional pci with flow-control - based link arbitration that allows data to pass up and down the link based upon traffic class priority. high priority is given to traffi c classes that require guaranteed bandwidth such as isochronous transactions while room is simultaneously made for lower priority transactions to avoid bottlenecks. the ich6 provides 4 (x1) pci express ports with each port supporting up to 5 gb/s concurrent bandwidth (2.5 gb/s in each direct ion). these all reside in device 28 , and take function 0 ? 3. port 1 is function 0, port 2 is f unction 1, port 3 is function 2, and port 4 is function 3. 5.2.1 interrupt generation the root port generates interrupts on behalf of hot-plug and power management events, when enabled. these interrupts can either be pin based, or can be msis, when enabled. when an interrupt is generated via the legacy pin, the pin is internally routed to the ich6 interrupt controllers. the pin that is driven is based upon the setting of the chipset configuration registers. specifically, the chipset configur ation registers used are the d2 8ip (base address + 310ch) and d28ir (base address + 3146h) registers. the following table summarizes interrupt behavior for msi and wire-modes. in the table ?bits? refers to the hot-plug and pme interrupt bits. table 5-2. msi vs. pci irq actions interrupt register wire-mode action msi action all bits 0 wire inactive no action one or more bits set to 1 wire active send message one or more bits set to 1, new bit gets set to 1 wire active send message one or more bits set to 1, software cl ears some (but not all) bits wire active send message one or more bits set to 1, software clears all bits wire inactive no action software clears one or more bits, and one or more bits are set on the same clock wire active send message
102 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.2.2 power management 5.2.2.1 s3/s4/s5 support software initiates the transition to s3/s4/s5 by pe rforming an i/o write to the power management control register in the ich6. after the i/o write completion has been returned to the processor, each root port will send a pme_turn_off tlp (transaction layer packet) message on it's downstream link. the device att ached to the link will eventua lly respond with a pme_to_ack tlp message followed by sending a pm_enter_l23 dllp (data link layer packet) request to enter the l2/l3 ready state. when all of the ich6 root ports links are in th e l2/l3 ready state, the ich6 power management control logic will proceed with the entry into s3/s4/s5. prior to entering s3, software is required to put each device into d3 hot . when a device is put into d3 hot it will initiate entry into a l1 link state by sending a pm_enter_l1 dllp. thus under normal operating conditions when the root ports sends the pme_turn_off message the link will be in state l1. however, when the root port is instructed to send the pme_turn_off message, it will send it whether or not the link was in l1. endpoints attached to ich6 can make no assumptions about the state of the link prior to receiving a pme_turn_off message. 5.2.2.2 resuming from suspended state the root port contains enough circuitry in the resume well to detect a wake event thru the wake# signal and to wake the system. when wake# is detect ed asserted, an internal signal is sent to the power management controller of the ich6 to cause the system to wake up. this internal message is not logged in any register, nor is an interrupt/gpe generated due to it. 5.2.2.3 device initiated pm_pme message when the system has returned to a working state fr om a previous low po wer state, a device requesting service will send a pm_pme message continuously, until acknowledge by the root port. the root port will take different actions depending upon whether this is the first pm_pme has been received, or whether a previous message has been received but not yet serv iced by the operating system. if this is the first message received (rsts.ps - d28:f0/f1/f2/f3:offset 60h:bit 16 is cleared), the root port will set rsts.ps, and log the pme requester id into rsts.rid (d28:f0/f1/f2/ f3:offset 60h:bits 15:0). if an interrupt is enabled via rctl.pie (d28:f0/f1/f2/f3:offset 5ch:bit 3), an interrupt will be generated. this in terrupt can be either a pin or an msi if msi is enabled via mc.msie (d28:f0/f1/f2/f3:offset 82h:bit 0). see section 5.2.2.4 for smi/sci generation. if this is a subsequent message received (rsts.ps is already set), the r oot port will set rsts.pp (d28:f0/f1/f2/f3:offset 60h:bit 17) and log the pme requester id from the message in a hidden register. no other action will be taken. when the first pme event is cleared by software clearing rsts.ps, the root port will set rsts.ps, clear rsts.pp, and move the requester id from the hidden register into rsts.rid. if rctl.pie is set, generate an interrupt. if rctl.pie is not set, send over to the power management controller so that a gpe can be set. if messages have been l ogged (rsts.ps is set), and rctl.pie is later written from a 0 to a 1, a nd interrupt must be generated. this last condition handles the case where the message was receive d prior to the operating system re-enabling interrupts after resuming from a low power state.
intel ? i/o controller hub 6 (ich6) family datasheet 103 functional description 5.2.2.4 smi/sci generation interrupts for power management events are not supported on legacy operating systems. to support power management on non-pci express aware operat ing systems, pm events can be routed to generate sci. to generate sci, mpc.pmce must be set. when set, a power management event will cause smscs.pmcs (d28:f0/f1/f2/f3:offset dch:bit 31) to be set. additionally, bios workarounds for power manage ment can be supported by setting mpc.pmme (d28:f0/f1/f2/f3:offset d8h:bit 0). when this bit is set, power management events will set smscs.pmms (d28:f0/f1/f2/f3:offset dch:bit 0), a nd smi # will be generated. this bit will be set regardless of whether interrupts or sci is enab led. the smi# may occur concurrently with an interrupt or sci. 5.2.3 serr# generation serr# may be generated via two paths; through pci mechanisms involving bits in the pci header, or through pci express mechanisms involving bits in the pci express capability structure. 5.2.4 hot-plug each root port implements a hot-plug controller which performs the following: ? messages to turn on / off / blink leds ? presence and attenti on button detection ? interrupt generation the root port only allows hot-plug with module s (e.g., expresscard*). edge-connector based hot- plug is not supported. 5.2.4.1 presence detection when a module is plugged in and power is supplied , the physical layer will detect the presence of the device, and the root port sets slsts. pds (d28:f0/f1/f2/f3:offset 5ah:bit 6) and slsts.pdc (d28:f0/f1/f2/f3:offset 6h:bit 3). if slctl.pde (d28:f0/f1/f2/f3:offset 58h: bit 3) and slctl.hpe (d28:f0/f1/f2/f3:offset 58h: bit 5) are both set, the root port will also generate an interrupt. figure 5-1. generation of serr# to platform psts.sse serr# pcicmd.see secondary parity error primary parity error secondary serr# correctable serr# fatal serr# non-fatal serr# pci pci express
104 intel ? i/o controller hub 6 (i ch6) family datasheet functional description when a module is removed (via th e physical layer detection), the root port clears slsts.pds and sets slsts.pdc. if slctl.pde and slctl.hpe are both set, the root port will also generate an interrupt. 5.2.4.2 message generation when system software writes to slctl.aic (d28:f0/f1/f2/f3:offset 58h:bits 7:6) or slctl.pic (d28:f0/f1/f2/f3:offset 58h:bits 9:8), the root port will send a message down the link to change the state of leds on the module. writes to these fields are non-pos table cycles, and the resulting messa ge is a postable cycle. when receiving one of these writes, the root port performs the following: ? changes the state in the register ? generates a completion into the upstream queue ? formulates a message for the downstream port if th e field is written to regardless of if the field changed ? generates the message on the downstream port ? when the last message of a command is transmitted, sets slsts.cce (d28:f0/f1/f2/ f3:offset 58h:bit 4) to indicate the command has completed. if slctl.cce and slctl.hpe (d28:f0/f1/f2/f3:offset 58h:bit 5) are set, the root port generates an interrupt. the command completed register (slsts.cc) app lies only to commands issued by software to control the attention indicator (slctl.aic), powe r indicator (slctl.pic), or power controller (slctl.pcc). however, writes to other parts of th e slot control register would invariably end up writing to the indicators and power controller fields . hence, any write to th e slot control register is considered a command and if enabled, will result in a command complete interrupt. the only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. a single write to the slot control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the slot control register. 5.2.4.3 attention button detection when an attached device is ejected , an attention button could be pressed by the user. this attention button press will result in a the pci express me ssage ?attention_button_pressed? from the device. upon receiving this message, the root port wi ll set slsts.abp (d28: f0/f1/f2/f3:offset 5ah:bit 0). if slctl.abe (d28:f0/f1/f2/f3:offset 58h:bit 0) and slctl.hpe (d28:f0/f1/f2/f3:offset 58h:bit 5) are set, the hot-plug c ontroller will also generate an in terrupt. the interrupt is generated on an edge-event. for example, if slsts.abp is already set, a new interrupt will not be generated.
intel ? i/o controller hub 6 (ich6) family datasheet 105 functional description 5.2.4.4 smi/sci generation interrupts for hot-plug events are not supported on legacy operating systems. to support hot-plug on non-pci express aware operating systems, hot-plug events can be routed to generate sci. to generate sci, mpc.hpce (d28:f0/f1/f2/f3:offset d8h:bit 30) must be set. when set, enabled hot-plug events will cause smscs.hpcs (d28:f 0/f1/f2/f3:offset dch:bit 30) to be set. additionally, bios workarounds for hot-plug can be supported by setting mpc.hpme (d28:f0/ f1/f2/f3:offset d8h:bit 1). when this bit is set, hot-plug events can cause smi status bits in smscs to be set. supported hot-plug ev ents and their corresponding smscs bit are: ? command completed ? smscs.hpccm (d28:f0/f1/f2/f3:offset dch:bit 3) ? presence detect changed ? smscs.hppd m (d28:f0/f1/f2/f3:offset dch:bit 1) ? attention button pressed ? smscs.hpab m (d28:f0/f1/f2/f3:offset dch:bit 2) when any of these bits are set, smi # will be gene rated. these bits are set regardless of whether interrupts or sci is enabled for hot-plug events. the smi# may occur concurrently with an interrupt or sci. 5.3 lan controller (b1:d8:f0) the ich6?s integrated lan cont roller includes a 32-bit pci controller that provides enhanced scatter-gather bus mastering capabilities and enab les the lan controller to perform high-speed data transfers over the pci bus. its bus master cap abilities enable the comp onent to process high level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. two larg e transmit and receive fifos of 3 kb each, help prevent data underruns and overruns while waiting for bus accesses. this enables the integrated lan controller to transmit data with minimum interframe spacing (ifs). the ich6 integrated lan c ontroller can operate in either full-duplex or half-duplex mode. in full- duplex mode the lan controller adheres with the ieee 802.3x flow control specification . half duplex performance is enhanced by a proprietary collision reduction mechanism. the integrated lan controller al so includes an interface to a serial (4-pin) eeprom. the eeprom provides power-on initialization for hard ware and software configuration parameters. from a software perspective, the integrated lan controller appears to reside on the secondary side of the ich6?s virtual pci-to-pci bridge (see section 5.1.6 ). this is typically bus 1, but may be assigned a different number, depending upon system configuration. the following summar izes the ich6 lan controller features: ? compliance with advanced configuration an d power interface and pci power management standards ? support for wake-up on interesting packets and link status change ? support for remote power-up using wake on lan* (wol) technology ? deep power-down mode support ? support of wired for management (wfm) revision 2.0 ? backward compatible software with 82550, 82557, 82558 and 82559 ? tcp/udp checksum off load capabilities ? support for intel?s adaptive technology
106 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.3.1 lan controller pci bus interface as a fast ethernet controller, the role of th e ich6 integrated lan controller is to access transmitted data or deposit recei ved data. the lan controller, as a bus master device, initiates memory cycles via the pci bus to fe tch or deposit the required data. to perform these actions, the lan controller is controlled and ex amined by the processor via its control and status structures and re gisters. some of these control and status structures reside in the lan controller and some reside in system memo ry. for access to the lan controller?s control/ status registers (csr), the lan controller acts as a slave (in other words, a target device). the lan controller serves as a slave also while the processor accesses the eeprom. 5.3.1.1 bus slave operation the ich6 integrated lan controller serves as a target device in one of the following cases: ? processor accesses to the lan controller system control block (scb) control/status registers (csr) ? processor accesses to the eeprom through its csr ? processor accesses to the lan cont roller port address via the csr ? processor accesses to the mdi control register in the csr the size of the csr memory space is 4 kb in th e memory space and 64 bytes in the i/o space. the lan controller treats accesses to th ese memory spaces differently. control/status register (csr) accesses the integrated lan controller supports zero wait-state single cycle memory or i/o mapped accesses to its csr space. separate bars request 4 kb of memory space and 64 bytes of i/o space to accomplish this. based on its need s, the software driver uses e ither memory or i/o mapping to access these registers. the lan controller provide s four valid kb of csr space that include the following elements: ? system control block (scb) registers ? port register ? eeprom control register ? mdi control register ? flow control registers in the case of accessing the control/status regist ers, the processor is the initiator and the lan controller is the target. retry premature accesses the lan controller responds with a retry to any configuration cycle accessing the lan controller before the completion of the automatic read of the eeprom. the lan controller may continue to retry any configuration accesses until the eeprom read is complete. the lan controller does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. any master access to the lan controller af ter the completion of the eeprom read is honored.
intel ? i/o controller hub 6 (ich6) family datasheet 107 functional description error handling data parity errors: the lan controller checks for data parity errors while it is the target of the transaction. if an error was detected, the lan co ntroller always sets the detected parity error bit in the pci configuration status register, bit 15. the lan controller also asserts perr#, if the parity error response bit is set (pci co nfiguration command register, bit 6). the lan controller does not attempt to terminate a cycle in which a parity error was detected. this gives the initiator the option of recovery. target-disconnect: the lan controller premat urely terminate a cycle in the following cases: ? after accesses to its csr ? after accesses to the configuration space system error: the lan controller reports parity error during the address phase using the serr# pin. if the serr# enable bit in the pci confi guration command register or the parity error response bit are not set, the lan controller onl y sets the detected parity error bit (pci configuration status register, bit 15). if serr# en able and parity error response bits are both set, the lan controller sets the signal ed system error bit (pci configuration status register, bit 14) as well as the detected parity error bit and asserts serr# for one clock. the lan controller, when detectin g system error, claims the cycl e if it was the target of the transaction and continues the transact ion as if the address was correct. note: the lan controller reports a system error for any er ror during an address phase, whether or not it is involved in the current transaction. 5.3.1.2 clkrun# signal (mobile only) the ich6 receives a free-running 33 mhz clock. it does not st op based on the clkrun# signal and protocol. when the lan controller runs cycl es on the pci bus, the ich6 makes sure that the stp_pci# signal is high indicating that the pci clock will be running. this is to make sure that any pci tracker does not get confused by transact ions on the pci bus with its pci clock stopped. 5.3.1.3 pci power management enhanced support for the power management standard, pci local bus specification, revision 2.3 , is provided in the ich6 integrated lan controlle r. the lan controller supports a large set of wake-up packets and the capability to wake the system from a low power state on a link status change. the lan controller enables the host system to be in a sleep state and remain virtually connected to the network. after a power management event or link status ch ange is detected, the lan controller wakes the host system. the sections below describe these events, the lan controll er power states, and estimated power consumpt ion at each power state. the lan controller contains power management registers for pci, and implements four power states, d0 through d3, which vary from maximum power consumption at d0 to the minimum power consumption at d3. pci transactions are only allowed in the d0 state, except for host accesses to the lan controller?s pci configuratio n registers. the d1 and d2 power management states enable intermediate power savings while pr oviding the system wake-up capabilities. in the d3 cold state, the lan controller can provide wake-up capabilities. wake-up indications from the lan controller are provided by the power management event (pme#) signal.
108 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.3.1.4 pci reset signal the pcirst# signal may be activated in one of the following cases: ? during s3?s5 states ? due to a cf9h reset if pme is enabled (in the pci power management registers), pcirst# assertion does not affect any pme related circuits (in other words, pci power management registers and the wake-up packet would not be affected). while pc irst# is active, the lan controller ignores other pci signals. the configuration of the lan controller registers asso ciated with acpi wake events is not affected by pcirst#. the integrated lan controller uses the pcirst# or the pwrok signal as an indication to ignore the pci interface. following the de-assertion of pcirst#, the la n controller pci configuration space, mac configuration, and memory structure ar e initialized while preserving the pme# signal and its context. 5.3.1.5 wake-up events there are two types of wake-up events: ?interestin g? packets and link st atus change. these two events are detailed below. note: if the wake on lan bit in the eeprom is not set, wake-up events are supported only if the pme enable bit in the power management control/status register (pmcsr) is set. however, if the wake on lan bit in the eeprom is set, and wake on magic packet* or wake on link status change are enabled, the power mana gement enable bit is ignored with respect to these events. in the latter case, pme# would be asserted by these events. ?interesting? packet event in the power-down state, the lan controller is cap able of recognizing ?int eresting? packets. the lan controller supports predefined and programmabl e packets that can be defined as any of the following: ? arp packets (with multiple ip addresses) ? direct packets (with or without type qualification) ? magic packet ? neighbor discovery multicast address p acket (?arp? in ipv6 environment) ? netbios over tcp/ip (nbt) qu ery packet (under ipv4) ? internetwork package exchan ge* (ipx) diagnostic packet this allows the lan controller to handle various packet types. in general, the lan controller supports programmable filtering of any packet in the first 128 bytes.
intel ? i/o controller hub 6 (ich6) family datasheet 109 functional description when the lan controller is in one of the low power states, it search es for a predefined pattern in the first 128 bytes of the inco ming packets. the only exception is the magic packet, which is scanned for the entire frame. the lan controller classifies the incoming packets as one of the following categories: ? no match: the lan controller discards the packet and continues to process the incoming packets. ? tco packet: the lan controller implements perfect filtering of tco packets. after a tco packet is processed, the lan controller is ready for the next incoming packet. tco packets are treated as any other wake-up packet and may a ssert the pme# signal if configured to do so. ? wake-up packet: the lan controller is capable of rec ognizing and storing the first 128 bytes of a wake-up packet. if a wake-up packet is larg er than 128 bytes, its tail is discarded by the lan controller. after the system is fully powered-up, software has the ability to determine the cause of the wake-up event via the pmdr and dump the stored data to the host memory. magic packets are an exceptio n. the magic packets may cause a power management event and set an indication bit in the pmdr; however, it is not stored by the lan controller for use by the system when it is woken up. link status change event the lan controller link status indication circuit is capable of issuing a pme on a link status change from a valid link to an invalid link cond ition or vice versa. the lan controller reports a pme link status event in all power states. if the wake on lan bit in the eeprom is not set, the pme# signal is gated by the pme enable bit in the pmcsr and the csma configure command. 5.3.1.6 wake on lan* (preboot wake-up) the lan controller enters wake on lan mode after reset if the wake on lan bit in the eeprom is set. at this point, the lan controller is in the d0u state. when the lan co ntroller is in wake on lan mode: ? the lan controller scans incoming packets for a magic packet and asserts the pme# signal for 52 ms when a 1 is detected in wake on lan mode. ? the activity led changes its functionality to indicates that the received frame passed individual address (ia) filtering or broadcast filtering. ? the pci configuration registers are accessible to the host. the lan controller switches from wake on lan mode to the d0a power state following a setup of the memory or i/o base address regi sters in the pci configuration space. 5.3.2 serial eeprom interface the serial eeprom stores confi guration data for the ich6 integrated lan controller and is a serial in/serial out device. the lan controller supports a 64-regis ter or 256-register size eeprom and automatically detects the eeprom?s size. th e eeprom should operate at a frequency of at least 1 mhz. all accesses, either read or write, are preceded by a command instruction to the device. the address field is six bits for a 64-register eeprom or eight bits for a 256-register eeprom. the end of the address field is indicated by a dummy 0 bit from the eeprom, which indicates the entire address field has been tran sferred to the device. an eeprom read instruction waveform is shown in figure 5-2 .
110 intel ? i/o controller hub 6 (i ch6) family datasheet functional description the lan controller performs an automatic read of seven words (0h, 1h, 2h, ah, bh, ch, and dh) of the eeprom after the de-assertion of reset. 5.3.3 csma/cd unit the ich6 integrated lan controller csma/cd unit implements both the ieee 802.3 ethernet 10 mbps and ieee 802.3u fast ethernet 100 mbps standards. it performs all the csma/cd protocol functions (e.g., transm ission, reception, collision handli ng, etc.). the lan controller csma/cd unit interfaces to the 82562et/em/ez/ex 10/100 mbps ethernet through the ich6?s lan connect interface signals. 5.3.3.1 full duplex when operating in full-duplex mode, the lan controller can transmit and receive frames simultaneously. transmission starts regardless of the state of the internal receive path. reception starts when the platform lan connect component detects a vali d frame on its recei ve differential pair. the ich6 integrated lan controller also supports the ieee 802.3x flow control standard, when in full-duplex mode. the lan controller operat es in either half-duplex mode or full-duplex mode. for proper operation, both the lan controller csma/cd module and the discrete platform lan connect component must be set to the same duplex mode. the csma duplex mode is set by the lan controller configure command or forced by automatically tracking the mode in the platform lan connect component. following reset, the csma defaults to automatically track th e platform lan connect component duplex mode. the selection of duplex operation (full or half) and flow control is done in two levels: mac and lan connect. figure 5-2. 64-word eeprom read instruction waveform a 1 a 0 ee_cs ee_shclkk ee_din ee_dout a 5 a 4 a 2 d 15 d 0 read op code a 3 a 1 a 0
intel ? i/o controller hub 6 (ich6) family datasheet 111 functional description 5.3.3.2 flow control the lan controller supports ieee 802.3x frame-base d flow control frames only in both full duplex and half duplex switched environments. th e lan controller flow control feature is not intended to be used in shared media environments. flow control is optional in full-duplex mode and is selected through software configuration. there are three modes of flow control that can be selected: frame-based transmit flow control, frame- based receive flow control, and none. 5.3.3.3 vlan support the lan controller supports th e ieee 802.1 standard vlan. all vlan flows will be implemented by software. the lan controller supports the recepti on of long frames, specifically frames longer than 1518 bytes, incl uding the crc, if software sets the long receive ok bit in the configuration command. otherwise, ?long? frames are discarded. 5.3.4 media management interface the management interface allows the processor to control the platform lan connect component via a control register in the ich6 integrated lan controller. this allows the software driver to place the platform lan connect in specific modes (e.g., full dupl ex, loopback, power down, etc.) without the need for specific hardware pins to se lect the desired mode. this structure allows the lan controller to query the platform lan connect component for status of the link. this register is the mdi control register and resides at of fset 10h in the lan controller csr. the mdi registers reside within the plat form lan connect component, and are described in detail in the platform lan connect component?s datasheet. the pr ocessor writes commands to this register and the lan controller reads or writes the control/ status parameters to the platform lan connect component through the mdi register. 5.3.5 tco functionality the ich6 integrated lan controller supports management communication to reduce total cost of ownership (tco). the smbus is used as an interface between the asf controller and the integrated tco host controller. there are two different types of tco operation that are supported (only one supported at a time), they are 1) integr ated asf control or 2) external tco controller support. the smlink is a dedicated bus between the lan controller and the integrated asf controller (if enabled) or an external management controller. an eeprom of 256 words is required to support the heartbeat command. 5.3.5.1 advanced tco mode the advanced tco functionalities through the smlink are listed in table 5-3 .
112 intel ? i/o controller hub 6 (i ch6) family datasheet functional description note: for a complete description on various commands, see the total cost of ownership (tco) system management bus interface application note (ap-430) . transmit command during normal operation to serve a transmit request from the tco controller, the ich6 lan controller first completes the current transmit dma, sets the tco request bit in the pmdr register (see section 8.2 ), and then responds to the tco controller?s transmit request. following the completion of the tco transmit dma, the lan controller increments the tran smit tco statistic counter (described in section 8.2.14 ). following the completion of the transm it operation, the ic h6 increments the nominal transmit statistic counter s, clears the tco request bit in the pmdr register, and resumes its normal transmit flow. the r eceive flow is not affected durin g this entire period of time. receive tco the ich6 lan controller supports receive fl ow towards the tco controller. the ich6 can transfer only tco packets, or all packets that passed mac ad dress filtering according to its configuration and mode of operation as detailed be low. while configured to transfer only tco packets, it supports ethernet type ii packets with optional vlan tagging. force tco mode: while the ich6 is in the force tco mo de, it may receive pack ets (tco or all) directly from the tco controller. receiving tco packets and filtering level is controlled by the set receive enable command from th e tco controller. fo llowing a reception of a tco packet, the ich6 increments its nominal r eceive statistic counters as well as the receive tco counter. dx>0 power state: while the ich6 is in a powerdown stat e, it may receive tco packets or all directly to the tco controller. receiving tco p ackets is enabled by the set receive enable command from the tco controller. although tco packet might match one of the other wake up filters, once it is transf erred to the tco controller, no further matching is searched for and pme is not issued. while receive to tco is not enabled, a tco packet ma y cause a pme if configured to do so (setting tco to 1 in the filter type). d0 power state: at d0 power state, the ich6 may transf er tco packets to the tco controller. at this state, tco packets are posted first to the host memory, then read by the ich6, and then posted back to the tco controller. after the packet is posted to tco, the receive memory structure (that is occupied by the tco packet) is reclaimed. other than providing the necessary receive resources, there is no required device driver intervention with this process. eventually, the ich6 increments the receive tco static counter, clears the tc o request bit, and resumes normal control. table 5-3. advanced tco functionality power state tco controller functionality d0 nominal transmit set receive tco packets receive tco packets read ich6 status (pm & link state) force tco mode dx (x>0) d0 functionality plus: read phy registers force tco mode dx functionality plus: configuration commands read/write phy registers
intel ? i/o controller hub 6 (ich6) family datasheet 113 functional description read ich6 status (pm and link state) the tco controller is capable of reading the ich6 power state and link status. following a status change, the ich6 asserts linkalert# and th en the tco can read its new power state. set force tco mode the tco controller put the ich6 into the force tc o mode. the ich6 is se t back to the nominal operation following a pcirst#. following the transition from nominal mode to a tco mode, the ich6 aborts transmission and r eception and loses its memory stru ctures. the tco may configure the ich6 before it starts tran smission and reception if required. warning: the force tco is a destructive command. it cause s the ich6 to lose its memory structures, and during the force tco mode the ich6 ignores any pci accesses. therefore, it is highly recommended to use this command by the tc o controller at system emergency only. 5.4 alert standard format (asf) the asf controller collects info rmation from various components in the system (including the processor, chipset, bios, and sensors on the moth erboard) and sends this information via the lan controller to a remote server running a mana gement console. the c ontroller also accepts commands back from the management console a nd drives the execution of those commands on the local system. the asf controller is responsible for monitoring sensor devices and sending packets through the lan controller smbus (system management bus) interface. these asf controller alerting capabilities include system health information (such as bios messages, post alerts, operating system failure notifications , and heartbeat signals) to indicate th e system is accessible to the server. also included are environmental notification (e.g ., thermal, voltage and fan alerts) that send proactive warnings that something is wrong with the hardware. the packets are used as alert (s.o.s.) packets or as ?heartbeat? status packet s. in addition, asset security is provided by messages (e.g., ?cover tamper? and ?processor missi ng?) that notify of pot ential system break-ins and processor or memory theft. the asf controller is also responsible for receiving and responding to rmcp (remote management and control protocol) packets. rmcp packets are used to perform various system apm commands (e.g., reset, power-up, power-cycle , and power-down). rmcp can also be used to ping the system to ensure that it is on the network and runn ing correctly and for capability reporting. a major advantage of asf is that it pr ovides these services during the time that software is unable to do so (e.g., during a low-power st ate, during boot-up, or during an operating system hang) but are not precluded from running in the working state. the asf controller communicates to the system and the lan cont roller logic through the smbus connections. the first smbus connects to the hos t smbus controller (within the ich6) and any smbus platform sensors. the smbus host is accessi ble by the system software, including software running on the operating system and the bios. note that the host side bus may require isolation if there are non-auxiliary devices that can pull down the bus when un-powered. the second smbus connects to the lan controller. th is second smbus is used to pr ovide a transmit/receive network interface. the stimulus for causing the asf controller to send pa ckets can be either internal or external to the asf controller. external stimuli are link status changes or polling data from smbus sensor devices; internal events come from , among others, a set of timers or an event caused by software.
114 intel ? i/o controller hub 6 (i ch6) family datasheet functional description the asf controller provides three local configuration protocols via the host smbus. the first one is the smbus arp interface that is used to id entify the smbus device and allow dynamic smbus address assignment. the second pr otocol is the asf controller command set that allows software to manage an asf controller compliant interface for retrieving info, sending alerts, and controlling timers. ich6 provides an input and an output eepr om interface. the eeprom contains the lan controller configuration and the asf contro ller configuration/packet information. 5.4.1 asf management solu tion features/capabilities ? alerting ? transmit sos packets from s0?s5 states ? system health heartbeats ? sos hardware events - system boot failure (watchdog expires on boot) - lan link loss - entity presence (on asf power-up) - smbus hung - maximum of eight legacy sensors - maximum of 128 asf sensor events ? watchdog timer for operating system lockup/system hang/failure to boot ? general push support for bios (post messages) ? remote control ? presence ping response ? configurable boot options ? capabilities reporting ? auto-arp support ? system remote control - power-down - power-up - power cycle - system reset ? state-based security ? conditional action on watchdog expire ? asf compliance ? compliant with the alert standard format (asf) specification, version 1.03 - pet compliant packets - rmcp - legacy sensor polling - asf sensor polling - remote control sensor support ? advanced features / miscellaneous ? smbus 2.0 compliant ? optional reset extension logic (for use with a power-on reset)
intel ? i/o controller hub 6 (ich6) family datasheet 115 functional description 5.4.2 asf hardware support asf requires additional hardware to make a complete solution. note: if an asf compatible device is externally connect ed and properly configur ed, the internal ich6 asf controller will be disabled . the external asf device will have access to the smbus controller. 5.4.2.1 82562em/ex the 82562em/ex et hernet lan controller is necessary. th is lan controller provides the means of transmitting and receiving data on the network, as well as addi ng the ethernet crc to the data from the asf. 5.4.2.2 eeprom (256x16, 1 mhz) to support the ich6 asf solution, a larger, 256x16 1 mhz, eeprom is necessary to configure defaults on reset and on hard powe r losses (software un-initiated). the asf controller shares this eeprom with the lan controller and provides a pass through interface to achieve this. the asf controller expects to have exclusive access to words 40h through f7h. the lan controller can use the other eeprom words. the asf controller will default to safe defaults if the eeprom is not present or not confi gured properly (both cause an invalid crc). 5.4.2.3 legacy sensor smbus devices the asf controller is capable of monitoring up to eight sensor devices on the main smbus. these sensors are expected to be comp liant with the legacy sensor characteristics defined in the alert standard format (asf) specification, version 1.03. 5.4.2.4 remote control smbus devices the asf controller is capable of causing remote control actions to remote control devices via smbus. these remote control act ions include power-up, power-do wn, power-cycle, and reset. the asf controller supports devices that conform to the alert standard format (asf) specification, version 1.03. , remote control devices. 5.4.2.5 asf sensor smbus devices the asf controller is capable of monitoring up to 128 asf sensor devices on the main smbus. however, asf is restricted by the number of total events which may reduce the number of smbus devices supported. the maximum number of events supported by asf is 128. the asf sensors are expected to operate as defined in the alert standard format (asf) specification, version 1.03 . 5.4.3 asf software support asf requires software support to make a complete solution. the following software is used as part of the complete solution. ? asf configuration driver / application ? network driver ? bios support for smbios, smbus arp, acpi ? sensor configuration driver / application note: contact your intel field representative for the client asf software development kit (sdk) that includes additional documentation and a copy of the client asf software drivers. intel also provides an asf console sdk to add asf support to a management console.
116 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.5 lpc bridge (w/ system and management functions) (d31:f0) the lpc bridge function of the ich6 resides in pci device 31:function 0. in addition to the lpc bridge function, d31:f0 contains other functiona l units including dma, interrupt controllers, timers, power management, system management, gp io, and rtc. in this chapter, registers and functions associated with other functional units (power management, gpio, usb, ide, etc.) are described in their respective sections. 5.5.1 lpc interface the ich6 implements an lpc in terface as described in the low pin count interface specification, revision 1.1 . the lpc interface to the ich6 is shown in figure 5-3 . note that the ich6 implements all of the signals that are shown as optional, but peripherals are not required to do so. figure 5-3. lpc interface diagram lad[3:0] intel ? ich6 lpc device ldrq# (optional) lframe# pci clk pci rst# pci serirq pci pme# pci bus sus_stat# gpi lsmi# (optional) lpcpd# (optional)
intel ? i/o controller hub 6 (ich6) family datasheet 117 functional description 5.5.1.1 lpc cycle types the ich6 implements all of th e cycle types described in the low pin count interface specification, revision 1.0 . table 5-4 shows the cycle types supported by the ich6. notes: 1. for memory cycles below 16 mb that do not ta rget enabled firmware hub ranges, the ich6 performs standard lpc memory cycles. it only attempts 8-bit tr ansfers. if the cycle appears on pci as a 16-bit transfer, it appears as two consecutive 8-bit transfers on lpc. likewise, if the cycle appears as a 32-bit transfer on pci, it appears as four consecutive 8- bit transfers on lpc. if the cycle is not claimed by any peripheral, it is subsequently aborted, and the ich6 returns a value of all 1s to the processor. this is done to maintain compatibility with isa memory cycles where pull-up re sistors would keep the bus high if no device responds. 2. bus master read or write cycles must be naturally al igned. for example, a 1-byte transfer can be to any address. however, the 2-byte transfer must be word -aligned (i.e., with an address where a0=0). a dword transfer must be dword-aligned (i.e., with an address where a1 and a0 are both 0). 5.5.1.2 start field definition note: all other encodings are reserved. table 5-4. lpc cycle types supported cycle type comment memory read single: 1 byte only memory write single: 1 byte only i/o read 1 byte only. intel ? ich6 breaks up 16- and 32-bit proces sor cycles into multiple 8-bit transfers. see note 1 below. i/o write 1 byte only. ich6 breaks up 16- and 32-bi t processor cycles into multiple 8-bit transfers. see note 1 below. dma read can be 1, or 2 bytes dma write can be 1, or 2 bytes bus master read can be 1, 2, or 4 bytes. (see note 2 below) bus master write can be 1, 2, or 4 bytes. (see note 2 below) table 5-5. start fi eld bit definitions bits[3:0] encoding definition 0000 start of cycle for a generic target 0010 grant for bus master 0 0011 grant for bus master 1 1111 stop/abort: end of a cycle for a target.
118 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.5.1.3 cycle type / di rection (cyctype + dir) the ich6 always drives bit 0 of this field to 0. peripherals running bus ma ster cycles must also drive bit 0 to 0. table 5-6 shows the valid bit encodings. 5.5.1.4 size bits[3:2] are reserved. the ich6 always drives th em to 00. peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the ich6 ignores those bits. bits[1:0] are encoded as listed in table 5-7 . table 5-6. cycle type bit definitions bits[3:2] bit1 definition 00 0 i/o read 00 1 i/o write 01 0 memory read 01 1 memory write 10 0 dma read 10 1 dma write 11 x reserved. if a peripheral performing a bus master cycle generates this value, the intel ? ich6 aborts the cycle. table 5-7. transfer size bit definition bits[1:0] size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 reserved. the intel ? ich6 never drives this combinat ion. if a peripheral running a bus master cycle drives this combinatio n, the ich6 may abort the transfer. 11 32-bit transfer (4 bytes)
intel ? i/o controller hub 6 (ich6) family datasheet 119 functional description 5.5.1.5 sync valid values for the sync field are shown in table 5-8 . notes: 1. all other combinations are reserved. 2. if the lpc controller receives any sync returned from t he device other than short (0101), long wait (0110), or ready (0000) when running a fwh cycle, indeterminate results may occur. a fwh device is not allowed to assert an error sync. 5.5.1.6 sync time-out there are several error cas es that can occur on the lpc interface. the ich6 responds as defined in section 4.2.1.9 of the low pin count interface specifica tion, revision 1.1 to the stimuli described therein. there may be other peripheral failure co nditions; however, these are not handled by the ich6. 5.5.1.7 sync error indication the ich6 responds as defined in section 4.2.1.10 of the low pin count interface specification, revision 1.1 . upon recognizing the sync field indicating an error, the ich6 treats this as an serr by reporting this into the device 31 error reporting logic. 5.5.1.8 lframe# usage the ich6 follows the usage of lframe# as defined in the low pin count interface specification, revision 1.1 . the ich6 performs an abort for the fo llowing cases (possi ble failure cases): ? ich6 starts a memory, i/o, or dma cycle, but no device drives a valid sync after four consecutive clocks. ? ich6 starts a memory, i/o, or dma cycle, and the peripheral drives an invalid sync pattern. ? a peripheral drives an illegal addre ss when performing bus master cycles. ? a peripheral drives an invalid value. table 5-8. sync bit definition bits[3:0] 1,2 indication 0000 ready: sync achieved with no error. for dma tr ansfers, this also indicates dma request de-assertion and no more transf ers desired for that channel. 0101 short wait: part indicating wait-states. fo r bus master cycles, the intel ? ich6 does not use this encoding. instead, the ich6 uses t he long wait encoding (see next encoding below). 0110 long wait: part indicating wait-states, and many wait-states will be added. this encoding driven by the ich6 for bus master cycles, rather than the short wait (0101). 1001 ready more (used only by peripheral for dma cycle): sync achieved with no error and more dma transfers desired to continue after th is transfer. this value is valid only on dma transfers and is not allowed for any other type of cycle. 1010 error: sync achieved with error. this is genera lly used to replace the serr# or iochk# signal on the pci/isa bus. it indica tes that the data is to be trans ferred, but there is a serious error in this transfer. for dma transfers, this not only indicates an erro r, but also indicates dma request de-assertion and no more transfers desired for that channel.
120 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.5.1.9 i/o cycles for i/o cycles targeting registers specified in th e ich6?s decode ranges, the ich6 performs i/o cycles as defined in the low pin count interface specification, revision 1.1 . these are 8-bit transfers. if the processor attempts a 16-bit or 32-bit transfer, the ich6 breaks the cycle up into multiple 8-bit transfers to consecutive i/o addresses. note: if the cycle is not claimed by any peripheral (and subsequently aborted), the ich6 returns a value of all 1s (ffh) to the processor. this is to main tain compatibility with isa i/o cycles where pull-up resistors would keep the bus high if no device responds. 5.5.1.10 bus master cycles the ich6 supports bus master cycles and re quests (using ldrq#) as defined in the low pin count interface specification, revision 1.1 . the ich6 has two ldrq# inputs, and thus supports two separate bus master devices. it uses the asso ciated start fields for bus master 0 (0010b) or bus master 1 (0011b). note: the ich6 does not support lpc bus masters perf orming i/o cycles. lpc bus masters should only perform memory read or memory write cycles. 5.5.1.11 lpc power management clkrun# protocol (mobile only) the clkrun# protocol is same as the pci specification. stopping the pci clock stops the lpc clock. lpcpd# protocol same timings as for sus_stat#. upon driving sus_stat# low, lpc peripherals drive ldrq# low or tri-state it. ich6 shuts off the ldrq# input buffers. after driving sus_stat# active, the ich6 drives lframe# low, and tri- states (or drive low) lad[3:0]. note: the low pin count interface specification, revision 1.1 defines the lpcpd# protocol where there is at least 30 s from lpcpd# assertion to lrst # assertion. this specifi cation explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. the ich6 assert s both sus_stat# (connects to lpcpd#) and pltrst# (connects to lrst#) at the same time when the core logic is reset (via cf9h, pwrok, or sys_reset#, etc.). this is not inco nsistent with the lpc lpcpd# protocol. 5.5.1.12 configuration and intel ? ich6 implications lpc i/f decoders to allow the i/o cycles and memory mapped cycles to go to the lpc inte rface, the ich6 includes several decoders. during configuration, the ic h6 must be programmed with the same decode ranges as the peripheral. the decoders are program med via the device 31:function 0 configuration space. note: the ich6 cannot accept pci write cycles from pc i-to-pci bridges or devices with similar characteristics (specifically those with a ?retry r ead? feature which is enab led) to an lpc device if there is an outstanding lpc read cycle towards the same pci device or bridge. these cycles are not part of normal system operation, but may be en countered as part of platform validation testing using custom test fixtures.
intel ? i/o controller hub 6 (ich6) family datasheet 121 functional description bus master device mapping and start fields bus masters must have a unique start field. in the case of the ich6 that supports two lpc bus masters, it drives 0010 for the start field for grants to bus master #0 (requested via ldrq0#) and 0011 for grants to bus master #1 (requested via ldrq1#.). thus, no re gisters are needed to configure the start fields for a particular bus master. 5.6 dma operation (d31:f0) the ich6 supports lpc dma using the ich6?s dma controller. the dma controller has registers that are fixed in the lower 64 kb of i/o space. the dma controlle r is configured using registers in the pci configuration space. these regi sters allow configuration of the channels for use by lpc dma. the dma circuitry incor porates the functionality of two 82c37 dma controllers with seven independently programmable channels ( figure 5-4 ). dma controller 1 (dma-1) corresponds to dma channels 0?3 and dma controller 2 (dma-2) corresponds to channels 5?7. dma channel 4 is used to cascade the two controllers and defa ults to cascade mode in the dma channel mode (dcm) register. channel 4 is not available for an y other purpose. in addition to accepting requests from dma slaves, the dma controller also responds to requests that software initiates. software may initiate a dma service request by setting any bi t in the dma channel request register to a 1. each dma channel is hardwired to the compatible settings for dma device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfer s, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ich6 provides 24-bit addressing in compliance with the isa-compatible specification. each channel includes a 16-bit isa-comp atible current register which holds the 16 least-significant bits of the 24-bit address, an is a-compatible page register which contains the eight next most significant bits of address. the dma controller also features refresh address generation, and autoinitialization following a dma termination. figure 5-4. intel ? ich6 dma controller channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 dma-1 dma-2
122 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.6.1 channel priority for priority resolution, the dma consists of two logical channel groups: channels 0?3 and channels 4?7. each group may be in either fixed or rotate mode, as determined by the dma command register. dma i/o slaves normally assert their dreq li ne to arbitrate for dma service. however, a software request for dma service can be presen ted through each channel's dma request register. a software request is subject to the same prior itization as any hardware request. see the detailed register description for request register programming information in section 10.2 . 5.6.1.1 fixed priority the initial fixed priority structure is as follows: the fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. in this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. channels [3:0] of dma-1 assume the priority position of channel 4 in dma-2, thus taking priority over channels 5, 6, and 7. 5.6.1.2 rotating priority rotation allows for "fairness" in priority resolutio n. the priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0?3, 5?7). channels 0?3 rotate as a group of 4. they are always placed between channel 5 and channel 7 in the priority list. channel 5?7 rotate as part of a group of 4. that is, channels (5?7) form the first three positions in the rotation, while channel gr oup (0?3) comprises the fourth position in the arbitration. 5.6.2 address compatibility mode when the dma is operating, the addresses do not increment or decremen t through the high and low page registers. theref ore, if a 24-bit address is 01ffffh and increments, the next address is 010000h, not 020000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 02ffffh, not 01ffffh. however, when the dma is operating in 16-bit mode, the addresses still do not increment or decrement through the high and low page registers but the page boundary is now 128 k. therefore, if a 24-bit address is 01f ffeh and increments, the next address is 000000h, not 0100000h. similarly, if a 24-bit address is 020000h and decrements, the next address is 03fffeh, not 02fffeh. this is compatible with the 82c37 and page register implementation used in the pc-at. this mode is set after cpurst is valid. high priority low priority 0, 1, 2, 3 5, 6, 7
intel ? i/o controller hub 6 (ich6) family datasheet 123 functional description 5.6.3 summary of dma transfer sizes table 5-9 lists each of the dma device transfer sizes . the column labeled ?current byte/word count register? indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. the column labeled ?cur rent address increment/ decrement? indicates the number added to or taken from the curr ent address register after each dma transfer cycle. the dma cha nnel mode register determines if the current address register will be incremented or decremented. 5.6.3.1 address shifting when programmed for 16-bit i/o count by words the ich6 maintains compatibility with the implementation of the dma in the pc at that used the 82c37. the dma shifts the addr esses for transfers to/from a 16-bit device count-by-words. note: the least significant bit of the low page register is dropped in 16-bit shifted mode. when programming the current address register (when th e dma channel is in this mode), the current address must be programmed to an even address with the address value shifted right by one bit. the address shifting is shown in table 5-10 . note: the least significant bit of the page register is dropped in 16-bit shifted mode. 5.6.4 autoinitialize by programming a bit in the dma channel mode register, a channel may be set up as an autoinitialize channel. when a channel undergoes autoinitiali zation, the original values of the current page, current address and current byte/w ord count registers are automatically restored from the base page, address, and byte/word count registers of that channel following tc. the base registers are loaded simult aneously with the current regist ers by the microprocessor when the dma channel is programmed and remain unchanged throughout the dma service. the mask bit is not set when the channel is in autoinitialize. following autoinitialize, the channel is ready to perform another dma service, without processo r intervention, as soon as a valid dreq is detected. table 5-9. dma transfer size dma device date size and word count current byte/word count register current address increment/decrement 8-bit i/o, count by bytes bytes 1 16-bit i/o, count by words (address shifted) words 1 table 5-10. address shifting in 16-bit i/o dma transfers output address 8-bit i/o programmed address (ch 0?3) 16-bit i/o programmed address (ch 5?7) (shifted) a0 a[16:1] a[23:17] a0 a[16:1] a[23:17] 0 a[15:0] a[23:17]
124 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.6.5 software commands there are three additional special software commands that the dma controller can execute. the three software commands are: ? clear byte pointer flip-flop ? master clear ? clear mask register they do not depend on any specific bit pattern on the data bus. 5.7 lpc dma dma on lpc is handled through the use of th e ldrq# lines from pe ripherals and special encodings on lad[3:0] from the host. single, de mand, verify, and increment modes are supported on the lpc interface. channels 0?3 are 8 bit channels. channels 5?7 are 16-bit channels. channel 4 is reserved as a generic bus master request. 5.7.1 asserting dma requests peripherals that need dma service encode thei r requested channel number on the ldrq# signal. to simplify the protocol , each peripheral on the lpc i/f has its own dedicated ldrq# signal (they may not be shared between two separate peripher als). the ich6 has two ldrq# inputs, allowing at least two devices to support dma or bus mastering. ldrq# is synchronous with lclk (pci clock). as shown in figure 5-5 , the peripheral uses the following serial encoding sequence: ? peripheral starts the sequence by asserting ldrq# low (start bit). ldrq# is high during idle conditions. ? the next three bits contain the enc oded dma channel number (msb first). ? the next bit (act) indicates wh ether the request for the indicated dma channel is active or inactive. the act bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. the case where act is low is rare, and is only used to in dicate that a previous re quest for that channel is being abandoned. ? after the active/inactive indicatio n, the ldrq# signal must go high for at least 1 clock. after that one clock, ldrq# signal can be brought low to the next encoding sequence. if another dma channel also needs to request a tr ansfer, another sequence can be sent on ldrq#. for example, if an encoded request is sent for cha nnel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. this allows multiple dma agents be hind an i/o device to request use of the lpc interface, and the i/o device does not need to self-arbitrate before sending the message. figure 5-5. dma request assertion through ldrq# start msb lsb act start lclk ldrq#
intel ? i/o controller hub 6 (ich6) family datasheet 125 functional description 5.7.2 abandoning dma requests dma requests can be de-asserted in two fashions: on error conditions by sending an ldrq# message with the ?act? bit set to 0, or normally through a sync field during the dma transfer. this section describes boundary conditions where th e dma request needs to be removed prior to a data transfer. there may be some special cases where the peri pheral desires to abandon a dma transfer. the most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its fifo, or software stopping a device prematurely. in these cases, the peripheral wishes to stop further dma activity. it may do so by sending an ldrq# message with the act bit as 0. however, since the dma request was seen by the ich6, there is no guarantee that the cy cle has not been granted and will shortly run on lpc. therefore, peripherals must take into account that a dma cycl e may still occur. the peripheral can choose not to respond to this cycle, in which case the host wi ll abort it, or it can choos e to complete the cycle normally with any random data. this method of dma de-assertion should be pr evented whenever possible, to limit boundary conditions both on the ich6 and the peripheral. 5.7.3 general flow of dma transfers arbitration for dma channels is performed through the 8237 within the host. once the host has won arbitration on behalf of a dma channel assi gned to lpc, it asserts lframe# on the lpc i/f and begins the dma transfer. the general flow for a basic dma transfer is as follows: 1. ich6 starts transfer by asserting 00 00b on lad[3:0] with lframe# asserted. 2. ich6 asserts ?cycle type? of dma, di rection based on dma transfer direction. 3. ich6 asserts channel number and, if applicable, terminal count. 4. ich6 indicates the size of the transfer: 8 or 16 bits. 5. if a dma read? ? the ich6 drives the first 8 bits of data and turns the bus around. ? the peripheral acknowledges the data with a valid sync. ? if a 16-bit transfer, the process is repeated for the next 8 bits. 6. if a dma write? ? the ich6 turns the bus around and waits for data. ? the peripheral indicates data ready th rough sync and transfers the first byte. ? if a 16-bit transfer, the peripheral indicat es data ready and transfers the next byte. 7. the peripheral tu rns around the bus.
126 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.7.4 terminal count terminal count is communicated through lad[3] on the same clock that dma channel is communicated on lad[2:0]. this field is the cha nnel field. terminal count indicates the last byte of transfer, based upon the size of the transfer. for example, on an 8-bit tran sfer size (size field is 00b), if the tc bit is set, then this is the last byte. on a 16-bit transfer (size field is 01b), if th e tc bit is set, then the second byte is the last byte. the peripheral, therefore, must internalize the tc bit when the channel field is communicated, and only signal tc when the last byte of that tr ansfer size has been transferred. 5.7.5 verify mode verify mode is supported on the lpc interface. a verify transfer to the peripheral is similar to a dma write, where the peripheral is transferring data to main memory. the indication from the host is the same as a dma write, so the peripher al will be driving data onto the lpc interface. however, the host will not transfer this data into main memory. 5.7.6 dma request de-assertion an end of transfer is communicat ed to the ich6 through a special sync field transmitted by the peripheral. an lpc device must not attempt to signal the end of a transfer by de-asserting ldreq#. if a dma transfer is several bytes (e.g ., a transfer from a demand mode device) the ich6 needs to know when to de-assert the dma request based on the data currently being transferred. the dma agent uses a sync encodi ng on each byte of data being tr ansferred, which indicates to the ich6 whether this is the last byte of transfer or if more bytes are requested. to indicate the last byte of transfer, the peripheral uses a sync value of 0000b (ready with no error), or 1010b (ready with error). these encodings te ll the ich6 that this is the la st piece of data transferred on a dma read (ich6 to peripheral), or the byte that follows is the la st piece of data transferred on a dma write (peripheral to ich6). when the ich6 sees one of these two encodings, it ends the dma transfer after this byte and de- asserts the dma request to the 8237. therefore, if the ich6 indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a sync value of 0000b or 1010b. the ich6 does not attempt to transfer the second byte, and de-asserts the dma request internally. if the peripheral indicates a 0000b or 1010b sync pattern on the last byte of the indicated size, then the ich6 only de-asserts the dma request to the 8237 since it does not need to end the transfer. if the peripheral wishes to keep the dma reques t active, then it uses a sync value of 1001b (ready plus more data). this tells the 8237 that mo re data bytes are requested after the current byte has been transferred, so the ich6 keeps the dma re quest active to the 8237. therefore, on an 8-bit transfer size, if the peripheral indicates a sync value of 1001b to the ich6, the data will be transferred and the dma request will remain active to the 8237. at a later time, the ich6 will then come back with another start ? cyctype ? channel ? size etc. combination to initiate another transfer to the peripheral.
intel ? i/o controller hub 6 (ich6) family datasheet 127 functional description the peripheral must not assume that the next start indication from the ich6 is another grant to the peripheral if it had indicated a sync value of 1001b. on a single mode dma device, the 8237 will re-arbitrate after every transfer. only demand mode dma devices can be guaranteed that they will receive the next star t indication from the ich6. note: indicating a 0000b or 1010b encoding on the sync field of an odd byte of a 16-bit channel (first byte of a 16 bit transfer ) is an error condition. note: the host stops the transfer on th e lpc bus as indicated, fills the upper byte with random data on dma writes (peripheral to memory), and indicates to the 8237 that the dma transfer occurred, incrementing the 8237?s address and decrementing its byte count. 5.7.7 sync field / ldrq# rules since dma transfers on lpc are requested through an ldrq# assertion message, and are ended through a sync field during the dma transfer, the peripheral must obey the following rule when initiating back-to-back tran sfers from a dma channel. the peripheral must not assert another message for eight lclks after a de -assertion is indicated through the sync field. this is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message de-asserted before it is re-asserted so that it can arbitrate to the next agent. under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. the method by which this communication between host and peripheral through system bios is performed is beyond the scope of this specificatio n. since the lpc host and lpc peripheral are motherboard devices, no ?plug-n- play? registry is required. the peripheral must not assume that the host is able to perform tran sfer sizes that are larger than the size allowed for the dma channel, and be w illing to accept a size field that is smaller than what it may currently have buffered. to that end, it is recommended that future devices that may app ear on the lpc bus, that require higher bandwidth than 8-bit or 16- bit dma allow, do so with a bu s mastering interface and not rely on the 8237.
128 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.8 8254 timers (d31:f0) the ich6 contains three counters that have fixed uses. all registers and fu nctions associated with the 8254 timers are in the core well. the 8254 unit is clocked by a 14.31818 mhz clock. counter 0, system timer this counter functions as the system timer by controlling the state of irq0 and is typically programmed for mode 3 operation. the counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. the counter loads the initial count value 1 counter period after software writes the count value to the counter i/o address. the counter initially asserts irq0 and decrements the count value by two each counter period. the counter negates irq0 when the count value reaches 0. it then reloads the initial count value and again decrements the initial count value by two each counter period. the coun ter then asserts irq0 when the count value reaches 0, reloads the initia l count value, and repeat s the cycle, alternately asserting and negating irq0. counter 1, refresh request signal this counter provides the refresh request signal and is typically programmed for mode 2 operation and only impacts the period of the ref_toggle bit in port 61. the initial count value is loaded one counter period after being written to the counter i/o address. the ref_toggle bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. programming the counter to anything other than mode 2 will result in undefined behavior for the ref_toggle bit. counter 2, speaker tone this counter provides the speaker tone and is typically programmed for mode 3 operation. the counter provides a speaker frequency equal to the counter clock frequency (1.193 mhz) divided by the initial count value. the speaker must be enabled by a write to port 061h (see nmi status and control ports). 5.8.1 timer programming the counter/timers are programmed as follows: 1. write a control word to select a counter. 2. write an initial count for that counter. 3. load the least and/or most significant bytes (as required by control word bits 5, 4) of the 16-bit counter. 4. repeat with other counters. only two conventions need to be observed when programming the counters. first, for each counter, the control word must be written before the initial count is written. second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). a new initial count may be written to a counter at any time w ithout affecting the counter's programmed mode. counting is affected as descri bed in the mode definitions. the new count must follow the programmed count format.
intel ? i/o controller hub 6 (ich6) family datasheet 129 functional description if a counter is programmed to read/write two-by te counts, the following precaution applies: a program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. otherwis e, the counter will be lo aded with an incorrect count. the control word register at port 43h controls the operation of all three counters. several commands are available: ? control word command. specifies which counter to read or write, the operating mode, and the count format (binary or bcd). ? counter latch command. latches the current count so that it can be read by the system. the countdown process continues. ? read back command. reads the count value, programmed mode, the current state of the out pins, and the state of the null count flag of the selected counter. table 5-11 lists the six operating modes for the interval counters. 5.8.2 reading from the interval timer it is often desirable to read the value of a coun ter without disturbing the count in progress. there are three methods for reading the counters: a simp le read operation, counter latch command, and the read-back command. each is explained below. with the simple read and counter latch command methods, the coun t must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other. read, write, or programming operations for other counters may be inserted between them. table 5-11. counter operating modes mode function description 0 out signal on end of count (=0) output is 0. when count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 hardware retriggerable one-shot output is 0. when count goes to 0, output goes to 1 for one clock time. 2 rate generator (divide by n counter) output is 1. output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3 square wave output output is 1. output goes to 0 when counter rolls over, and counter is reloaded. output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 software triggered strobe output is 1. output goes to 0 when count expires for one clock time. 5 hardware triggered strobe output is 1. output goes to 0 when count expires for one clock time.
130 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.8.2.1 simple read the first method is to perform a simple read operation. the counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). note: performing a direct read from th e counter does not return a determ inate value, because the counting process is asynchronous to read operations. however, in the case of counter 2, the count can be stopped by writing to the gate bit in port 61h. 5.8.2.2 counter latch command the counter latch command, written to port 43h, latches the count of a specific counter at the time the command is received. this command is used to ensure that the count r ead from the counter is accurate, particularly when reading a two-byte coun t. the count value is then read from each counter?s count register as was programmed by the control register. the count is held in the latch until it is read or the counter is reprogrammed. the count is then unlatched. this allows reading the contents of th e counters on the fly wit hout affecting counting in progress. multiple counter latch commands may be used to latch more than one counter. counter latch commands do not affect the programmed mode of the counter in any way. if a counter is latched and then, some time later, latched again before the count is read, the second counter latch command is ignored. the count read is the count at the time the first counter latch command was issued. 5.8.2.3 read back command the read back command, written to port 43h, latches the count value, programmed mode, and current states of the out pin and null count flag of the selected counter or counters. the value of the counter and its status may then be read by i/o access to the counter address. the read back command may be used to latch multiple counter outputs at one time. this single command is functionally equivalent to several counter latch commands, one for each counter latched. each counter's latched count is held until it is read or reprogrammed. once read, a counter is unlatched. the other counters remain latched until they are read. if multiple count read back commands are issued to the same counter without reading the count, all but the first are ignored. the read back command may additionally be used to latch status information of selected counters. the status of a counter is accessed by a read from that counter's i/o port address. if multiple counter status latch operations are performed wi thout reading the status , all but the first are ignored. both count and status of the selected counters ma y be latched simultaneously. this is functionally the same as issuing two consecutive, separate read back commands. if multiple count and/or status read back commands are issued to the same counters w ithout any intervening reads, all but the first are ignored. if both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latche d first. the next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. subsequent reads return unlatched count.
intel ? i/o controller hub 6 (ich6) family datasheet 131 functional description 5.9 8259 interrupt controllers (pic) (d31:f0) the ich6 incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the isa compatible interrupts. these interrupts are: sy stem timer, keyboard controller, serial ports, parallel ports, floppy disk, ide, mouse, and dma channels. in addition, this interrupt controller can support the pci based interrupts, by mapping the pci interrupt onto the compatible isa interrupt line. each 8259 co re supports eight interrupts, numbered 0 ? 7. table 5-12 shows how the cores are connected. . the ich6 cascades the slave controller onto the master controller thro ugh master controller interrupt input 2. this means there are only 15 possible interrupts for the ich6 pic. interrupts can individually be programmed to be ed ge or level, except for irq0, irq2, irq8#, and irq13. note: active-low interrupt sources (e.g., the pirq#s) ar e inverted inside the ich6. in the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. therefore, the term ?high? indicates ?active,? which means ?low? on an originating pirq#. table 5-12. interrupt controller core connections 8259 8259 input typical interrupt source connected pin / function master 0 internal internal timer / counter 0 output / hpet #0 1 keyboard irq1 via serirq 2 internal slave controller intr output 3 serial port a irq3 via serirq, pirq# 4 serial port b irq4 via serirq, pirq# 5 parallel port / generic irq5 via serirq, pirq# 6 floppy disk irq6 via serirq, pirq# 7 parallel port / generic irq7 via serirq, pirq# slave 0 internal real time clock internal rtc / hpet #1 1 generic irq9 via serirq, sci, tco, or pirq# 2 generic irq10 via serirq, sci, tco, or pirq# 3 generic irq11 via serirq, sci, tco, or pirq# 4 ps/2 mouse irq12 via serirq, sci, tco, or pirq# 5 internal state machine output based on processor ferr# assertion. may optionally be used for sci or tco interrupt if ferr# not needed. 6 ide cable, sata ideirq (legacy mode, non-combined or combined mapped as primary), sata primary (legacy mode), or via serirq or pirq# 7 ide cable, sata ideirq (legacy mode ? combined, mapped as secondary), sata secondary (legacy mode) or via serirq or pirq#
132 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.9.1 interrupt handling 5.9.1.1 generating interrupts the pic interrupt sequence involves three bits, fr om the irr, isr, and imr, for each interrupt level. these bits are used to determine the interr upt vector returned, and status of any other pending interrupts. table 5-13 defines the irr, isr, and imr. 5.9.1.2 acknowledging interrupts the processor generates an interrupt acknowledge cycl e that is translated by the host bridge into a pci interrupt acknowledge cycle to the ich6. the pic translates this command into two internal inta# pulses expected by the 8259 cores. the pic uses the first internal inta# pulse to freeze the state of the interrupts for priority resolution. on the second inta# pulse, the master or slave sends the interrupt vector to the processor with the ack nowledged interrupt code. this code is based upon bits [7:3] of the corresponding icw2 register, comb ined with three bits representing the interrupt within that controller. table 5-13. interrupt status registers bit description irr interrupt request register. this bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. th is bit is set whether or not the interrupt is masked. however, a masked interrupt will not generate intr. isr interrupt service register. this bit is set, and the corresponding irr bit cleared, when an interrupt acknowledge cycle is seen, and the vect or returned is for that interrupt. imr interrupt mask register. this bit determines whether an interru pt is masked. masked interrupts will not generate intr. table 5-14. content of interrupt vector byte master, slave interrupt bits [7:3] bits [2:0] irq7,15 icw2[7:3] 111 irq6,14 110 irq5,13 101 irq4,12 100 irq3,11 011 irq2,10 010 irq1,9 001 irq0,8 000
intel ? i/o controller hub 6 (ich6) family datasheet 133 functional description 5.9.1.3 hardware/softwa re interrupt sequence 1. one or more of the interrupt request lines (irq) are raised high in edge mode, or seen high in level mode, setting the corresponding irr bit. 2. the pic sends intr active to the processor if an asserted interrupt is not masked. 3. the processor acknowledges the intr and respond s with an interrupt acknowledge cycle. the cycle is translated into a pci interrupt acknowledge cycle by th e host bridge. this command is broadcast over pci by the ich6. 4. upon observing its own interrupt acknowledge cycle on pci, the ich6 converts it into the two cycles that the internal 8259 pair can resp ond to. each cycle appears as an interrupt acknowledge pulse on the internal inta# pin of the cascaded interrupt controllers. 5. upon receiving the first internally generated inta# pulse, th e highest priority isr bit is set and the corresponding irr bit is reset. on th e trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. the slave controller uses these bits to deter mine if it must respond with an interrupt vector during the second inta# pulse. 6. upon receiving the second inte rnally generated inta# pulse, the pic returns the interrupt vector. if no interr upt request is present because the reque st was too short in duration, the pic returns vector 7 from the master controller. 7. this completes the interrupt cycle. in aeoi mode the isr bit is reset at the end of the second inta# pulse. otherwise, the is r bit remains set until an appr opriate eoi command is issued at the end of the interrupt subroutine. 5.9.2 initialization command words (icwx) before operation can begin, each 8259 must be initialized. in the ich6, this is a four byte sequence. the four initializatio n command words are referred to by their acronyms: icw1, icw2, icw3, and icw4. the base address for each 8259 ini tialization command word is a fi xed location in the i/o memory space: 20h for the master controller , and a0h for the slave controller. 5.9.2.1 icw1 an i/o write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to icw1. upon sensing this write, the ich6 pic expects three more byte writes to 21h for the master controller, or a1h for the sl ave controller, to complete the icw sequence. a write to icw1 starts the initialization sequence during which the following automatically occur: 1. following initialization, an interrupt request (i rq) input must make a low-to-high transition to generate an interrupt. 2. the interrupt mask register is cleared. 3. irq7 input is assigned priority 7. 4. the slave mode address is set to 7. 5. special mask mode is cleared and status read is set to irr.
134 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.9.2.2 icw2 the second write in the sequence (icw2) is progra mmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. a different base is selected for each interrupt controller. 5.9.2.3 icw3 the third write in the sequence (icw3) ha s a different meaning for each controller. ? for the master controller, icw3 is used to indi cate which irq input line is used to cascade the slave controller. within the ich6, irq2 is us ed. therefore, bit 2 of icw3 on the master controller is set to a 1, and the other bits are set to 0s. ? for the slave controller, icw3 is the slave identification code used during an interrupt acknowledge cycle. on interrupt acknowledge cy cles, the master controller broadcasts a code to the slave controller if the cascaded interr upt won arbitration on the master controller. the slave controller compares this id entification code to the value st ored in its icw3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector. 5.9.2.4 icw4 the final write in the sequence (icw4) must be pr ogrammed for both controllers. at the very least, bit 0 must be set to a 1 to indicate that the cont rollers are operating in an intel architecture-based system. 5.9.3 operation command words (ocw) these command words reprogram the interrupt controller to operate in various interrupt modes. ? ocw1 masks and unmasks interrupt lines. ? ocw2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the eoi function. ? ocw3 is sets up isr/irr reads, enables/disabl es the special mask mode (smm), and enables/ disables polled interrupt mode. 5.9.4 modes of operation 5.9.4.1 fully nested mode in this mode, interrupt requests are ordered in pr iority from 0 through 7, with 0 being the highest. when an interrupt is acknowledged, the highest prio rity request is determin ed and its vector placed on the bus. additionally, the isr for the interrup t is set. this isr bit remains set until: the processor issues an eoi command im mediately before returning from the service routine; or if in aeoi mode, on the trailing edge of the second inta#. while the isr bit is set, all further interrupts of the same or lower priority are inhibite d, while higher levels generate another interrupt. interrupt priorities can be changed in the rotating priority mode.
intel ? i/o controller hub 6 (ich6) family datasheet 135 functional description 5.9.4.2 special fully-nested mode this mode is used in the case of a system wher e cascading is used, and th e priority has to be conserved within each slave. in this case, the sp ecial fully-nested mode is programmed to the master controller. this mode is similar to the fully-nested mode with the following exceptions: ? when an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and init iate interrupts to the processor. in the normal- nested mode, a slave is masked ou t when its request is in service. ? when exiting the interrupt service routine, software has to check whether the interrupt serviced was the only one from that slave. this is done by sending a non-specific eoi command to the slave and then read ing its isr. if it is 0, a non-sp ecific eoi can also be sent to the master. 5.9.4.3 automatic rotation mo de (equal priority devices) in some applications, there are a number of in terrupting devices of equal priority. automatic rotation mode provides for a sequential 8-way rota tion. in this mode, a device receives the lowest priority after being serviced. in the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. there are two ways to accomplish automatic ro tation using ocw2; the rotation on non-specific eoi command (r=1, sl=0, eoi=1) and the rotate in automatic eoi mode which is set by (r=1, sl=0, eoi=0). 5.9.4.4 specific rotation mo de (specific priority) software can change interrupt priorities by programming the bottom priority. for example, if irq5 is programmed as the bottom priority device, then irq6 is the highest priority device. the set priority command is issued in ocw2 to accomplish this , where: r=1, sl=1, and lo?l2 is the binary priority level code of the bottom priority device. in this mode, internal status is updated by software control during ocw2. however, it is independent of the eoi command. priority changes can be executed during an eoi command by using the rotate on specific eoi command in ocw2 (r=1, sl=1, eoi=1 and lo?l2=irq level to receive bottom priority. 5.9.4.5 poll mode poll mode can be used to conserve space in the interrupt vector tabl e. multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. poll mode can also be used to expand the number of interrupts. the polling interrupt service routine can call th e appropriate service routine, in stead of providing the interrupt vectors in the vector table. in this mode, the intr output is not used and the microprocessor internal interrupt enable flip-flop is reset, di sabling its interrupt input. service to devices is achieved by software using a poll command. the poll command is issued by setting p=1 in oc w3. the pic treats its next i/o read as an interrupt acknowledge, sets the appropriate isr bit if there is a request, and reads the priority level. interrupts are frozen from the oc w3 write to the i/o read. the by te returned during the i/o read contains a 1 in bit 7 if there is an interrupt, an d the binary code of the highest priority level in bits 2:0.
136 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.9.4.6 cascade mode the pic in the ich6 has one master 8259 and one slave 8259 cascaded onto the master through irq2. this configuration can handle up to 15 separate priority levels. the master controls the slaves through a three bit internal bus. in the ich6, when the master drives 010b on this bus, the slave controller takes responsibility for returnin g the interrupt vector. an eoi command must be issued twice: once for the ma ster and once for the slave. 5.9.4.7 edge and level triggered mode in isa systems this mode is programmed using b it 3 in icw1, which sets level or edge for the entire controller. in the ich6, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. this is the edge/level control registers elcr1 and elcr2. if an elcr bit is 0, an interrupt request will be recognized by a low-to -high transition on the corresponding irq input. the irq input can remain high without generating another interrupt. if an elcr bit is 1, an interrupt request will be recognized by a high level on the corresponding irq input and there is no need for an edge detection. the interrupt request must be removed before the eoi command is issued to preven t a second interrupt from occurring. in both the edge and level triggered modes, the irq inputs must remain active until after the falling edge of the first internal inta#. if the irq inpu t goes inactive before this time, a default irq7 vector is returned. 5.9.4.8 end of interrupt (eoi) operations an eoi can occur in one of two fashions: by a command word write issued to the pic before returning from a service routine, the eoi command; or automatically when aeoi bit in icw4 is set to 1. 5.9.4.9 normal end of interrupt in normal eoi, software writes an eoi command before leaving the interrupt service routine to mark the interrupt as completed. there ar e two forms of eoi commands: specific and non-specific. when a non-specifi c eoi command is issued, the pi c clears the highest isr bit of those that are set to 1. non-specific eoi is the normal mode of operation of the pic within the ich6, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. when the pic is operat ed in modes that preserve the fu lly nested structure, software can determine which isr bit to clear by issuing a specific eoi. an isr bit that is masked is not cleared by a non-specific eoi if the pic is in th e special mask mode. an eoi command must be issued for both the mast er and slave controller. 5.9.4.10 automatic end of interrupt mode in this mode, the pic automatically performs a non-specific eoi operation at the trailing edge of the last interrupt acknowledge pulse. from a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single pic. the aeoi mode can only be used in the master co ntroller and not the slave controller.
intel ? i/o controller hub 6 (ich6) family datasheet 137 functional description 5.9.5 masking interrupts 5.9.5.1 masking on an indi vidual interrupt request each interrupt request can be masked individually by the interrupt mask register (imr). this register is programmed through ocw1. each bit in the imr masks one interrupt channel. masking irq2 on the master controller masks all re quests for service from the slave controller. 5.9.5.2 special mask mode some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. for example, the routin e may wish to inhibit lower priority requests for a portion of its executio n but enable some of them for another portion. the special mask mode enables all interrupts not masked by a bit set in the mask register. normally, when an interrupt serv ice routine acknowledges an interrupt without issuing an eoi to clear the isr bit, the interrupt controller inhibits all lower priority requests. in the special mask mode, any interrupts may be selectively enabled by loading the mask register with the appropriate pattern. the special mask mode is set by ocw3 where: ssmm=1, smm=1, and cleared where ssmm=1, smm=0. 5.9.6 steering pci interrupts the ich6 can be programmed to allow pirqa#-pirqh# to be internally routed to interrupts 3?7, 9?12, 14 or 15. the assignment is programmable through the through the pirqx route control registers, located at 60?63h and 68?6bh in device 31:function 0. one or more pirqx# lines can be routed to the same irqx input. if interrupt steering is not required, the route registers can be programmed to disable steering. the pirqx# lines are defined as active low, level sensitive to allow multiple interrupts on a pci board to share a single line across the connector. when a pirqx# is routed to specified irq line, software must change the irq's corresponding elcr bit to level sensitive mode. the ich6 internally inverts the pirqx# line to send an active high level to the pic. when a pci interrupt is routed onto the pic, the selected irq can no longer be used by an active high device (through serirq). however, active low interrupts can share their interrupt with pci interrupts. internal sources of the pirqs, including sci and tco interrupts, cause the external pirq to be asserted. the ich6 receives the pirq input, like all of the other external sources, and routes it accordingly.
138 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.10 advanced programmable interrupt controller (apic) (d31:f0) in addition to the standard isa-compatible pi c described in the previous chapter, the ich6 incorporates the apic. while the st andard interrupt controller is intended for use in a uni-processor system, apic can be used in either a uni-processor or multi-processor system. 5.10.1 interrupt handling the i/o apic handles interrupts very differently than the 8259. briefly, these differences are: ? method of interrupt transmission. the i/o apic transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle. ? interrupt priority. the priority of interrupts in the i/ o apic is independent of the interrupt number. for example, interrupt 10 can be given a higher priority than interrupt 3. ? more interrupts. the i/o apic in the ich6 supports a total of 24 interrupts. ? multiple interrupt controllers. the i/o apic architecture a llows for multiple i/o apic devices in the system with their own interrupt vectors. 5.10.2 interrupt mapping the i/o apic within the ich6 supports 24 apic interrupts. each interrupt has its own unique vector assigned by software. the interrupt vectors are mapped as follows, and match ?config 6? of the multi-processo r specification. table 5-15. apic interrupt mapping (sheet 1 of 2) irq # via serirq direct from pin via pci message internal modules 0 no no no cascade from 8259 #1 1yes no yes 2 no no no 8254 counter 0, hpet #0 (legacy mode) 3yes no yes 4yes no yes 5yes no yes 6yes no yes 7yes no yes 8 no no no rtc, hpet #1 (legacy mode) 9 yes no yes option for sci, tco 10 yes no yes option for sci, tco 11 yes no yes hpet #2, option for sci, tco 12 yes no yes 13 no no no ferr# logic 14 yes yes 1 yes ideirq (legacy mode, non-combined or combined mapped as primary), sata primary (legacy mode) 15 yes yes yes ideirq (legacy mode ? combined, mapped as secondary), sata secondary (legacy mode)
intel ? i/o controller hub 6 (ich6) family datasheet 139 functional description notes: 1. ideirq can only be driven directly from the pin when in legacy ide mode. 2. when programming the polarity of internal interrupt sources on the apic, interrupts 0 through 15 receive active-high internal interrupt sources, while interr upts 16 through 23 receive active-low internal interrupt sources. 3. if irq 11 is used for hpet #2, software should ensur e irq 11 is not shared wi th any other devices to guarantee the proper operation of hpet #2. ich6 hardware does not prevent sharing of irq 11. 5.10.3 pci / pci express* message-based interrupts when external devices through pci / pci express wish to generate an interrupt, they will send the message defined in the pci express* base specific ation, revision 1.0a for generating inta# - intd#. these will be translated internal assertions/de-assertions of inta# - intd#. 5.10.4 front side bus interrupt delivery for processors that support front side bus (fsb) interrupt delivery, the ich6 requires that the i/o apic deliver interrupt messages to the processor in a parallel manner, rather than using the i/o apic serial scheme. this is done by the ich6 writing (via dmi) to a memory location that is snooped by the processor(s). the processor(s) snoop the cycle to know which interrupt goes active. the following sequence is used: 1. when the ich6 detects an interrupt event (activ e edge for edge-triggered mode or a change for level-triggered mode), it sets or resets the in ternal irr bit associated with that interrupt. 2. internally, the ich6 requests to use the bus in a way that automati cally flushes upstream buffers. this can be internally implemented similar to a dma device request. 3. the ich6 then delivers the message by perfor ming a write cycle to the appropriate address with the appropriate data. the address a nd data formats are described below in section 5.10.4.4 . note: fsb interrupt delivery compatibility with processor clock control depends on the processor, not the ich6. 16 pirqa# pirqa# yes internal devices are routable; see section 7.1.41 thru section 7.1.50 . 17 pirqb# pirqb# 18 pirqc# pirqc# 19 pirqd# pirqd# 20 n/a pirqe# yes option for sci, tco, hpet #0,1,2. other internal devices are routable; see section 7.1.41 thru section 7.1.50 . 21 n/a pirqf# 22 n/a pirqg# 23 n/a pirqh# table 5-15. apic interrupt mapping (sheet 2 of 2) irq # via serirq direct from pin via pci message internal modules
140 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.10.4.1 edge-triggered operation in this case, the ?assert message? is sent when th ere is an inactive-to-act ive edge on the interrupt. 5.10.4.2 level-triggered operation in this case, the ?assert message? is sent when th ere is an inactive-to-activ e edge on the interrupt. if after the eoi the interrupt is still active, then another ?assert message? is sent to indicate that the interrupt is still active. 5.10.4.3 registers associat ed with front side bus interrupt delivery capabilities indication: the capability to support front side bus interrupt delivery is indicated via acpi configuration techniques. this involves the bios creating a data structure that gets reported to the acpi configuration software. 5.10.4.4 interrupt message format the ich6 writes the message to pci (and to the ho st controller) as a 32-bit memory write cycle. it uses the formats shown in table 5-16 and table 5-17 for the address and data. the local apic (in the processor) has a delivery mode option to interpret front side bus messages as a smi in which case the processor treats the in coming interrupt as a smi instead of as an interrupt. this does not mean that the ich6 has any way to have a smi source from ich6 power management logic cause the i/o apic to send an smi message (there is no way to do this). the ich6?s i/o apic can only send interrupts due to interrupts which do not include smi, nmi or init. this means that in ia32/ia64 based platforms, front side bus interrupt message format delivery modes 010 (smi/pmi), 100 (nmi), and 101 (i nit) as indicated in this section, must not be used and is not supported. only the hardware pin connection is supported by ich6. : table 5-16. interrupt message address format bit description 31:20 will always be feeh 19:12 destination id: this is the same as bits 63:56 of the i/o redirection table entry for the interrupt associated with this message. 11:4 extended destination id : this is the same as bits 55:48 of the i/o redirection table entry for the interrupt associated with this message. 3 redirection hint: this bit is used by the processor host bridge to allow the interrupt message to be redirected. 0 = the message will be delivered to t he agent (processor) listed in bits 19:12. 1 = the message will be delivered to an agent with a lower interrupt priority this can be derived from bits 10:8 in the data field (see below). the redirection hint bit will be a 1 if bits 10 :8 in the delivery mode field associated with corresponding interrupt are encoded as 001 (lowest pr iority). otherwise, the redirection hint bit will be 0 2 destination mode: this bit is used only the r edirection hint bit is set to 1. if the redirection hint bit and the destination mode bit are both set to 1, then the logical destination mode is used, and the redirection is limited only to those processors that are part of the logical group as based on the logical id. 1:0 will always be 00.
intel ? i/o controller hub 6 (ich6) family datasheet 141 functional description 5.11 serial interrupt (d31:f0) the ich6 supports a serial irq sc heme. this allows a single signal to be used to report interrupt requests. the signal used to transmit this informat ion is shared between th e host, the ich6, and all peripherals that support serial interrupts. the si gnal line, serirq, is synchronous to pci clock, and follows the sustained tri-state protocol that is used by all pci signals. this means that if a device has driven serirq low, it will first drive it high synchronous to pci clock and release it the following pci clock. the serial irq protocol defines this sustained tri-state signaling in the following fashion: ? s ? sample phase. signal driven low ? r ? recovery phase. signal driven high ? t ? turn-around phase. signal released the ich6 supports a message for 21 serial inte rrupts. these represent the 15 isa interrupts (irq0?1, 2?15), the four pci interrupts, and the control signals smi# and iochk#. the serial irq protocol does not support the additional apic interrupts (20?23). note: when the ide controller is enab led or the sata controller is configured for legacy ide mode, irq14 and irq15 are are expected to behave as is a legacy interrupts, which cannot be shared, i.e. through the serial interrupt pin. if irq14/irq15 are shared with the serial interrupt pin then abnormal system behavior may occur. for example, irq14/irq15 may not be detected by the ich6?s interrupt controller. table 5-17. interrupt message data format bit description 31:16 will always be 0000h. 15 trigger mode: 1 = level, 0 = edge. same as the corres ponding bit in the i/o redirection table for that interrupt. 14 delivery status: 1 = assert, 0 = de-assert. only assert messages are sent. this bit is always 1. 13:12 will always be 00 11 destination mode: 1 = logical. 0 = physical. same as the corresponding bit in the i/o redirection table for that interrupt. 10:8 delivery mode: this is the same as the corresponding bi ts in the i/o redirection table for that interrupt. 000 = fixed 100 = nmi 001 = lowest priority 101 = init 010 = smi/pmi 110 = reserved 011 = reserved 111 = extint 7:0 vector: this is the same as the corresponding bits in the i/o redirection table for that interrupt.
142 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.11.1 start frame the serial irq protocol has two modes of operation which affect the start frame. these two modes are: continuous, where the ich6 is solely respons ible for generating the start frame; and quiet, where a serial irq periph eral is responsible for beginning the start frame. the mode that must first be ente red when enabling the serial irq protocol is continuous mode. in this mode, the ich6 asserts the start frame. this start frame is 4, 6, or 8 pci clocks wide based upon the serial irq control register, bits 1:0 at 64h in device 31:functio n 0 configuration space. this is a polling mode. when the serial irq stream ente rs quiet mode (signaled in the stop frame), the serirq line remains inactive and pulled up be tween the stop and start frame until a peripheral drives the serirq signal low. the ich6 senses the line low and continues to drive it low for the remainder of the start frame. since the firs t pci clock of the start frame was driven by the peripheral in this mode, the ich6 drives the serirq line low for 1 pci clock less than in continuous mode. this mode of operation allows for a quiet, and therefore lower power, operation. 5.11.2 data frames once the start frame has been initiated, all of th e serirq peripherals must start counting frames based on the rising edge of serirq. each of the irq/data frames has exactly 3 phases of 1 clock each: ? sample phase. during this phase, the serirq device drives serirq low if the corresponding interrupt signal is low. if the co rresponding interrupt is high, then the serirq devices tri-state the serirq signal. the serirq line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). a low level during the irq0 ? 1 and irq2 ? 15 frames indicates that an active-high isa interrupt is not being requested, but a low level during the pci int[a:d], smi#, and iochk# frame indicates that an active-low interrupt is being requested. ? recovery phase. during this phase, the device drives the serirq line high if in the sample phase it was driven low. if it was not driven in th e sample phase, it is tri-stated in this phase. ? turn-around phase. the device tri-states the serirq line 5.11.3 stop frame after all data frames, a stop frame is driven by the ich6. the serirq signal is driven low by the ich6 for 2 or 3 pci clocks. the number of cloc ks is determined by the serirq configuration register. the number of clocks determines the next mode: table 5-18. stop frame explanation stop frame width next mode 2 pci clocks quiet mode. any serirq device may initiate a start frame 3 pci clocks continuous mode. only the host (intel ? ich6) may initiate a start frame
intel ? i/o controller hub 6 (ich6) family datasheet 143 functional description 5.11.4 specific interrupts not supported via serirq there are three interrupts seen through the serial st ream that are not supported by the ich6. these interrupts are generated internally , and are not sharable with other devices within the system. these interrupts are: ? irq0. heartbeat interrupt generated off of the internal 8254 counter 0. ? irq8#. rtc interrupt can only be generated internally. ? irq13. floating point error interrupt genera ted off of the processor assertion of ferr#. the ich6 ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. 5.11.5 data frame format table 5-19 shows the format of the data frames. for the pci interrupts (a ? d), the output from the ich6 is anded with the pci input signal. this way, the interrupt can be signaled via both the pci interrupt input signal and via the serirq signal (they are shared). table 5-19. data frame format data frame # interrupt clocks past start frame comment 1 irq0 2 ignored. irq0 can only be generated via the internal 8524 2irq1 5 3 smi# 8 causes smi# if low. will set the serirq_smi_sts bit. 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9 irq8 26 ignored. irq8# can only be generated internally. 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 ignored. irq13 can only be generated from ferr# 15 irq14 44 not attached to pata or sata logic 16 irq15 47 not attached to pata or sata logic 17 iochck# 50 same as isa iochck# going active. 18 pci inta# 53 drive pirqa# 19 pci intb# 56 drive pirqb# 20 pci intc# 59 drive pirqc# 21 pci intd# 62 drive pirqd#
144 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.12 real time clock (d31:f0) the real time clock (rtc) module provides a battery backed-up date and time keeping device with two banks of static ram with 128 bytes each, although the first bank has 114 bytes for general purpose usage. three interr upt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 s to 500 ms, and end of update cycle notification. seconds, minutes, hours, days, day of week, m onth, and year are counted. daylight savings compensation is available. the h our is represented in twelve or twenty-four hour format, and data can be represented in bcd or binary format. the design is functionally compatible with the motorola ms146818b. the time keeping comes from a 32.768 khz oscillating source, which is divided to achieve an update every second. the lower 14 bytes on the lower ram block has very specific functions. the first ten are for time and date information. the next four (0ah to 0dh) are registers, which configure and report rtc functions. the time and calendar data should match the data mode (bcd or binary) and hour mode (12 or 24 hour) as selected in register b. it is up to the programmer to make sure that data stored in these locations is within the reas onable values ranges and represents a possible date and time. the exception to these ranges is to store a value of c0?ffh in the alarm bytes to indicate a don?t care situation. all alarm conditions must match to trig ger an alarm flag, which could trigger an alarm interrupt if enabled. the set bit must be 1 wh ile programming these locations to avoid clashes with an update cycle. access to time and date information is done through the ram locations. if a ram read from the ten tim e and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. any ram writes under the same conditions are ignored. note: the leap year determination for adding a 29th day to february does not take into account the end-of-the-century exceptions. the logic simply assumes that all years divisible by 4 are leap years. according to the royal ob servatory greenwich, years that ar e divisible by 100 are typically not leap years. in every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap -year occurs. note that the year 2100 will be the first time in which the current rtc implementation would in correctly calculate the leap-year. the ich6 does not implem ent month/year alarms. 5.12.1 update cycles an update cycle occurs once a second, if the set bi t of register b is not asserted and the divide chain is properly configured. during this proced ure, the stored time and date are incremented, overflow is checked, a ma tching alarm condition is checked, and the time and date are rewritten to the ram locations. the update cycle will start at least 488 s afte r the uip bit of register a is asserted, and the entire cycle does not take more than 1984 s to complete. the time and date ram locations (0 ? 9) are disconnected from the ex ternal bus during this time. to avoid update and data corrupt ion conditions, external ram access to these locations can safely occur at two times. when a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. if the uip bit of register a is detected to be low, there is at least 488 s before the update cycle begins. warning: the overflow conditions for leap years and daylig ht savings adjustments are based on more than one date or time item. to ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before one of these conditions (leap year, daylight savings time adjustments) occurs.
intel ? i/o controller hub 6 (ich6) family datasheet 145 functional description 5.12.2 interrupts the real-time clock interru pt is internally routed within the ich6 both to the i/o apic and the 8259. it is mapped to interrupt vector 8. this interrupt does not leave the ich6, nor is it shared with any other interrupt. irq8# from the serirq str eam is ignored. however, the high performance event timers can also be mapped to irq8#; in this case, the rtc interrupt is blocked. 5.12.3 lockable ram ranges the rtc?s battery-backed ram supports two 8- byte ranges that can be locked via the configuration space. if the lockin g bits are set, the correspondi ng range in the ram will not be readable or writable. a write cycl e to those locations will have no effect. a read cycle to those locations will not return the location?s actual value (resultant value is undefined). once a range is locked, the range can be unlocked only by a hard reset, which will invoke the bios and allow it to relock the ram range. 5.12.4 century rollover the ich6 detects a rollover when the year byte (r tc i/o space, index offset 09h) transitions from 99 to 00. upon detecting the rollover, the ich6 sets the newcentury_sts bit (tcobase + 04h, bit 7). if the system is in an s0 state, this causes an smi#. the smi# handler can update registers in the rtc ram that are associated with century value. if the system is in a sleep state (s1 ? s5) when the century rollover occurs, the ich6 also sets the newcentury_sts bit, but no smi# is generated. when the system resumes from the sleep state, bios should check the newcentury_sts bit and update the century value in the rtc ram. 5.12.5 clearing battery-backed rtc ram clearing cmos ram in an ich6-based platform can be done by using a jumper on rtcrst# or gpi. implementations should not attempt to clear cmos by using a jumper to pull vccrtc low. using rtcrst# to clear cmos a jumper on rtcrst# can be used to clear cmos va lues, as well as reset to default, the state of those configuration bits that reside in the rt c power well. when the rtcrst# is strapped to ground, the rtc_pwr_sts bit (d31:f0:a4h bit 2) will be set and those configuration bits in the rtc power well will be set to their default stat e. bios can monitor the state of this bit, and manually clear the rtc cmos ar ray once the system is booted. the normal position would cause rtcrst# to be pulled up through a weak pull-up resistor. table 5-20 shows which bits are set to their default state when rtcrst# is asserted. th is rtcrst# jumper techni que allows the jumper to be moved and then replaced?a ll while the system is powered off. then, on ce booted, the rtc_pwr_sts can be detected in the set state.
146 intel ? i/o controller hub 6 (i ch6) family datasheet functional description table 5-20. configuration bits reset by rtcrst# assertion bit name register location bit(s) default state alarm interrupt enable (aie) register b (general configuration) (rtc_regb) i/o space (rtc index + 0bh) 5 x alarm flag (af) register c (flag register) (rtc_regc) i/o space (rtc index + 0ch) 5 x swsmi_rate_sel general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 7:6 0 slp_s4# minimum assertion width general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 5:4 0 slp_s4# assertion stretch enable general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 3 0 rtc power status (rtc_pwr_sts) general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 2 0 power failure (pwr_flr) general pm configuration 3 register (gen_pmcon_3) d31:f0:a4h 1 0 afterg3_en general pm configuration 3 register gen_pmcon_3 d31:f0:a4h 0 0 power button override status (prbtnor_sts) power management 1 status register (pm1_sts) pmbase + 00h 11 0 rtc event enable (rtc_en) power management 1 enable register (pm1_en) pmbase + 02h 10 0 sleep type (slp_typ) power management 1 control (pm1_cnt) pmbase + 04h 12:10 0 pme_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 11 0 batlow_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 10 0 ri_en general purpose event 0 enables register (gpe0_en) pmbase + 2ch 8 0 newcentury_sts tco1 status register (tco1_sts) tcobase + 04h 7 0 intruder detect (intrd_det) tco2 status register (tco2_sts) tcobase + 06h 0 0 top swap (ts) backed up control register (buc) chipset configuration registers:offset 3414h 0x pata reset state (prs) (mobile only) backed up control register (buc) chipset configuration registers:offset 3414h 11
intel ? i/o controller hub 6 (ich6) family datasheet 147 functional description using a gpi to clear cmos a jumper on a gpi can also be used to clear cmos values. bios would detect the setting of this gpi on system boot-up, and ma nually clear th e cmos array. note: the gpi strap technique to clear cmos requires mul tiple steps to implement. the system is booted with the jumper in new position, then powered back down. the jumper is replaced back to the normal position, then the system is rebooted again. warning: clearing cmos, using a jumper on vccrtc, must not be implemented. 5.13 processor interface (d31:f0) the ich6 interfaces to the pro cessor with a variety of signals ? standard outputs to processor: a20m#, sm i#, nmi, init#, intr, stpclk#, ignne#, cpuslp#, cpupwrgd ? standard input from processor: ferr# ? intel speedstep ? technology output to processor: cpupwrgood (in mobile configurations) most ich6 outputs to the processor use standa rd buffers. the ich6 has separate v_cpu_io signals that are pulled up at the system level to the processor voltage, and thus determines v oh for the outputs to the processor. 5.13.1 processor interface signals this section describes each of the signals that interface betw een the ich6 and the processor(s). note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping. 5.13.1.1 a20m# (mask a20) the a20m# signal is active (low) when both of the following conditions are true: ? the alt_a20_gate bit (bit 1 of port92 register) is a 0 ? the a20gate input signal is a 0 the a20gate input signal is expected to be generated by the external microcontroller (kbc). 5.13.1.2 init# (i nitialization) the init# signal is active (driven low) based on any one of several events described in table 5-21 . when any of these events occur, init# is dr iven low for 16 pci cloc ks, then driven high. note: the 16-clock counter for init# assertion halts wh ile stpclk# is active. therefore, if init# is supposed to go active while stpclk# is assert ed, it actually goes active after stpclk# goes inactive. this section refers to init#, but applies to tw o signals: init# and init3_3v#, as init3_3v# is functionally identical to init#, but signaling at 3.3 v.
148 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.13.1.3 ferr#/ignne# (numer ic coprocessor error / ignore numeric error) the ich6 supports the coprocessor error function with the ferr#/ignne# pins. the function is enabled via the coproc_err_en bit (chipset co nfiguration registers:offset 31ffh:bit 1). ferr# is tied directly to the co processor error signal of the proces sor. if ferr# is driven active by the processor, irq13 goes active (internally) . when it detects a write to the coproc_err register (i/o register f0h), the ich6 negates the internal irq13 and drives ignne# active. ignne# remains active until ferr# is driven in active. ignne# is never driven active unless ferr# is active. if coproc_err_en is not set, the assertion of ferr# will not generate an internal irq13, nor will the write to f0h generate ignne#. table 5-21. init# going active cause of init# going active comment shutdown special cycle from processor. port92 write, where init_now (bit 0) transitions from a 0 to a 1. portcf9 write, where sys_rst (bit 1) was a 0 and rst_cpu (bit 2) transitions from 0 to 1. rcin# input signal goes low. rcin# is expected to be driven by the external microcontroller (kbc). 0 to 1 transition on rcin# must occur before the intel ? ich6 will arm init# to be generated again. note: rcin# signal is expec ted to be high during s3 hot and low during s3 cold , s4, and s5 states. transition on the rcin# signal in those states (or the transition to those states) may not necessarily cause the init# signal to be generated to the processor. processor bist to enter bist, software sets cpu_bist_en bit and then does a full processor reset using the cf9 register. figure 5-6. coprocessor error timing diagram ferr# internal irq13 i/o write to f0h ignne#
intel ? i/o controller hub 6 (ich6) family datasheet 149 functional description 5.13.1.4 nmi (non-maskable interrupt) non-maskable interrupts (nmis) can be ge nerated by several sources, as described in table 5-22 . 5.13.1.5 stop clock request and processor sleep (stpclk# and cpuslp#) the ich6 power management logic contro ls these active-low signals. refer to section 5.14 for more information on the functionality of these signals. 5.13.1.6 processor power good (cpupwrgood) this signal is connected to the processor?s pwrg ood input. in mobile conf igurations to allow for intel speedstep technology support, this signal is kept high during an intel speedstep technology state transition to prevent loss of processor contex t. this is an open-drain output signal (external pull-up resistor required) that represents a logical and of the ich6 ?s pwrok and vrmpwrgd signals. 5.13.1.7 deeper sleep (d pslp#) (mobile only) this active-low signal controls the internal gating of the processor?s core clock. this signal asserts before and de-asserts after the stp_cpu# signa l to effectively stop the processor?s clock (internally) in the states in which stp_cpu# can be used to stop the processor?s clock externally. 5.13.2 dual-processor is sues (desktop only) 5.13.2.1 signal differences in dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs. table 5-22. nmi sources cause of nmi comment serr# goes active (either internally, externally via serr# signal, or via message from (g)mch) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). iochk# goes active via serirq# stream (isa system error) can instead be routed to generate an sci, through the nmi2sci_en bit (device 31:function 0, tco base + 08h, bit 11). table 5-23. dp signal differences signal difference a20m# / a20gate generally not used, but still supported by intel ? ich6. stpclk# used for s1 state as well as preparation for entry to s3?s5 also allows for therm# based throttling (n ot via acpi control methods). should be connected to both processors. ferr# / ignne# generally not used, but still supported by ich6.
150 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.13.2.2 power management for multiple-processor (or multiple- core) configurations in which mo re than one stop grant cycle may be generated, the (g)mch is expected to count stop grant cycles and only pass the last one through to the ich6. this prevents the ich6 from getting out of sync with the processor on multiple stpclk# assertions. because the s1 state will have the stpclk# signal active, the stpclk# signal can be connected to both processors. however, for acpi implemen tations, the bios must indicate that the ich6 only supports the c1 state for dual-processor designs. in going to the s1 state for desktop, multiple stop- grant cycles will be generated by the processors. the intel ich6 also has the option to assert the pr ocessor?s slp# signal (cpuslp#). it is assumed that prior to setting the slp_en bit that causes the tr ansition to the s1 state, the processors will not be executing code that is likely to delay the stop-grant cycles. in going to the s3, s4, or s5 st ates, the system will appear to pass throug h the s1 state; thus, stpclk# and slp# are also used. during the s3, s4, and s5 stat es, both processors will lose power. upon exit from those states, the processors will have their power restored. 5.14 power management (d31:f0) 5.14.1 features ? support for advanced configuration and power interface, version 2.0 (acpi) providing power and thermal management ? acpi 24-bit timer ? software initiated throttling of processor performance for thermal and power reduction ? hardware override to throttle proce ssor performance if system too hot ? sci and smi# generation ? pci pme# signal for wake up from low-power states ? system clock control ? (mobile only) acpi c2 state: stop grant (using stpclk# signal) halts processor?s instruction stream ? (mobile only) acpi c3 state: ability to halt processor clock (but not memory clock) ? (mobile only) acpi c4 state: ability to lower processor voltage. ? (mobile only) clkrun# protocol for pci clock starting/stopping ? system sleep state control ? acpi s1 state: stop grant (using stpclk# signal) halts processor?s instruction stream (only stpclk# active, and cpuslp# optional) ? acpi s3 state ? suspend to ram (str) ? acpi s4 state ? suspend-to-disk (std) ? acpi g2/s5 state ? soft off (soff) ? power failure detection and recovery ? streamlined legacy power management for apm-based systems
intel ? i/o controller hub 6 (ich6) family datasheet 151 functional description 5.14.2 intel ? ich6 and syst em power states table 5-24 shows the power states defined for ich6-b ased platforms. the state names generally match the corresponding acpi states. table 5-25 shows the transitions rules among the various states. note that transitions among the various states may appear to temporarily transitio n through intermediate st ates. for example, in going from s0 to s1, it may appear to pass through the g0/s0/c2 states. these intermediate transitions and st ates are not listed in the table. table 5-24. general power states for systems using intel ? ich6 state/ substates legacy name / description g0/s0/c0 full on: processor operating. indi vidual devices may be shut down to save power. the different processor operating levels are defined by cx states, as shown in table 5-25 . within the c0 state, the intel ? ich6 can throttle the processor us ing the stpclk# signal to reduce power consumption. the throttling can be initiat ed by software or by the operating system or bios. g0/s0/c1 auto-halt: processor has executed an autohalt in struction and is not executing code. the processor snoops the bus and maintains cache coherency. g0/s0/c2 (mobile only) stop-grant: the stpclk# signal goes active to t he processor. the processor performs a stop-grant cycle, halts its instruction stream , and remains in that state until the stpclk# signal goes inactive. in the stop-grant state, the processor snoops the bus and maintains cache coherency. g0/s0/c3 (mobile only) stop-clock: the stpclk# signal goes active to the processor. the processor performs a stop-grant cycle, halts its instruction stream. ich6 then asserts dpslp# followed by stp_cpu#, which forces the clock generator to stop the processor clock. this is also used for intel speedstep ? technology support. accesses to memory (by graphics, pci, or internal units) is not permitted while in a c3 state. g0/s0/c4 (mobile only) stop-clock with lower processor voltage: this closely resembles the g0/s0/c3 state. however, after the ich6 has asserted stp_cpu#, it then lowers the voltage to the processor. this reduces the leak age on the processor. prior to exiting the c4 state, the ich6 increases the voltage to the processor. g1/s1 stop-grant: similar to g0/s0/c2 state. ich6 also has the option to assert the cpuslp# signal to further reduce processor power consumption. note: the behavior for this state is slightly different when supporting ia64 processors. g1/s3 suspend-to-ram (str): the system context is maintained in system dram, but power is shut off to non-critical circuits. memory is retained, and refreshes continue. all clocks stop except rtc clock. g1/s4 suspend-to-disk (std): the context of the system is ma intained on the disk. all power is then shut off to the system except for the logic required to resume. g2/s5 soft off (soff): system context is not maintained. all power is shut off except for the logic required to restart. a full boot is required when waking. g3 mechanical off (moff): system context not maintained. al l power is shut off except for the rtc. no ?wake? events ar e possible, because the system does not have any power. this state occurs if the user removes the batteries, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the ?waking? logic. when system power returns, transition will depends on the state just prior to the entry to g3 and the afterg3 bit in the gen_pmcon3 register (d31:f0, offset a4). refer to table 5-32 for more details.
152 intel ? i/o controller hub 6 (i ch6) family datasheet functional description notes: 1. transitions from the s1?s5 or g3 states to the s0 state are deferred until batlow# is inactive in mobile configurations. 2. some wake events can be preserved through power failure. table 5-25. state transition rules for intel ? ich6 present state transition trigger next state g0/s0/c0 ? processor halt instruction ? level 2 read ? level 3 read (mobile only) ? level 4 read (mobile only) ? slp_en bit set ? power button override ? mechanical off/power failure ?g0/s0/c1 ?g0/s0/c2 ? g0/s0/c2, g0/s0/c3 or g0/s0/c4 - depending on c4onc3_en bit (d31:f0:offset a0h:bit 7) and bm_sts_zero_en bit (d31:f0:offset a9h :bit 2) (mobile only) ? g1/sx or g2/s5 state ?g2/s5 ?g3 g0/s0/c1 ? any enabled break event ? stpclk# goes active ? power button override ? power failure ?g0/s0/c0 ?g0/s0/c2 ?g2/s5 ?g3 g0/s0/c2 (mobile only) ? any enabled break event ? power button override ? power failure ? previously in c3/c4 and bus masters idle ?g0/s0/c0 ?g2/s5 ?g3 ? c3 or c4 - depending on pdme bit (d31:f0: offset a9h: bit 4) g0/s0/c3 (mobile only) ? any enabled break event ? any bus master event ? power button override ? power failure ? previously in c4 and bus masters idle ?g0/s0/c0 ? g0/s0/c2 - if pume bit (d31:f0: offset a9h: bit 3) is set, else g0/s0/c0 ?g2/s5 ?g3 ? c4 - depending on pdme bit (d31:f0: offset a9h: bit 4 g0/s0/c4 (mobile only) ? any enabled break event ? any bus master event ? power button override ? power failure ?g0/s0/c0 ? g0/s0/c2 - if pume bit (d31:f0: offset a9h: bit 3) is set, else g0/s0/c0 ?g2/s5 ?g3 g1/s1, g1/s3, or g1/s4 ? any enabled wake event ? power button override ? power failure ? g0/s0/c0 1 ?g2/s5 ?g3 g2/s5 ? any enabled wake event ? power failure ?g0/s0/c0 1 ?g3 g3 ? power returns ? optional to go to s0/c0 (reboot) or g2/s5 (stay off until power button pressed or other wake event). 1,2
intel ? i/o controller hub 6 (ich6) family datasheet 153 functional description 5.14.3 system power planes the system has several independent power planes, as described in table 5-26 . note that when a particular power plane is shut off, it should go to a 0 v level. s 5.14.4 smi#/sci generation on any smi# event taking place, ich6 asserts sm i# to the processor, which causes it to enter smm space. smi# remains active unt il the eos bit is set. when th e eos bit is set, smi# goes inactive for a minimum of 4 pciclk. if another smi event occurs, smi# is driven active again. the sci is a level-mode interrupt that is typically handled by an acpi-aware operating system. in non-apic systems (which is the default), the sci ir q is routed to one of the 8259 interrupts (irq 9, 10, or 11). the 8259 interrupt controller must be programmed to level mode for that interrupt. in systems using the apic, the sci can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. the interrupt polarity changes depending on whether it is on an interrupt shareable with a pirq or not (see section 10.1.13 ). the interrupt remains asserted until all sci sources are removed. table 5-26. system power plane plane controlled by description processor slp_s3# signal the slp_s3# signal can be used to cut the power to the processor completely. the dprslpvr support allows lowering the processor?s voltage during the c4 state. s3 hot : the new s3 hot state keeps more of the platform logic, including the ich6 core well, powered to reduce the cost of external power plane logic. slp_s3# is only used to remove power to the processor and to shut system clocks. this impacts the boar d design, but there is no specific ich6 bit or strap needed to indicate which option is selected. main slp_s3# signal (s3 cold ) or slp_s4# signal (s3 hot ) s3 cold : when slp_s3# goes active, power can be shut off to any circuit not required to wake the system from the s3 state. since the s3 state requires that the memory context be pr eserved, power must be retained to the main memory. the processor, devices on the pci bus , lpc i/f, and graphics will typically be shut off when the main power plane is shut, although there may be small subsections powered. s3 hot : slp_s4# is used to cut the main power well, rather than using slp_s3#. this impacts the board design, but there is no specific ich6 bit or strap needed to indicate which option is selected. memory slp_s4# signal slp_s5# signal when the slp_s4# goes active, power c an be shut off to any circuit not required to wake the system from t he s4. since the memory context does not need to be preserved in the s4 state, the power to the memory can also be shut down. when slp_s5# goes active, power can be shut to any circuit not required to wake the system from the s5 state. since the memory context does not need to be preserved in the s5 state, the power to the memory can also be shut. device[n] gpio individual subsystems may have their own power plane. for example, gpio signals may be used to control the power to disk drives, audio amplifiers, or the display screen.
154 intel ? i/o controller hub 6 (i ch6) family datasheet functional description table 5-27 shows which events can cause an smi# an d sci. note that some events can be programmed to cause either an sm i# or sci. the usage of the even t for sci (instead of smi#) is typically associated with an acpi-based system. each smi# or sci source has a corresponding enable and status bit. table 5-27. causes of smi# and sci (sheet 1 of 2) cause 1-5 sci smi additional enables where reported pme# yes yes pme_en=1 pme_sts pme_b0 (internal ehci controller) yes yes pme_b0_en=1 pme_b0_sts pci express* pme messages yes yes pci_exp_en=1 (not enabled for smi) pci_exp_sts pci express hot plug message yes yes hot_plug_en=1 (not enabled for smi) hot_plug_sts power button press yes yes pwrbtn_en=1 pwrbtn_sts power button override (note 6) yes no none prbtnor_sts rtc alarm yes yes rtc_en=1 rtc_sts ring indicate yes yes ri_en=1 ri_sts ac ?97 wakes yes yes ac97_en=1 ac97_sts usb#1 wakes yes yes usb1_en=1 usb1_sts usb#2 wakes yes yes usb2_en=1 usb2_sts usb#3 wakes yes yes usb3_en=1 usb3_sts usb#4 wakes yes yes usb4_en=1 usb4_sts thrm# pin active yes yes thrm_en=1 thrm_sts acpi timer overflow (2.34 sec.) yes yes tmrof_en=1 tmrof_sts any gpi 7 yes yes gpi[x]_route=10 (sci) gpi[x]_route=01 (smi) gpe0[x]_en=1 gpi[x]_sts gpe0_sts tco sci logic yes no tcosci_en=1 tcosci_sts tco sci message from (g)mch yes no none mchsci_sts tco smi logic no yes tco_en=1 tco_sts tco smi ? year 2000 rollover no yes none newcentury_sts tco smi ? tco timerout no yes none timeout tco smi ? os writes to tco_dat_in register no yes none os_tco_smi tco smi ? message from (g)mch no yes none mchsmi_sts tco smi ? nmi occurred (and nmis mapped to smi) no yes nmi2smi_en=1 nmi2smi_sts tco smi ? intruder# signal goes active no yes intrd_sel=10 intrd_det tco smi ? change of the bioswp bit from 0 to 1 no yes bld=1 bioswr_sts tco smi ? write attempted to bios no yes bioswp=1 bioswr_sts
intel ? i/o controller hub 6 (ich6) family datasheet 155 functional description notes: 1. sci_en must be 1 to enable sci. sci_en must be 0 to enable smi. 2. sci can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in apic mode). 3. gbl_smi_en must be 1 to enable smi. 4. eos must be written to 1 to re-enable smi for the next 1. 5. ich6 must have smi# fully enabled when ich6 is also enabled to trap cycles. if smi# is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. when a power button override first occurs, the system will transition immediately to s5. the sci will only occur after the next wake to s0 if the residual st atus bit (prbtnor_sts) is not cleared prior to setting sci_en. 7. only gpi[15:0] may generate an smi# or sci. 5.14.4.1 pci express* sci pci express ports and the (g)mch (via dmi) have the ability to cause pme using messages. when a pme message is received, ich6 will set the pci_exp_sts bit. if the pci_exp_en bit is also set, the ich6 can cause an sci via the gpe1_sts register. 5.14.4.2 pci express* hot-plug pci express has a hot-plug mechanism and is capable of generating a sci via the gpe1 register. it is also capable of generating an smi. however, it is not capable of generating a wake event. bios_rls written to yes no gbl_en=1 gbl_sts gbl_rls written to no yes bios_en=1 bios_sts write to b2h register no yes apmc_en = 1 apm_sts periodic timer expires no yes periodic_en=1 periodic_sts 64 ms timer expires no yes swsmi_tmr_en=1 swsmi_tmr_sts enhanced usb legacy support event no yes legacy_usb2_en = 1 legacy_usb2_sts enhanced usb intel specific event no yes intel_usb2_en = 1 intel_usb2_sts uhci usb legacy logic no yes legacy_usb_en=1 legacy_usb_sts serial irq smi reported no yes none serirq_smi_sts device monitors match address in its range no yes none devmon_sts, devact_sts smbus host controller no yes smb_smi_en host controller enabled smbus host status reg. smbus slave smi message no yes none smbus_smi_sts smbus smbalert# signal active no yes none smbus_smi_sts smbus host notify message received no yes host_notify_intren smbus_smi_sts host_notify_sts (mobile only) batlow# assertio n yes yes batlow_en=1. batlow_sts access microcontroller 62h/66h no yes mcsmi_en mcsmi_sts slp_en bit written to 1 no yes smi_on_slp_en=1 smi_on_slp_en_sts table 5-27. causes of smi# and sci (sheet 2 of 2) cause 1-5 sci smi additional enables where reported
156 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.5 dynamic process or clock control the ich6 has extensive control for dynamically starting and stopping system clocks. the clock control is used for transitions among the various s0/cx states, and processor th rottling. each dynamic clock control method is described in this section. the various sleep states may also perform types of non-dynamic clock control. the ich6 supports the acpi c0 and c1 states (in desktop) or c0, c1, c2, c3 and c4 (in mobile) states. the dynamic processor clock control is handled using the following signals: ? stpclk#: used to halt pro cessor instruction stream. ? (mobile only) stp_cpu#: used to stop processor?s clock ? (mobile only) cpuslp#: asserted prior to stp_cpu# (in stop grant mode) ? (mobile only) dpslp# used to fo rce deeper sleep for processor. ? (mobile only) dprslpvr: used to lo wer voltage of vrm during c4 state. ? (mobile only) dprstp#: used to lo wer voltage of vrm during c4 state the c1 state is entered based on the pro cessor performing an auto halt instruction. (mobile only) the c2 state is entered based on th e processor reading the level 2 register in the ich6. it can also be entered from c3 or c4 states if bus masters require snoops and the pume bit (d31:f0: offset a9h: bit 3) is set. (mobile only) the c3 state is entered based on th e processor reading the level 3 register in the ich6 and when the c4on c3_en bit is clear (d31:f0:offset a0:bit 7). this state can also be entered after a temporary return to c2 from a prior c3 or c4 state. (mobile only) the c4 state is entered based on th e processor reading the level 4 register in the ich6, or by reading the level 3 register when the c4onc3_en bit is set. this state can also be entered after a temporary return to c2 from a prior c4 state. a c1 state in desktop or a c1, c2, c3 or c4 state in mobile ends du e to a break event. based on the break event, the ich6 return s the system to c0 state. (mobile only) table 5-28 lists the possible break events from c2, c3 or c4. the break events from c1 are indicated in the processor?s datasheet. table 5-28. break events (mobile only) (sheet 1 of 2) event breaks from comment any unmasked interrupt goes active c2, c3, c4 irq[0:15] when using the 8259s, irq[0:23] for i/o apic. since sci is an interru pt, any sci will also be a break event. any internal event that cause an nmi or smi# c2, c3, c4 many possible sources
intel ? i/o controller hub 6 (ich6) family datasheet 157 functional description 5.14.5.1 transition rules among s0/cx and throttling states the following priority rules and assumptions apply among the various s0/cx and throttling states: ? entry to any s0/cx state is mutually exclusive w ith entry to any s1?s5 state. this is because the processor can only perform one register acces s at a time and sleep states have higher priority than thermal throttling. ? when the slp_en bit is set (system going to a s1 - s5 sleep st ate), the thtl_en and force_thtl bits can be internally treated as being disabled (no throttling while going to sleep state). ? (mobile only) if the thtl_en or force_thtl bi ts are set, and a level 2, level 3 or level 4 read then occurs, the system should immediately go and stay in a c2, c3 or c4 state until a break event occurs. a level 2, level 3 or level 4 read has higher priority than the software initiated throttling. ? (mobile only) after an exit from a c2, c3 or c4 state (due to a break event), and if the thtl_en or force_thtl bits are still set the system will continue to throttle stpclk#. depending on the time of break event, the first transition on stpclk# active can be delayed by up to one thrm period (1024 pci clocks = 30.72 s). ? the host controller must post stop-grant cycles in such a way that the processor gets an indication of the end of the sp ecial cycle prior to the ich6 observing the stop-grant cycle. this ensures that the stpclk# signals stays activ e for a sufficient period after the processor observes the response phase. ? (mobile only) if in the c1 st ate and the stpclk# signal goes active, the processor will generate a stop-grant cycle, and the system sh ould go to the c2 stat e. when stpclk# goes inactive, it should return to the c1 state. 5.14.5.2 deferred c3/c4 (mobile only) due to the new dmi protocol, if there is any bus master activity (other than true isoch), then the c0 to c3 transition will pause at the c2 state. ic h6 will keep the processo r in a c2 state until: ? ich6 sees no bus master activity. ? a break event occurs. in this case, the ich6 will perform the c2 to c0 sequence. note that bus master traffic is not a break event in this case. any internal event that cause init# to go active c2, c3, c4 could be indicated by the keyboard controller via the rcin input signal. any bus master request (internal, external or dma, or bmbusy#) goes active and bm_rld=1 (d31:f0:offset pmbase+04h: bit 1) c3, c4 need to wake up processor so it can do snoops note: if the pume bit (d31:f0: offset a9h: bit 3) is set, then bus master activity wi ll not be treated as a break event. instead, there will be a return only to the c2 state. processor pending break event indication c2, c3, c4 only available if ferr# enabled for break event indication (see ferr# mux enable in gcs, chipset configuration registers:offset 3410h:bit 6) table 5-28. break events (mobile only) (sheet 2 of 2) event breaks from comment
158 intel ? i/o controller hub 6 (i ch6) family datasheet functional description to take advantage of the deferred c3/c4 mode, th e bm_sts_zero_en bit must be set. this will cause the bm_sts bit to read as 0 even if some bus master activity is present. if this is not done, then the software may avoid even attempting to go to the c3 or c4 state if it sees the bm_sts bit as 1. if the pume bit (d31:f0: offset a9h: bit 3) is 0, then the ich6 will treat bus master activity as a break event. when reaching the c2 state, if there is any bus master activity, the ich6 will return the processor to a c0 state. 5.14.5.3 popup (auto c3/c4 to c2) (mobile only) when the pume bit (d31:f0: offset a9h: bit 3) is set, the ich6 enable s a mode of operation where standard (non-isoch) bus master activity will not be treated as a full break event from the c3 or c4 states. instead, these will be treated merely as bus master even ts and return the platform to a c2 state, and thus allow snoops to be performed. after returning to the c2 state, the bus master cy cles will be sent to the (g)mch, even if the arb_dis bit is set. 5.14.5.4 popdown (auto c2 to c3/c4) (mobile only) after returning to the c2 state from c3/c4, it the pdme bit (d31:f0: offset a9h: bit 4) is set, the platform can return to a c3 or c4 state (depending on where it was prior to going back up to c2). this behaves similar to the deferred c3/c4 transi tion, and will keep the pr ocessor in a c2 state until: ? bus masters are no longer active. ? a break event occurs. note that bus master traffic is not a break event in this case. 5.14.6 dynamic pci clock control (mobile only) the pci clock can be dynamically controlled independent of any other low-power state. this control is accomplished using the clkrun# protocol as described in the pci mobile design guide, and is transparent to software. the dynamic pci clock control is handled using the following signals: ? clkrun#: used by pci and lpc peripherals to request the system pci clock to run ? stp_pci#: used to stop the system pci clock note: the 33 mhz clock to the ich6 is ?free-running? and is not affected by the stp_pci# signal. 5.14.6.1 conditions for ch ecking the pci clock when there is a lack of pci activity the ich6 has the capability to stop the pci clocks to conserve power. ?pci activity? is defined as any activity that would require the pci clock to be running. any of the following conditions will indicate that it is not okay to stop the pci clock: ? cycles on pci or lpc ? cycles of any internal device that would need to go on the pci bus ? serirq activity
intel ? i/o controller hub 6 (ich6) family datasheet 159 functional description behavioral description ? when there is a lack of activity (as defined above) for 29 pci clocks, the ich6 de-asserts (drive high) clkrun# for 1 clock and then tri-states the signal. 5.14.6.2 conditions for main taining the pci clock pci masters or lpc devices that wish to maintain the pci clock running will observe the clkrun# signal de-asserted, and then must re -assert if (drive it low) within 3 clocks. ? when the ich6 has tri-stated the clkrun# sign al after de-asserting it, the ich6 then checks to see if the signal has been re-asserted (externally). ? after observing the clkrun# signal asserted for 1 clock, the ich6 agai n starts asserting the signal. ? if an internal device needs the pci bus, the ich6 asserts the clkrun# signal. 5.14.6.3 conditions for stopping the pci clock ? if no device re-asserts clkrun# once it has been de-asserted fo r at least 6 clocks, the ich6 stops the pci clock by asserting the stp_ pci# signal to the clock synthesizer. 5.14.6.4 conditions for re-s tarting the pci clock ? a peripheral asserts clkrun # to indicate that it needs the pci clock re-started. ? when the ich6 observes the clkrun# signal a sserted for 1 (free running) clock, the ich6 de-asserts the stp_pci# signal to the clock sy nthesizer within 4 (free running) clocks. ? observing the clkrun# signal asserted externally for 1 (free running) clock, the ich6 again starts driving clkrun# asserted. if an internal source requests the clock to be re-started, the ich6 re-asserts clkrun#, and simultaneously de-asserts the stp_pci# signal. 5.14.6.5 lpc devices and clkrun# if an lpc device (of any type) needs the 33 mhz pc i clock, such as for lpc dma or lpc serial interrupt, then it can assert clkrun#. note th at lpc devices running dma or bus master cycles will not need to assert clkrun#, sin ce the ich6 asserts it on their behalf. the ldrq# inputs are ignored by the ich6 when the pci clock is stopped to the lpc devices in order to avoid misinterpreting the request. the ich6 assumes that only one more rising pci clock edge occurs at the lpc device after the asser tion of stp_pci#. upon de-assertion of stp_pci#, the ich6 assumes that the lpc de vice receives its first clock risi ng edge corresponding to the ich6?s second pci clock rising edge after the de-assertion.
160 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.7 sleep states 5.14.7.1 sleep state overview the ich6 directly supports diff erent sleep states (s1?s5), which are entered by setting the slp_en bit, or due to a power button press. th e entry to the sleep states are based on several assumptions: ? entry to a cx state is mutually exclusive with entry to a sleep state. this is because the processor can only perform one re gister access at a time. a request to sleep always has higher priority than throttling. ? prior to setting the slp_en bit, the software turns off processor-controlled throttling. note that thermal throttling cannot be disabled, but setting the slp_en bit disables thermal throttling (since s1?s5 sleep state has higher priority). ? the g3 state cannot be entered via any soft ware mechanism. the g3 state indicates a complete loss of power. 5.14.7.2 initiating sleep state sleep states (s1?s5) are initiated by: ? masking interrupts, turning off all bus master enable bits, setting the desired type in the slp_typ field, and then setting th e slp_en bit. the hardware then attempts to gracefully put the system into the corresponding sleep state. ? pressing the pwrbtn# signal for more than 4 seconds to cause a power button override event. in this case the transition to the s5 state is less graceful , since there are no dependencies on observing stop-grant cycles from the processor or on clocks other than the rtc clock. 5.14.7.3 exiting sleep states sleep states (s1?s5) are exited based on wake even ts. the wake events forces the system to a full on state (s0), although some non-critical subsystems might still be shut off and have to be brought back manually. for example, the hard disk may be shut off during a sleep state, and have to be enabled via a gpio pin before it can be used. upon exit from the ich6-controlled sleep states, the wak_sts bit is set. the possible causes of wake events (and their restrictions) are shown in table 5-30 . note: (mobile only) if the batlow# sign al is asserted, ich6 does not attempt to wake from an s1?s5 state, even if the power button is pressed. this prevents the syst em from waking when the battery power is insufficient to wake the system. wake events that occur while batlow# is asserted are latched by the ich6, and the system wakes after batlow# is de-asserted. table 5-29. sleep types sleep type comment s1 intel ? ich6 asserts the stpclk# signal. it also has the option to assert cpuslp# signal. this lowers the processor?s power consumption. no snooping is possible in this state. s3 ich6 asserts slp_s3#. the slp_s3# signal controls the power to non-critical circuits. power is only retained to devices needed to wake from this sleeping state, as well as to the memory. s4 ich6 asserts slp_s3# and slp_s4#. the slp_s4 # signal shuts off the power to the memory subsystem. only devices needed to wake from this state should be powered. s5 same power state as s4. ich6 asserts slp_s3#, slp_s4# and slp_s5#.
intel ? i/o controller hub 6 (ich6) family datasheet 161 functional description notes: 1. if in the s5 state due to a powerbutton override or thrmtrip#, the possible wake events are due to power button, hard reset without cycling (see command type 3 in table 5-52 ), and hard reset system (see command type 4 in table 5-52 ). 2. when the wake# pin is active and the pci express dev ice is enabled to wake the system, the ich6 will wake the platform. 3. this is a wake event from s5 only if the sleep st ate was entered by setting the slp_en and slp_typ bits via software, or if there is a power failure. it is important to understand that the various gpis have different levels of functionality when used as wake events. the gpis that reside in the core power well can only gene rate wake events from sleep states where the core well is powered. table 5-31 summarizes the use of gpis as wake events. the latency to exit the various sl eep states varies greatly and is heavily dependent on power supply design, so much so that the exit latenc ies due to the ich6 are insignificant. table 5-30. causes of wake events cause 1,2 states can wake from how enabled rtc alarm s1 ? s5 3 set rtc_en bit in pm1_en register power button s1 ? s5 always enabled as wake event gpi[0:15] s1 ? s5 3 gpe0_en register note: gpis that are in the core well are not capable of waking the system from sleep states where the core well is not powered. classic usb s1 ? s5 set usb1_en, usb 2_en, usb3_en, and usb4_en bits in gpe0_en register lan s1 ? s5 will use pme#. wake enable set with lan logic. ri# s1 ? s5 3 set ri_en bit in gpe0_en register ac ?97 / intel high definition audio s1 ? s5 set ac97_en bit in gpe0_en register primary pme# s1 ? s5 3 pme_b0_en bit in gpe0_en register secondary pme# s1 ? s5 set pme_en bit in gpe0_en register. pci_exp_wake# s1?s5 pci_exp_wake bit (note 3) pci_exp pme message s1 must use the pci express* wake# pi n rather than messages for wake from s3,s4, or s5. smbalert# s1 ? s5 always enabled as wake event smbus slave message s1 ? s5 wake/smi# command always enabled as a wake event. note: smbus slave message can wake the system from s1?s5, as well as from s5 due to power button override. smbus host notify message received s1 ? s5 host_notify_wken bit smbus sl ave command register. reported in the smb_wak_sts bit in the gpeo_sts register. table 5-31. gpi wake events gpi power well wake from notes gpi[12, 7:0] core s1 acpi compliant gpi[15:13,11:8] resume s1?s5 acpi compliant
162 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.7.4 pci express* wake# si gnal and pme event message pci express ports can wake the pl atform from any sleep state (s1, s3, s4, or s5) using the wake# pin. wake# is treated as a wake event, but doe s not cause any bits to go active in the gpe_sts register. pci express ports and the (g)mch (via dmi) ha ve the ability to cause pme using messages. when a pme message is received, ic h6 will set the pci_exp_sts bit. 5.14.7.5 sx-g3-sx, ha ndling power failures depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. the after_g3 bit provides the ability to prog ram whether or not the system should boot once power returns after a power loss even t. if the policy is to not boot, the system remains in an s5 state (unless previously in s4). there are only three poss ible events that will wake the system after a power failure. 1. pwrbtn#: pwrbtn# is always enabled as a wa ke event. when rsmrst# is low (g3 state), the pwrbtn_sts bit is reset. when the ich6 exits g3 after power returns (rsmrst# goes high), the pwrbtn# signal is already high (because v cc -standby goes high before rsmrst# goes high) and the pwrbtn_sts bit is 0. 2. ri#: ri# does not have an internal pull-up. therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. if this signal goes low (active), when power returns the ri_sts bit is set and the system interprets that as a wake event. 3. rtc alarm: the rtc_en bit is in the rtc well and is preserved after a power loss. like pwrbtn_sts the rtc_sts bit is cl eared when rsmrst# goes low. the ich6 monitors both pwrok and rsmrst# to detect for power failures. if pwrok goes low, the pwrok_flr bit is set. if rsmrst# goes low, pwr_flr is set. note: although pme_en is in the rtc well, this signal cannot wake the system after a power loss. pme_en is cleared by rtcrst#, an d pme_sts is cleared by rsmrst#. table 5-32. transitions due to power failure state at power failure afterg3_en bit transition when power returns s0, s1, s3 1 0 s5 s0 s4 1 0 s4 s0 s5 1 0 s5 s0
intel ? i/o controller hub 6 (ich6) family datasheet 163 functional description 5.14.8 thermal management the ich6 has mechanisms to assist with managing thermal problems in the system. 5.14.8.1 thrm# signal the thrm# signal is used as a status input for a thermal sensor. based on the thrm# signal going active, the ich6 generates an smi# or sci (depending on sci_en). if the thrm_pol bit is set low, when the thrm# signal goes low, the thrm_sts bit will be set. this is an indicator that the thermal threshold has b een exceeded. if the thrm_en bit is set, then when thrm_sts goes active, either an smi# or sci will be ge nerated (depending on the sci_en bit being set). the power management software (bios or acpi) can then take measures to start reducing the temperature. examples includ e shutting off unwanted subsyste ms, or halting the processor. by setting the thrm_pol bit to high, another smi# or sci can optionally be generated when the thrm# signal goes back high. this allows the software (bios or acpi) to turn off the cooling methods. note: thrm# assertion does not cause a tco event message in s3 or s4. the level of the signal is not reported in the heartbeat message. 5.14.8.2 processor initiated passive cooling this mode is initiated by software setting the thtl_en or thtl_dty bits. software sets the thtl_dty bits to select throttle ratio and thtl_en bit to enable the throttling. throttling results in stpclk# active for a minimum time of 12.5% and a maximum of 87.5%. the period is 1024 pci clocks. thus, the stpclk# signal can be active for as little as 128 pci clocks or as much as 896 pci clocks. the actual slowdown (and cooling) of the processor depends on the instruction stream, because the pro cessor is allowed to finish the cu rrent instruction. furthermore, the ich6 waits for the stop-grant cycle before starting the count of the time the stpclk# signal is active. 5.14.8.3 thrm# override software bit the force_thtl bit allows the bios to force passive cooling, independent of the acpi software (that uses the thtl_en and thtl_dty bits). if this bit is set, the ich6 starts throttling using the ratio in the thrm_dty field. when this bit is cleared, the ich6 stops throttling, unless the thtl_en bit is set (indicating that acpi software is attempting throttling). if both the thtl_en and force_thtl bits are set, then the ich should use the duty cycle defined by the thrm_dty field, not the thtl_dty field. 5.14.8.4 active cooling active cooling involves fans. the gpio signals from the ich6 can be used to turn on/off a fan.
164 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.9 event input signals and their usage the ich6 has various input signals that trigger sp ecific events. this section describes those signals and how they should be used. 5.14.9.1 pwrbtn# (power button) the ich6 pwrbtn# signal operates as a ?f ixed power button? as described in the advanced configuration and power interface, version 2.0b. pwrbtn# signal has a 16 ms de-bounce on the input. the state transition desc riptions are included in table 5-33 . note that the transitions start as soon as the pwrbtn# is pressed (but after the debounce logic), and does not depend on when the power button is released. note: during the time that the slp_s4# signal is stretc hed for the minimum assertion width (if enabled), the power button is not a wake event. refer to power button override function section below for further detail. power button override function if pwrbtn# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the g2/s5 state, regard less of present state (s 0?s4), even if pwrok is not active. in this case, the transition to th e g2/s5 state should not depend on any particular response from the processor (e.g., a stop-grant cycle), nor any similar dependency from any other subsystem. the pwrbtn# status is readable to check if th e button is currently being pressed or has been released. the status is taken after the de-bo unce, and is readable via the pwrbtn_lvl bit. note: the 4-second pwrbtn# assertion should only be used if a system lock-up has occurred. the 4-second timer starts counting when the ich6 is in a s0 state. if the pwrbtn# signal is asserted and held active when the system is in a suspend state (s1?s5), th e assertion causes a wake event. once the system has resumed to the s0 state, the 4-second timer starts. note: during the time that the slp_s4# signal is stretc hed for the minimum assertion width (if enabled by d31:f0:a4h bit 3), the power button is not a wake event. as a result, it is conceivable that the user will press and continue to hold the powe r button waiting for the syst em to awake. since a 4-second press of the power button is already defined as an unconditional power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. once the power-cycle timer has expired, the power button awak es the system. once the minimum slp_s4# table 5-33. transitions due to power button present state event transition/action comment s0/cx pwrbtn# goes low smi# or sci generated (depending on sci_en) software typically initiates a sleep state s1?s5 pwrbtn# goes low wake event. transitions to s0 state standard wakeup g3 pwrbtn# pressed none no effect since no power not latched nor detected s0?s4 pwrbtn# held low for at least 4 consecutive seconds unconditional transition to s5 state no dependence on processor (e.g., stop-grant cycles) or any other subsystem
intel ? i/o controller hub 6 (ich6) family datasheet 165 functional description power cycle expires, the power bu tton must be pressed for another 4 to 5 seconds to create the override condition to s5. sleep button the advanced configuration and power interface, version 2.0b defines an optional sleep button. it differs from the power button in that it only is a request to go from s0 to s1?s4 (not s5). also, in an s5 state, the power button can wake the system, but the sleep button cannot. although the ich6 does not include a specific signa l designated as a sleep button, one of the gpio signals can be used to create a ?control method? sleep button. see the advanced configuration and power interface, version 2.0b for implementation details. 5.14.9.2 ri# (ring indicator) the ring indicator can cause a wake even t (if enabled) from the s1?s5 states. table 5-34 shows when the wake event is generated or ignored in diff erent states. if in the g0/s0/cx states, the ich6 generates an interrupt based on ri# active, and the interrupt will be set up as a break event. note: filtering/debounce on ri# will not be done in ich6. can be in modem or external. 5.14.9.3 pme# (pci power management event) the pme# signal comes from a pci device to reque st that the system be restarted. the pme# signal can generate an smi#, sci, or optionally a wake event. the event occurs when the pme# signal goes from high to low. no event is caused when it goes from low to high. there is also an internal pme_b0 bit. this is separate from the external pme# signal and can cause the same effect. 5.14.9.4 sys_reset# signal when the sys_reset# pin is detected as activ e after the 16 ms debounce logic, the ich6 attempts to perform a ?graceful? reset, by waiting up to 25 ms for the sm bus to go idle. if the smbus is idle when the pin is detected active, th e reset occurs immediately; otherwise, the counter starts. if at any point during the count the smbus goes idle the reset occurs. if, however, the counter expires and the smbus is still active, a reset is forced upon the system even though activity is still occurring. once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the sysreset# input remains asserted or not. it cannot occur again until sys_reset# has been detected inactive after the debounce logic, and the system is back to a full s0 state with pltrst# inactive. note that if bit 3 of the cf9h i/o register is set then sys_ reset# will result in a full power cycle reset. table 5-34. transitions due to ri# signal present state event ri_en event s0 ri# active x ignored s1?s5 ri# active 0 1 ignored wake event
166 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.9.5 thrmtrip# signal if thrmtrip# goes active, the processor is indicating an overheat condition, and the ich6 immediately transitions to an s5 state. however, since the processor has overheated, it does not respond to the ich6?s stpclk# pin with a stop gr ant special cycle. theref ore, the ich6 does not wait for one. immediately upon seeing thrmtrip# low, the ich6 initiates a transition to the s5 state, drive slp_s3#, slp_s4#, slp_s5# low, and set the cts bit. the transition looks like a power button override. it is extremely important th at when a thrmtrip# event occurs, the ich6 power down immediately without following the normal s0 -> s5 path. this path may be taken in parallel, but ich6 must immediately enter a po wer down state. it does this by driving slp_s3#, slp_s4#, and slp_s5# immediately after sampling thrmtrip# active. if the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the ich6, are no longer execu ting cycles properly . therefore, if thrmtrip# goes active, and the ich6 is relyi ng on state mach ine logic to perform the power down, the state machine may not be workin g, and the system will not power down. the ich6 follows this flow for thrmtrip#. 1. at boot (pltrst# low), thrmtrip# ignored. 2. after power-up (pltrst# high), if thrmtrip# sampled active, slp_s3#, slp_s4#, and slp_s5# assert, and normal sequ ence of sleep machine starts. 3. until sleep machine enters the s5 state, slp_s3#, slp_s4#, an d slp_s5# stay active, even if thrmtrip# is now inactive. this is the equivalent of ?latch ing? the thermal trip event. 4. if s5 state reached, go to step #1, otherwise stay here. if the ich6 never reaches s5, the ich6 does not reboot until power is cycled. during boot, thrmtrip# is ignored until slp_s3#, pwrok, vrmpwrgd/vgate, and pltrst# are all ?1?. during entry into a powered-dow n state (due to s3, s4, s5 entry, power cycle reset, etc.) thrmtrip# is ignored until eith er slp_s3# = 0, or pwrok = 0, or vrmpwrgd/ vgate = 0. note: a thermal trip event will: ? set the afterg3_en bit ? clear the pwrbtn_sts bit ? clear all the gpe0_en register bits ? clear the smb_wak_sts bit only if smb_sak_sts was se t due to smbus slave receiving message and not set due to smbalert 5.14.9.6 bmbusy# (mobile only) the bmbusy# signal is an input from a graphics co mponent to indicate if it is busy. if prior to going to the c3 state, the bmbusy# signal is act ive, then the bm_sts bit will be set. if after going to the c3 state, the bmbusy # signal goes back active, the ich6 will treat this as if one of the pci req# signals went active. this is treated as a break event.
intel ? i/o controller hub 6 (ich6) family datasheet 167 functional description 5.14.10 alt access mode before entering a low power state, several regi sters from powered down parts may need to be saved. in the majority of cases, this is not an issu e, as registers have read and write paths. however, several of the isa compatible re gisters are either read only or write only. to get data out of write-only registers, and to restore data into read-only registers, the ich6 implements an alt access mode. if the alt access mode is entered and exited after reading the registers of the ich6 timer (8254), the timer starts counting faster (13.5 ms). the following step s listed below can cause problems: 1. bios enters alt access mode for read ing the ich6 timer related registers. 2. bios exits alt access mode. 3. bios continues through the execution of other needed steps and passes control to the operating system. after getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. for example dos and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. operating systems (e.g., microsoft windows* 98, windows* 2000, and windows nt*) reprogram the system timer and therefore do not encounter this problem. for some other loss (e.g., microsoft ms-dos*) th e bios should restore the timer back to 54.6 ms before passing control to the op erating system. if the bios is entering alt access mode before entering the suspend state it is not necessary to restore the timer co ntents after the exit from alt access mode.
168 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.10.1 write only registers with read paths in alt access mode the registers described in table 5-35 have read paths in alt access mode. the access number field in the table indicates which register will be retu rned per access to that port. table 5-35. write only registers with read paths in alt access mode (sheet 1 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data 00h 2 1 dma chan 0 base address low byte 40h 7 1 timer counter 0 status, bits [5:0] 2 dma chan 0 base address high byte 2 timer counter 0 base count low byte 01h 2 1 dma chan 0 base count low byte 3 timer counter 0 base count high byte 2 dma chan 0 base count high byte 4 timer counter 1 base count low byte 02h 2 1 dma chan 1 base address low byte 5 timer counter 1 base count high byte 2 dma chan 1 base address high byte 6 timer counter 2 base count low byte 03h 2 1 dma chan 1 base count low byte 7 timer counter 2 base count high byte 2 dma chan 1 base count high byte 41h 1 tim er counter 1 status, bits [5:0] 04h 2 1 dma chan 2 base address low byte 42h 1 timer counter 2 status, bits [5:0] 2 dma chan 2 base address high byte 70h 1 bit 7 = nmi enable, bits [6:0] = rtc address 05h 2 1 dma chan 2 base count low byte c4h 2 1 dma chan 5 base address low byte 2 dma chan 2 base count high byte 2 dma chan 5 base address high byte 06h 2 1 dma chan 3 base address low byte c6h 2 1 dma chan 5 base count low byte 2 dma chan 3 base address high byte 2 dma chan 5 base count high byte 07h 2 1 dma chan 3 base count low byte c8h 2 1 dma chan 6 base address low byte 2 dma chan 3 base count high byte 2 dma chan 6 base address high byte 08h 6 1 dma chan 0?3 command 2 cah 2 1 dma chan 6 base count low byte 2 dma chan 0?3 request 2 dma chan 6 base count high byte 3 dma chan 0 mode: bits(1:0) = 00 cch 2 1 dma chan 7 base address low byte 4 dma chan 1 mode: bits(1:0) = 01 2 dma chan 7 base address high byte 5 dma chan 2 mode: bits(1:0) = 10 ceh 2 1 dma chan 7 base count low byte 6 dma chan 3 mode: bits(1:0) = 11. 2 dma chan 7 base count high byte
intel ? i/o controller hub 6 (ich6) family datasheet 169 functional description notes: 1. the ocw1 register must be read before entering alt access mode. 2. bits 5, 3, 1, and 0 return 0. 5.14.10.2 pic reserved bits many bits within the pic are reserved, and must have certain values written in order for the pic to operate properly. therefore, there is no need to return these values in alt access mode. when reading pic registers from 20h and a0h, the rese rved bits shall return the values listed in table 5-36 . 20h 12 1 pic icw2 of master controller d0h 6 1 dma chan 4?7 command 2 2 pic icw3 of master controller 2 dma chan 4?7 request 3 pic icw4 of master controller 3 dma chan 4 mode: bits(1:0) = 00 4 pic ocw1 of master controller 1 4 dma chan 5 mode: bits(1:0) = 01 5 pic ocw2 of master controller 5 dma chan 6 mode: bits(1:0) = 10 6 pic ocw3 of master controller 6 dma chan 7 mode: bits(1:0) = 11. 7 pic icw2 of slave controller 8 pic icw3 of slave controller 9 pic icw4 of slave controller 10 pic ocw1 of slave controller 1 11 pic ocw2 of slave controller 12 pic ocw3 of slave controller table 5-35. write only registers with read paths in alt access mode (sheet 2 of 2) restore data restore data i/o addr # of rds access data i/o addr # of rds access data table 5-36. pic reserved bits return values pic reserved bits value returned icw2(2:0) 000 icw4(7:5) 000 icw4(3:2) 00 icw4(0) 0 ocw2(4:3) 00 ocw3(7) 0 ocw3(5) reflects bit 6 ocw3(4:3) 01
170 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.10.3 read only regist ers with write paths in alt access mode the registers described in table 5-37 have write paths to them in alt access mode. software restores these values after returning from a powe red down state. these registers must be handled special by software. when in normal mode, writing to the base address/count re gister also writes to the current address/count re gister. therefore, the base address/c ount must be written first, then the part is put into alt access mode and the cu rrent address/count re gister is written. 5.14.11 system power supplie s, planes, and signals 5.14.11.1 power plane contro l with slp_s3#, slp_s4# and slp_s5# the usage of slp_s3# and slp_s4# depends on whether the platform is configured for s3 hot and s3 cold . 5.14.11.1.1 s3 hot the slp_s3# output signal is used to cut power only to the processor and associated subsystems and to optionally stop system clocks. 5.14.11.1.2 s3 cold the slp_s3# output signal can be used to cut power to the system core supply, since it only goes active for the str state (typically mapped to acpi s3). power must be maintained to the ich6 resume well, and to any other circuits that need to generate wake signals from the str state. cutting power to the core may be done via the power supply, or by external fets to the motherboard. the slp_s4# or slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. the slp_s4# output signal is used to remove po wer to additional subsystems that are powered during slp_s3#. slp_s5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. cutting power to the memory may be done via the power supply, or by external fets to the motherboard. table 5-37. register write accesses in alt access mode i/o address register write value 08h dma status register for channels 0?3. d0h dma status register for channels 4?7.
intel ? i/o controller hub 6 (ich6) family datasheet 171 functional description 5.14.11.2 slp_s4# and susp end-to-ram sequencing the system memory suspend voltage regulator is controlled by the glue logic. the slp_s4# signal should be used to remove power to system memo ry rather than the slp_s5# signal. the slp_s4# logic in the ich6 provides a mechanism to fully cy cle the power to the dram and/or detect if the power is not cycled for a minimum time. note: to use the minimum dram power- down feature that is enabled by the slp_s4# assertion stretch enable bit (d31:f0:a4h bit 3), the dram power must be controlled by the slp_s4# signal. 5.14.11.3 pwrok signal the pwrok input should go active based on the core supply voltages becoming valid. pwrok should go active no sooner than 100 ms after vcc3_3 and vcc1_5 have reached their nominal values. note: 1. sysreset# is recommended for implementing the system reset button. this saves external logic that is needed if the pwrok input is used . additionally, it allows for better handling of the smbus and processor resets, and avoids improperly reporting power failures. 2. if the pwrok input is used to implement the system reset button, the ich6 does not provide any mechanism to limit the amount of time that the processor is held in reset. the platform must externally guarantee that ma ximum reset assertion specs are met. 3. if a design has an active-low reset button electri cally and?d with the pwrok signal from the power supply and the processor?s voltage regulator module the ich6 pwrok_flr bit will be set. the ich6 treats this internally as if the rsmrst# signal had gone active. however, it is not treated as a full power failure. if pwr ok goes inactive and then active (but rsmrst# stays high), then the ich6 reboots (regardle ss of the state of the afterg3 bit). if the rsmrst# signal also goes low before pwrok goes high, then this is a full power failure, and the reboot policy is controlled by the afterg3 bit. 4. pwrok and rsmrst# are sampled using the rtc clock. therefore, low times that are less than one rtc clock period may not be detected by the ich6. 5. in the case of true pwrok failure, pw rok goes low first before the vrmpwrgd. 5.14.11.4 cpupwrgd signal this signal is connected to the processor?s vrm via the vrmpwrgd signal and is internally and?d with the pwrok signal that co mes from the system power supply. 5.14.11.5 vrmpwrgd signal vrmpwrgd is an input from the regulator indicatin g that all of the outputs from the regulator are on and within specification. vrmpwrgd may go active before or after the pwrok from the main power supply. ich6 has no dependency on the order in which these two signals go active or inactive. 5.14.11.6 batlow# (battery low) (mobile only) the batlow# input can inhibit waking from s3, s4, and s5 states if there is not sufficient power. it also causes an smi# if the sy stem is already in an s0 state.
172 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.14.11.7 controlling leakage and power consumption during low-power states to control leakage in the system, various signals tri-state or go low during some low-power states. general principles: ? all signals going to powered down planes (either internally or externally) must be either tri-stated or driven low. ? signals with pull-up resistors should not be lo w during low-power states. this is to avoid the power consumed in the pull-up resistor. ? buses should be halted (and held) in a known state to avoid a floating input (perhaps to some other device). floating inputs can cause extra power consumption. based on the above principles, the following measures are taken: ? during s3 (str), all signals a ttached to powered down planes are tri-stated or driven low. 5.14.12 clock generators the clock generator is expected to provide the frequencies shown in table 5-38 . table 5-38. intel ? ich6 clock inputs clock domain frequency source usage sata_clk 100 mhz differential main clock generator used by sata controller. stopped in s3 ~ s5 based on slp_s3# assertion. dmi_clk 100 mhz differential main clock generator used by dmi and pci express*. stopped in s3 ~ s5 based on slp_s3# assertion. pciclk 33 mhz main clock generator desktop: free-running pci clock to ich6. stopped in s3 ~ s5 based on slp_s3# assertion. mobile: free-running (not affected by stp_pci# pci clock to ich6. this is not the system pc i clock. this clock must keep running in s0 while the system pci clock may stop based on clkrun# protocol. stopped in s3 ~ s5 based on slp_s3# assertion. clk48 48.000 mhz main clock generator used by usb controllers and intel high definition audio controller. stopped in s3 ~ s5 based on slp_s3# assertion. clk14 14.318 mhz main clock generator used by acpi timers. stopped in s3 ~ s5 based on slp_s3# assertion. acz_bit_clk 12.288 mhz ac ?97 codec ac-link. control policy is determined by the clock source. note: becomes clock output when intel high definition audio is enabled. lan_clk 0.8 to 50 mhz lan connect lan connect interface. contro l policy is determined by the clock source.
intel ? i/o controller hub 6 (ich6) family datasheet 173 functional description 5.14.12.1 clock control signals from intel ? ich6 to clock synthesizer (mobile only) the clock generator is assumed to have direct connect from the following ich6 signals: ? stp_cpu# stops processor cl ocks in c3 and c4 states ? stp_pci# stops system pci clocks (not the ich6 free-running 33 mhz clock) due to clkrun# protocol ? slp_s3# expected to drive clock chip pwrdown (through inverter), to stop clocks in s3 hot and on the way to s3 cold to s5. 5.14.13 legacy power manageme nt theory of operation instead of relying on acpi software, legacy power management uses bios and various hardware mechanisms. the scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. however, the operating system is assumed to be at least apm enabled. wi thout apm calls, there is no quick way to know when the system is idle between keystrokes. the ich6 does not support burst modes. 5.14.13.1 apm power management (desktop only) the ich6 has a timer that, when enabled by th e 1min_en bit in the smi control and enable register, generates an smi# once per minute. th e smi handler can check for system activity by reading the devact_sts register. if none of the system bits are set, the smi handler can increment a software counter. when the counter reaches a sufficient number of consecutive minutes with no activity, the smi handler can th en put the system into a lower power state. if there is activity, various bits in the devact_sts register will be set. software clears the bits by writing a 1 to the bit position. the devact_sts register allows for monitoring various internal devices, or super i/o devices (sp, pp, fdc) on lpc or pci, keyboard controller accesses, or audio functions on lpc or pci. other pci activity can be monitored by checking the pci interrupts. 5.14.13.2 mobile apm power ma nagement (mobile only) in mobile systems, there are a dditional requirements associated with device power management. to handle this, the ich6 has specific smi# trap s available. the follow ing algorithm is used: 1. the periodic smi# timer checks if a device is idle for the require time. if so, it puts the device into a low-power state and sets the associated smi# trap. 2. when software (not the smi# handler) attempts to access the devi ce, a trap occurs (the cycle does not really go to the device and an smi# is generated). 3. the smi# handler turns on th e device and turns off the trap the smi# handler exits with an i/o restart. this allows the original software to continue.
174 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.15 system management (d31:f0) the ich6 provides various functions to make a system easier to manage and to lower the total cost of ownership (tco) of the system. in addition, ich6 provides integrated asf management support. features and functions can be augmente d via external a/d converters and gpio, as well as an external microcontroller. the following features and functions are supported by the ich6: ? processor present detection ? detects if processor fails to fetc h the first instruction after reset ? various error detection (such as e cc errors) indicated by host controller ? can generate smi#, sci, serr, nmi, or tco interrupt ? intruder detect input ? can generate tco interrupt or smi# when the system cover is removed ? intruder# allowed to go active in any power stat e, including g3 ? detection of bad firmware hub programming ? detects if data on first read is ffh (indicates unprogrammed firmware hub) ? ability to hide a pci device ? allows software to hide a pci device in term s of configuration space through the use of a device hide register (see section 7.1.56 ) ? integrated asf management support note: voltage id from the processor can be read via gpi signals. 5.15.1 theory of operation the system management functions are designed to allow the system to diagnose failing subsystems. the intent of this logic is that some of the system management functionality be provided without the aid of an external microcontroller. 5.15.1.1 detecting a system lockup when the processor is reset, it is expected to fetch its first instruction. if the processor fails to fetch the first instruction after reset, the tco timer times out twice and the ich6 asserts pltrst#. 5.15.1.2 handling an intruder the ich6 has an input signal, intruder#, that can be attached to a switch that is activated by the system?s case being open. this input has a two rtc clock debounce. if intruder# goes active (after the debouncer), this will set th e intrd_det bit in the tco_sts register. the intrd_sel bits in the tco_cnt register can enab le the ich6 to cause an smi# or interrupt. the bios or interrupt handler can then cause a tran sition to the s5 state by writing to the slp_en bit. the software can also directly r ead the status of the intruder# signal (high or low) by clearing and then reading the intrd_det bi t. this allows the signal to be used as a gpi if the intruder function is not required.
intel ? i/o controller hub 6 (ich6) family datasheet 175 functional description if the intruder# signal goes inactive some poin t after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 wh en intruder# input signal goes inactive. note that this is slightly different than a classic stic ky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. note: the intrd_det bit resides in the ich6?s rtc well, and is set and cleared synchronously with the rtc clock. thus, when software attempts to clear intrd_det (by writing a 1 to the bit location) there may be as much as two rtc clocks (about 65 s) delay before the bit is actually cleared. also, the intruder# signal should be as serted for a minimum of 1 ms to guarantee that the intrd_det bit will be set. note: if the intruder# signal is still active when software attempts to clear the intrd_det bit, the bit remains set and the smi is generated agai n immediately. the smi handler can clear the intrd_sel bits to avoid further smis. however, if the intruder# signal goes inactive and then active again, there will not be further smis , since the intrd_sel bits would select that no smi# be generated. 5.15.1.3 detecting improper firmware hub programming the ich6 can detect the case wher e the firmware hub is not programmed. this results in the first instruction fetched to have a value of ffh. if th is occurs, the ich6 sets the bad_bios bit, which can then be reported via the heartbeat and even t reporting using an external, alert on lan* enabled lan controller (see section 5.15.2 ). 5.15.2 heartbeat and even t reporting via smbus the ich6 integrated lan controller supports asf heartbeat and event reporting functionality when used with the 82562em or 82562ex platform lan connect component. this allows the integrated lan controller to repo rt messages to a network management console without the aid of the system processor. this is crucial in cases where the proce ssor is malfunctioning or cannot function due to being in a low-power state. all heartbeat and event messages are sent on the sm bus interface. this allows an external lan controller to act upon these messages if th e internal lan controller is not used. the basic scheme is for the ich6 integrated lan controller to se nd a prepared ethernet message to a network management console. the prepared message is stored in the non-volatile eeprom that is connected to the ich6. messages are sent by the lan controller either b ecause a specific event has occurred, or they are sent periodically (also known as a heartbeat). the event and hear tbeat messages have the exact same format. the event messages are sent based on events occurring. th e heartbeat messages are sent every 30 to 32 seconds. wh en an event occurs, the ich6 sends a new message and increments the seq[3:0] field. for heartbeat message s, the sequence number does not increment.
176 intel ? i/o controller hub 6 (i ch6) family datasheet functional description the following rules/steps apply if the system is in a g0 state and the policy is for the ich6 to reboot the system after a hardware lockup: 1. on detecting the lockup, the second_to_sts bit is set. the ich6 may send up to 1 event message to the lan controller. the ich6 then attempts to reboot the processor. 2. if the reboot at step 1 is successful then the bios s hould clear the se cond_to_sts bit. this prevents any further heartbeats from being sent. the bios may then perform addition recovery/boot steps. (see note 2, below.) 3. if the reboot attempt in step 1 is not successful , the timer will timeout a th ird time. at this point the system has locked up and was unsuccessful in rebooting. the ich6 does not attempt to automatically reboot again. the ich6 starts sending a mess age every heartbeat period (30?32 seconds). the heartbeats continue until some external intervention occurs (reset, power failure, etc.). 4. after step 3 (unsuccessful reboot after th ird timeout), if the user does a power button override, the system goes to an s5 state. the ich6 continues sendi ng the messages every heartbeat period. 5. after step 4 (power button override after unsu ccessful reboot) if the user presses the power button again, the system should wake to an s0 state and the processor should start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the ich6 continues sending messages every heartbeat period until the bi os clears the second_to _sts bit. (see note 2) 7. if step 5 (power button press) is unsuccessf ul in waking the system , the ich6 continues sending a message every heartbeat period. the ic h6 does not attempt to automatically reboot again. the ich6 starts sending a message ev ery heartbeat period (30?32 seconds). the heartbeats continue until some external intervention occurs (r eset, power failure, etc.). (see note 3) 8. after step 3 (unsuccessful reboot after third ti meout), if a reset is attempted (using a button that pulses pwrok low or via th e message on the smbus slave i/f), the ich6 attempts to reset the system. 9. after step 8 (reset attempt) if the reset is successful, the bios is run. the ich6 continues sending a message every heartbeat period until the bios clears the second_to_sts bit. (see note 2) 10. after step 8 (reset attempt), if the reset is unsuccessful, the ich6 continues sending a message every heartbeat period. the ich6 does not attemp t to reboot the system again without external intervention. (see note 3) the following rules/steps apply if the system is in a g0 state and the policy is for the ich6 to not reboot the system after a hardware lockup. 1. on detecting the lockup the second_to_sts bit is set. the ich6 sends a message with the watchdog (wd) event status bit set (and any other bits that must also be set). this message is sent as soon as the lockup is detected, and is sent with the next (incremented) sequence number. 2. after step 1, the ich6 sends a message every heartbeat period until some external intervention occurs. 3. rules/steps 4?10 apply if no user interventi on (resets, power button presses, smbus reset messages) occur after a third tim eout of the watchdog timer. if the intervention occurs before the third timeout, then jump to rule/step 11. 4. after step 3 (third timeout), if the user does a power button override, the system goes to an s5 state. the ich6 continues send ing heartbeats at this point.
intel ? i/o controller hub 6 (ich6) family datasheet 177 functional description 5. after step 4 (power button override), if the user presses the power button again, the system should wake to an s0 state and the pr ocessor should start executing the bios. 6. if step 5 (power button press) is successful in waking the system, the ich6 continues sending heartbeats until the bios clears th e second_to_sts bit. (see note 2) 7. if step 5 (power button press) is unsuccessful in waking th e system, the ich6 continues sending heartbeats. the ich6 does not attempt to reboot the syst em again until some external intervention occurs (reset, powe r failure, etc.). (see note 3) 8. after step 3 (third timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave i/f), the ich6 attempts to reset the system. 9. if step 8 (reset attempt) is successful, the bios is run. the ich6 continues sending heartbeats until the bios clears the se cond_to_sts bit. (see note 2) 10. if step 8 (reset attempt), is unsuccessful, th e ich6 continues sendin g heartbeats. the ich6 does not attempt to reboot the system again without external intervention. note: a system that has locked up and can not be restarted with power button press is probably broken (bad power supply, short circuit on some bus, etc.) 11. this and the following rules/steps apply if the user intervention (power button press, reset, smbus message, etc.) occur prior to th e third timeout of the watchdog timer. 12. after step 1 (second timeout), if the user does a power button override, the system goes to an s5 state. the ich6 continues sending heartbeats at this point. 13. after step 12 (power button override), if the user presses the power button again, the system should wake to an s0 state and the pr ocessor should start executing the bios. 14. if step 13 (power button press) is successful in waking the system, the ich6 continues sending heartbeats until the bios clears th e second_to_sts bit. (see note 2) 15. if step 13 (power button press) is unsuccessful in waking the system, the ich6 continues sending heartbeats. the ich6 does not attempt to reboot the syst em again until some external intervention occurs (reset, powe r failure, etc.). (see note 3) 16. after step 1 (second timeout), if a reset is attempted (using a button that pulses pwrok low or via the message on the smbus slave i/f), the ich6 attempts to reset the system. 17. if step 16 (reset attempt) is successful, the bios is run. the ich6 continues sending heartbeats until the bios clears th e second_to_sts bit. (see note 2) 18. if step 16 (reset attempt), is unsuccessful, the ich6 continues sending heartbeats. the ich6 does not attempt to reboot the system again without external intervention. (see note 3) if the system is in a g1 (s1?s4) state, the ich6 sends a heartbeat message every 30?32 seconds. if an event occurs prior to the system being shutdo wn, the ich6 immediately sends an event message with the next incremented seque nce number. after the event mess age, the ich6 resumes sending heartbeat messages. note: notes for previous two numbered lists. 1. normally, the ich6 does not se nd heartbeat messages while in th e g0 state (except in the case of a lockup). however, if a hardware event (or heartbeat) occurs ju st as the system is transitioning into a g0 state, the hardware continues to send the message even though the system is in a g0 state (and th e status bits may indicate this). these messages are sent via the smbus. the ic h6 abides by the smbus rules associated with collision detection. it delays starting a message un til the bus is idle, and detects collisions. if a collision is detected the ich6 waits until the bus is idle, and tries again. 2. warning: it is important the bios clears the seco nd_to_sts bit, as the alerts interfere with the lan device driver from working properly. the alerts rese t part of the lan controller
178 intel ? i/o controller hub 6 (i ch6) family datasheet functional description and would prevent an operating system?s devi ce driver from sending or receiving some messages. 3. a system that has locked up and can not be restarted with power button press is assumed to have broken hardware (bad power supply, short circuit on some bus, etc.), and is beyond ich6?s recovery mechanisms. 4. a spurious alert could occu r in the following sequence: ? the processor has initiated an alert using the send_now bit ? during the alert, the thrm#, in truder# or gpi[11] changes state ? the system then goes to a non-s0 state. once the system transitions to th e non-s0 state, it may send a si ngle alert with an incremental sequence number. 5. an inaccurate alert message can be generated in the following scenario ? the system successfully boots afte r a second watchdog timeout occurs. ? pwrok goes low (typically due to a reset button press) or a power button override occurs (before the second _to_sts bit is cleared). ? an alert message indicating that the processor is missing or locked up is generated with a new sequence number. table 5-39 shows the data included in the alert on lan messages. table 5-39. heartbeat message data field comment cover tamper status 1 = this bit is set if the intruder detect bit is set (intrd_det). temp event status 1 = this bit is set if the intel ? ich6 therm# input signal is asserted. processor missing event status 1 = this bit is set if the processor failed to fetch its first instruction. tco timer event status 1 = this bit is set when the tco timer expires. software event status 1 = this bit is set when software writes a 1 to the send_now bit. unprogrammed firmware hub event status 1 = first bios fetch returned a value of ffh, indicating that the firmware hub has not yet been programmed (still erased). gpio status 1 = this bit is set when gpi[11] signal is high. 0 = this bit is cleared when gpi[11] signal is low. an event message is triggered on an transition of gpi[11]. seq[3:0] this is a sequence number. it initially is 0, and increments each time the ich6 sends a new message. upon reaching 1111, the sequence number rolls over to 0000. msb (seq3) sent first. system power state 00 = g0, 01 = g1, 10 = g2, 11 = pre-boot. msb sent first message1 will be the same as the message1 register. msb sent first. message2 will be the same as the message2 register. msb sent first. wdstatus will be the same as the wd status register. msb sent first.
intel ? i/o controller hub 6 (ich6) family datasheet 179 functional description 5.16 ide controller (d31:f1) the ich6 ide controller features on e sets of interface signals that can be enabled, tri-stated or driven low. the ide interfaces of the ich6 can support several types of data transfers: ? programmed i/o (pio): processor is in control of the data transfer. ? 8237 style dma: dma protocol that resembles the dma on the isa bus, although it does not use the 8237 in the ich6. this protocol off loads the processor from moving data. this allows higher transfer rate of up to 16 mb/s. ? ultra ata/33: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 33 mb/s. ? ultra ata/66: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 66 mb/s. ? ultra ata/100: dma protocol that redefines signals on the ide cable to allow both host and target throttling of data and transfer rates of up to 100 mb/s. 5.16.1 pio transfers the ich6 ide controller includes both compatible and fast timing modes. the fast timing modes can be enabled only for the ide data ports. all ot her transactions to the ide registers are run in single transaction mode with compatible timings. up to two ide devices may be attached to the id e connector (drive 0 and drive 1). the ide_timp and ide_tims registers permit different timing mo des to be programmed for drive 0 and drive 1 of the same connector. the ultra ata/33/ 66/100 synchronous dma timing modes can also be applied to each drive by programming the ide i/o configuration register and the synchronous dma control and timing registers. when a drive is enabled for synchrono us dma mode operation, the dma transfers are executed with the synchronous dma timings. the pio transfers are execu ted using compatible timings or fast timings if also enabled. 5.16.1.1 pio ide timing modes ide data port transaction latency consists of start up latency, cycle latency, and shutdown latency. startup latency is incurred when a pci master cycl e targeting the ide data port is decoded and the da[2:0] and csxx# lines are not set up. startup latency provides the setup time for the da[2:0] and csxx# lines prior to assertion of the read and write strobes (dior# and diow#). cycle latency consists of the i/o command strobe assertion length and recovery time. recovery time is provided so that trans actions may occur back-to-back on the ide interface (without incurring startup and shutdown latency) without violating minimum cycle periods for the ide interface. the command strobe asse rtion width for the enhanced ti ming mode is selected by the ide_tim register and may be set to 2, 3, 4, or 5 pci clocks. the recovery time is selected by the ide_tim register and may be set to 1, 2, 3, or 4 pci clocks.
180 intel ? i/o controller hub 6 (i ch6) family datasheet functional description if iordy is asserted when the initial sample point is reached, no wait-states are added to the command strobe assertion length. if iordy is ne gated when the initial sample point is reached, additional wait-states are added. since the rising edge of iordy must be synchronized, at least two additional pci clocks are added. shutdown latency is incurred after outstanding scheduled ide data port transactions (either a non-empty write post buffer or an outstanding read prefetch cycles) have completed and before other transactions can proceed. it provides hold time on the da[2:0] and csxx# lines with respect to the read and write strobes (dior# and diow#). shutdown latency is two pci clocks in duration. the ide timings for various transaction types are shown in table 5-40 . 5.16.1.2 iordy masking the iordy signal can be ignored and assumed assert ed at the first iordy sample point (isp) on a drive by drive basis via the idetim register. 5.16.1.3 pio 32-bit id e data port accesses a 32-bit pci transaction run to the ide data addr ess (01f0h primary) results in two back to back 16-bit transactions to the ide data port. the 32-bit data port feature is enabled for all timings, not just enhanced timing. for compatible timings, a shutdown and startup latency is incurred between the two, 16-bit halves of the ide transaction. this guarantees that the chip selects are de-asserted for at least two pci clocks between the two cycles. 5.16.1.4 pio ide data port prefetching and posting the ich6 can be programmed vi a the idetim registers to allow data to be posted to and prefetched from the ide data ports. data prefetching is initiated when a data port read occurs. the read prefetch eliminates latency to the ide data ports and allows them to be performed back to back for the highest possible pio data transfer rates. the first data port read of a sect or is called the demand read. subsequent data port reads from the sector are called pr efetch reads. the demand read and all prefetch reads must be of the same size (16 or 32 bits); softwa re must not mix 32-bit and 16-bit reads. data posting is performed for writes to the ide data ports. the transaction is completed on the pci bus after the data is received by the ich6. the ich6 then runs the ide cycle to transfer the data to the drive. if the ich6 write buffe r is non-empty and an unrelated (non-data or opposite channel) ide transaction occurs, that trans action will be stalled until all current data in the write buffer is transferred to the drive. only 16-bit buffer writes are supported. table 5-40. ide transaction timings (pci clocks) ide transaction type startup latency iordy sample point (isp) recovery time (rct) shutdown latency non-data port compatible 4 11 22 2 data port compatible 3 6 14 2 fast timing mode 2 2?5 1?4 2
intel ? i/o controller hub 6 (ich6) family datasheet 181 functional description 5.16.2 bus master function the ich6 can act as a pci bus master on behalf of an ide device. one pci bus master channel is provided for the ide connector. by performing th e ide data transfer as a pci bus master, the ich6 off-loads the processor and improves syst em performance in multitasking environments. both devices attached to the connector can be programmed for bus master transfers, but only one device can be active at a time. 5.16.2.1 physical regi on descriptor format the physical memory region to be transferred is described by a p hysical region descriptor (prd). the prds are stored sequentially in a descriptor table in memory . the data transfer proceeds until all regions described by the prds in the table have been transferred. descriptor tables must not cross a 64-kb boundary. each prd entry in the table is 8 bytes in length. the first 4 bytes specify the byte address of a physical memory region. this memory region must be dword-aligned and must not cross a 64-kb boundary. the next two bytes specify the size or transfer count of the region in bytes (64-kb li mit per region). a value of 0 in these two bytes indicates 64-kb (thus the minimum tr ansfer count is 1). if bit 7 (eot) of the last byte is a 1, it indicates that this is the final prd in the descri ptor table. bus master operation terminates when the last descriptor has been retired. when the bus master ide controller is reading data from the memory regions, bit 1 of the base address is masked and byte enables are asserted for all read transfer s. when writing data, bit 1 of the base address is not masked and if set, will cau se the lower word byte enables to be de-asserted for the first dword tr ansfer. the write to pci typically consis ts of a 32-byte cache line. if valid data ends prior to end of the cache line, the byte enables will be de-asserted for invalid data. the total sum of the byte counts in every prd of the descriptor table must be equal to or greater than the size of the disk transfer request. if greater than the disk tr ansfer request, the driver must terminate the bus master transact ion (by setting bit 0 in the bus master ide command register to 0) when the drive issues an inte rrupt to signal transfer completion. figure 5-7. physical region descriptor table entry eot reserved byte count [15:1] memory region physical base address [31:1] byte 3byte 2byte 1byte 0 memory region main memory o o
182 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.16.2.2 bus master ide timings the timing modes used for bus mast er ide transfers are identical to those for pio transfers. the dma timing enable only bits in ide timing register can be used to program fast timing mode for dma transactions only. this is useful for ide de vices whose dma transfer timings are faster than its pio transfer timings. the ide device dma reque st signal is sampled on the same pci clock that dior# or diow# is de-asser ted. if inactive, the dma acknowl edge signal is de-asserted on the next pci clock and no more transfers take place until dma reques t is asserted again. 5.16.2.3 interrupts the ich6 can generate interrupts based upon a signal coming from the pata device, or due to the completion of a prd with the ?i? bit set. the inte rrupt is edge triggered and active high. the pata host controller generates ideirq. when the ich6 ide controller is operating independently from the sata controller (d31:f2), ideirq will generate irq14. when operating in conjunction with the sata controller (combined mode), ide interrupts will still generate ideirq, but this may in turn generate either irq14 or irq15, depending upon the value of the map.mv (d31:f2:90h:bits 1:0) register. when in combined mode and the sata controller is em ulating the logical sec ondary channel (map.mv = 1h), the pata channel will emulate the logical pr imary channel and ideirq will generate irq14. conversely, if the sata controll er in combined mode is emulating the logical primary channel (map.mv=2h), ideirq will generate irq15. note: ide interrupts cannot be communicated through pci devices or the serial irq stream. 5.16.2.4 bus master ide operation to initiate a bus master transfer between memo ry and an ide device, the following steps are required: 1. software prepares a prd table in system me mory. the prd table must be dword-aligned and must not cross a 64-kb boundary. 2. software provides the starti ng address of the prd table by loading the prd table pointer register. the direction of the data transfer is specified by setting the read/write control bit. the interrupt bit and error bit in the status register are cleared. 3. software issues the appropriate dma transfer command to the disk device. 4. the bus master function is engaged by software writing a 1 to the start bit in the command register. the first entry in the prd table is fetc hed and loaded into two registers which are not visible by software, the current base and curr ent count registers. th ese registers hold the current value of the address and byte count loaded from the prd table. the value in these registers is only valid when there is an active command to an ide device. 5. once the prd is loaded internally, the ide device will receive a dma acknowledge. 6. the controller transfers data to/from memo ry responding to dma requests from the ide device. the ide device and the ho st controller may or may not throttle the transfer several times. when the last data transfer for a regi on has been completed on the ide interface, the next descriptor is fetched from the table. the descriptor contents are loaded into the current base and current count registers. 7. at the end of the transfer, th e ide device signals an interrupt. 8. in response to the interrupt, software resets the start/stop bit in the command register. it then reads the controller status follo wed by the drive status to determine if the transfer completed successfully.
intel ? i/o controller hub 6 (ich6) family datasheet 183 functional description the last prd in a table has the end of list (e ol) bit set. the pci bus master data transfers terminate when the physical region described by the last prd in the table has been completely transferred. the active bit in the status register is re set and the ddrq signal is masked. the buffer is flushed (when in the write state) or invalidated (when in the read state) when a terminal count condition exists; that is, the current region descriptor has the eol bit set and that region has been exhausted. the buffer is also flushe d (write state) or invali dated (read state) when the interrupt bit in the bus master ide status register is set. softwa re that reads the status register and finds the error bit reset, and either the active bit reset or the interrupt bit set, can be assured that all data destined for system memory has been transferred and that data is valid in system memory. table 5-41 describes how to interpret the interrupt and active bits in the status register after a dma transfer has started. 5.16.2.5 error conditions ide devices are sector based mass storage devices. the drivers handle errors on a sector basis; either a sector is transferred successfu lly or it is not. a sector is 512 bytes. if the ide device does not complete the transfer due to a hardware or software error, the command will eventually be stopped by the driver setting command start bit to 0 when the driver times out the disk transaction. information in the ide devi ce registers help isolate the cause of the problem. if the controller encounters an er ror while doing the bus master transfers it will stop the transfer (i.e., reset the active bit in the command regist er) and set the error bit in the bus master ide status register. the controller does not generate an interrupt when this happens. the device driver can use device specific informa tion (pci configuration space st atus register and ide drive register) to determine what caused the error. whenever a requested transfer does not complete properly, information in the ide device registers (sector count) can be used to determine how much of the transfer was comp leted and to construct a new prd table to complete the requested operati on. in most cases the existing prd table can be used to complete the operation. table 5-41. interrupt/active bit interaction definition interrupt active description 0 1 dma transfer is in progress. no interrupt has been generated by the ide device. 10 the ide device generated an interrupt. t he controller exhausted the physical region descriptors. this is the normal completion case where the size of the physical memory regions was equal to the ide device transfer size. 11 the ide device generated an interrupt. the controller has not reached the end of the physical memory regions. this is a vali d completion case where the size of the physical memory regions was larger than the ide device transfer size. 00 this bit combination signals an error condition. if the error bit in the status register is set, then the controller has some problem transferring data to/from memory. specifics of the error have to be determi ned using bus-specific information. if the error bit is not set, then the prd's specifi ed a smaller size than the ide transfer size.
184 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.16.3 ultra ata/100/66/33 protocol the ich6 supports ultra ata/100/66/33 bus mastering protocol, providing support for a variety of transfer speeds with ide devices. ultra ata/33 provides transfers up to 33 mb/s, ultra ata/66 provides transfers at up to 44 mb/s or 66 mb/s, and ultra ata/100 can achie ve read transfer rates up to 100 mb/s and write transfer rates up to 88.9 mb/s. the ultra ata/100/66/33 definition also incor porates a cyclic redun dancy checking (crc-16) error checking protocol. 5.16.3.1 operation initial setup programming consists of enabling and performing the proper configuration of the ich6 and the ide device for ultra ata/100/66/33 operation. for the ich6, this consists of enabling synchronous dma mode and setting up appropriate sync hronous dma timings. when ready to transfer data to or from an ide device, the bus master ide programming model is followed. once programmed, the drive and ich6 co ntrol the transfer of data via the ultra ata/ 100/66/33 protocol. the actual data transfer consis ts of three phases, a st art-up phase, a data transfer phase, and a burst termination phase. the ide device begins the start-up phase by asse rting dmarq signal. when ready to begin the transfer, the ich6 asserts dmack# signal. when dmack# signal is asserted, the host controller drives cs0# and cs1# inactive, da0 ?da2 low. for write cycles, th e ich6 de-asserts stop, waits for the ide device to assert dmardy#, and then dr ives the first data word and strobe signal. for read cycles, the ich6 tri-states the dd lin es, de-asserts stop, and asserts dmardy#. the ide device then sends the fi rst data word and strobe. the data transfer phase continues the burst transfers with the data transmitter (ich6 ? writes, ide device ? reads) providing data and to ggling strobe. data is transfer red (latched by receiver) on each rising and falling edge of strobe. the tran smitter can pause the bu rst by holding strobe high or low, resuming the burst by again toggl ing strobe. the receiver can pause the burst by de-asserting dmardy# and resumes the transfer s by asserting dmardy#. the ich6 pauses a burst transaction to prevent an in ternal line buffer over or under flow condition, resuming once the condition has cleared. it may also pause a trans action if the current prd byte count has expired, resuming once it has fetched the next prd. the current burst can be terminat ed by either the transmitter or receiver. a burst termination consists of a stop request, stop acknowledge and transfer of crc data. the ich6 can stop a burst by asserting stop, with the ide device acknowl edging by de-asserting dmarq. the ide device stops a burst by de-asserting dmarq and the ich6 acknowledges by asserting stop. the transmitter then drives the stro be signal to a high level. the ich6 then drives the crc value onto the dd lines and de-assert dmack#. the id e device latches the crc value on rising edge of dmack#. the ich6 terminates a burst transfer if it needs to service the opposite ide channel, if a programmed i/o (pio) cycle is executed to the ide channel currently running the burst, or upon transferring the last data from the final prd.
intel ? i/o controller hub 6 (ich6) family datasheet 185 functional description 5.16.4 ultra ata/33/66/100 timing the timings for ultra ata/33/66/100 modes are programmed via the synchronous dma timing register and the ide configuration register. diff erent timings can be progr ammed for each drive in the system. the base clock freque ncy for each drive is selected in the ide configuration register. the cycle time (ct) and ready to pause (rp) time (defined as multiples of the base clock) are programmed in the synchronous dma timing regi ster. the cycle time represents the minimum pulse width of the data strobe (strobe) signal. the ready to pause time represents the number of base clock periods that the ich6 waits from de-assertion of dmardy# to the assertion of stop when it desires to stop a burst read transaction. note: the internal base clock for ultra ata/100 (mode 5) runs at 133 mhz, and the cycle time (ct) must be set for three base clocks. the ich6 t hus toggles the write strobe signal every 22.5 ns, transferring two bytes of data on each strobe edge. this means th at the ich6 performs mode 5 write transfers at a maximum rate of 88.9 mb/s. for read transfers, th e read strobe is driven by the ata/100 device, and the ich6 supports reads at the maximum rate of 100 mb/s. 5.16.5 ata swap bay to support pata swap bay, the ich6 allows the ide output signa ls to be tri-stated and input buffers to be turned off. this should be done prio r to the removal of the drive. the output signals can also be driven low. this can be used to remove charge built up on the signals. configuration bits are included in the ide i/o configuration register, offset 54h in the ide pci configuration space. in a pata swap bay operation, an ide device is removed and a new one inserted while the ide interface is powered down and the rest of the system is in a fully powered- on state (so). during a pata swap bay operation, if the operating system executes cycles to the ide interface after it has been powered down it will cause the ich6 to hang the system that is waiting for iordy to be asserted from the drive. to correct this issue, the foll owing bios procedures are requir ed for performing an ide swap: 1. program ide sig_mode (confi guration register at offset 54h) to 10b (drive low mode). 2. clear iordy sample point enable (bits 1 or 5 of ide timing reg.). this prevents the ich6 from waiting for iordy assertion when the operating system accesses the ide device after the ide drive powers down, and ensu res that 0s are always be re turned for read cycles that occur during swap operation. warning: software should not attempt to control the outputs (either tri-state or driving low), while an ide transfer is in progress. unpredictable re sults could occur, in cluding a system lockup. 5.16.6 smi trapping device 31:function 1: offset c0h (see section 11.1.26 ) contain control for generating smi# on accesses to the ide i/o spaces. these b its map to the legacy ranges (1f0 ? 1f7h and 3f6h). accesses to one of these ranges with the appropriate bit set causes th e cycle to not be forwarded to the ide controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enable d for the device being accessed, then the register is updated, an smi# is generated, and the device activity status bits (device 31:function 1:offset c4h) are updated indicating that a trap occurred.
186 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.17 sata host controller (d31:f2) the sata function in the ich6 has dual modes of operation to support different operating system conditions. in the case of native ide enabled operating systems, the ich6 has separate pci functions for serial and parallel ata (?enhanced mode?). to support leg acy operating systems, there is only one pci function for both the serial and parallel ata ports if functionality from both sata and pata devices is desired (?combined mode?). the map register, section 12.1.29 , provides the ability to share pci functions. when sharing is enabled, all decode of i/o is done through the sata registers. device 31, function 1 (ide controller) is hidden by software writing to the function disable register (d31, f0, offset f2h, bit 1), and its confi guration registers are not used. the ich6 sata controller features four (desktop only) / two (mobile only) sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). each interface is supported by an independent dma controller. the ich6 sata controller interacts with an attached mass storage device through a register interface that is equivalent to th at presented by a traditional ide host adapter. the host software follows existing standards and conventions when accessing the re gister interface and follows standard command protocol conventions. note: sata interface transfer rates are independent of udma mode settings. sata interface transfer rates will operate at the bus?s maximum speed, regardless of the udma mode reported by the sata device or the system bios. 5.17.1 theory of operation 5.17.1.1 standard ata emulation the ich6 contains a set of registers that shadow the contents of the legacy ide registers. the behavior of the command and control block regist ers, pio, and dma data transfers, resets, and interrupts are all emulated. note: the ich6 requires that software wait for bsy=0 and drdy=1 after drive power-up before writing to the device control register. further, it is recommended that software perform the following steps for each sata channel befo re unmasking the sata controller?s irq: 1. read the (task file) status re gister of each attached device. 2. read the existing bus mast er status register value. 3. or that value with 4 4. write the resulting value back to the bus master status register. the ich6 will assert intr when the mast er device completes the edd (execute device diagnostics) command regardless of the command co mpletion status of the slave device. if the master completes edd first, an intr is gene rated and bsy will remain ?1? until the slave completes the command. if the slave completes edd first, bsy will be ?0? when teh master completes the edd command and asserts intr. so ftware must wait for bsy to clear before completing an edd command, as required by the ata5 through ata7 (t13) industry specifications.
intel ? i/o controller hub 6 (ich6) family datasheet 187 functional description 5.17.1.2 48-bit lba operation the sata host controller supports 48-bit lba through the host-to-device register fis when accesses are performed via writes to the task file. the sata host controller will ensure that the correct data is put into the correct byte of the host-to-device fis. there are special considerations wh en reading from the ta sk file to support 48-bit lba operation. software may need to read all 16-bits. since the re gisters are only 8-bits wi de and act as a fifo, a bit must be set in the device/control register, which is at offset 3f6h for primary and 376h for secondary (or their native counterparts). if software clears bit 7 of the control register befo re performing a read, the last item written will be returned from the fifo. if software sets bit 7 of the control register before performing a read, the first item written will be returned from the fifo. 5.17.2 sata swap bay support dynamic hot-plug (e.g., surprise removal) is not supported by the sata host controller without special support from ahci and the proper board hardware. however, the ich6 does provide for basic sata swap bay support using the psc regist er configuration bits and power management flows. a device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. note: this sata swap bay operation requires board hardware (implementation specific), bios, and operating system support. 5.17.3 intel ? matrix storage technolo gy configuration (ich6r only) the intel matrix storage technology solution offers data striping for higher performance (raid level 0), alleviating disk bottlenecks by taking advantage of the independent dma engines that each sata port offers in the ich6r. intel matrix storage technology also offers mirroring for data security (raid level 1). there is no loss of pci resources (request/grant pair) or add-in card slot. intel matrix storage technology functionality requires the following items: ? ich6r ? intel ? application accelerator raid op tion rom must be on the platform ? intel application accelerator raid ed ition drivers, most recent revision. ? two sata hard disk drives. intel matrix storage technology is not available in the following configurations: ? the sata controller in compatible mode. 5.17.3.1 intel ? application accelerator raid option rom the intel application accelerator raid option rom is a standard pnp option rom that is easily integrated into any system bios . when in place, it provides the fo llowing three pr imary functions:
188 intel ? i/o controller hub 6 (i ch6) family datasheet functional description ? provides a text mode user interface that allows the user to manage the raid confi guration on the system in a pre-operat ing system environment. its feature set is kept simple to keep size to a minimum, but allows the user to create & dele te raid volumes and select recovery options when problems occur. ? provides boot support when using a raid volume as a boot disk. it does this by providing int13 services when a raid volume needs to be accessed by dos applications (such as ntldr) and by exporting the raid volumes to the system bios for selection in the boot order. ? at each boot up, pr ovides the user with a status of the raid volumes and the option to enter the user interface by pressing ctrl-i. 5.17.4 power management operation power management of the ich6 sata controller and ports will cover operations of the host controller and the sata wire. 5.17.4.1 power state mappings the d0 pci power management state for device is supported by the ich6 sata controller. sata devices may also have multiple power stat es. from parallel ata, three device states are supported through acpi. they are: ? d0 ? device is working and instantly available. ? d1 ? device enters when it receives a standb y immediate command. exit latency from this state is in seconds ? d3 ? from the sata device?s perspect ive, no different than a d1 stat e, in that it is entered via the standby immediate command. however, an acpi method is also called which will reset the device and then cut its power. each of these device states are subsets of the host controller?s d0 state. finally, sata defines three phy layer power states, that have no equivalent mappings to parallel ata. they are: ? phy ready ? phy logic and pll are both on and active ? partial ? phy logic is powered, but in a reduced stat e. exit latency is no longer than 10 ns ? slumber ? phy logic is powered, but in a reduced state. exit latency can be up to 10 ms. since these states have much lower exit latenc y than the acpi d1 and d3 states, the sata controller defines these states as su b-states of the device d0 state.
intel ? i/o controller hub 6 (ich6) family datasheet 189 functional description 5.17.4.2 power state transitions 5.17.4.2.1 partial and slumber state entry/exit the partial and slumber states sa ve interface power when the interf ace is idle. it would be most analogous to pci clkrun# (in power savings, no t in mechanism), where the interface can have power saved while no commands are pending. the sata controller defines phy layer power management (as performed via primitives) as a dr iver operation from the host side, and a device proprietary mechanism on the devi ce side. the sata controller accepts device transition types, but does not issue any transitions as a host. all r eceived requests from a sata device will be acked. when an operation is performed to the sata contro ller such that it needs to use the sata cable, the controller must check whether the link is in the partial or slumber states, and if so, must issue a com_wake to bring the link back online. similarly, the sata device must perform the same action. 5.17.4.2.2 device d1, d3 states these states are entered after some period of time when software has determined that no commands will be sent to this device for some time. the mechanism for putting a device in these states does not involve any work on the host co ntroller, other then sending commands over the interface to the device. the command most likely to be used in ata/atapi is the ?standby immediate? command. 5.17.4.2.3 host controller d3 hot state after the interface and device have been put into a low power state, the sata host controller may be put into a low power state. this is performed via the pci power management registers in configuration space. there are two very important aspects to note when using pci power management. ? when the power state is d3, only accesses to co nfiguration space are allo wed. any attempt to access the memory or i/o spaces will result in master abort. ? when the power state is d3, no interrupts may be generated, even if they are enabled. if an interrupt status bit is pending when the controller transitions to d0, an interrupt may be generated. figure 5-8. sata power states intel ? ich6 sata controller = d0 device = d3 p ower resume latency device = d0 phy = ready device = d1 phy = slumber phy = partial phy = off (port disabled) phy = slumber phy = off (port disabled) phy = slumber phy = off (port disabled)
190 intel ? i/o controller hub 6 (i ch6) family datasheet functional description when the controller is put into d3, it is assumed that software has properly shut down the device and disabled the ports. th erefore, there is no need to sustai n any values on the port wires. the interface will be treated as if no device is present on the cable , and power will be minimized. when returning from a d3 state, an internal reset will not be performed. 5.17.4.2.4 non-ahci mode pme# generation when in non-ahci mode (legacy mode) of operation, the sata controller does not generate pme#. this includes attach events (since the port must be disabled), or interlock switch events (via the satagp pins). 5.17.4.3 smi trapping (apm) device 31:function2:offset c0h (see section 12.1.40 ) contain control for generating smi# on accesses to the ide i/o spaces. these bi ts map to the legacy ranges (1f0 ? 1f7h, 3f6h, 170 ? 177h, and 376h). if the sata controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the sata controller, and for an smi# to be generated. if an access to the bus-master ide registers occurs while trapping is enabled for the device being accesse d, then the register is updated, an smi# is generated, and the device activity status bits ( section 12.1.41 ) are updated indica ting that a trap occurred. 5.17.5 sata led the sataled# output is driven when the bsy bit is set in any sata port. the sataled# is an active-low open-collector output . when sataled# is low, the led should be active. when sataled# is high, the led should be inactive. 5.17.6 ahci operation the ich6r/ich6-m provides hardware support for advanced host controller interface (ahci), a new programming interface for sata host controllers developed thru a joint industry effort. ahci defines transactions between the ich6r/ich6-m sata controller and software and enables advanced performance and usability with sata . platforms supporting ahci may take advantage of performance features such as no master/sla ve designation for sata devices?each device is treated as a master?and hardware assisted native command queuing. ahci also provides usability enhancements (such as hot-plug). ahci requires appropriate software support (e.g., an ahci driver) and for some features, hardware suppor t in the sata device or additional platform hardware. the ich6r/ich6-m supports all of the mandatory features of the serial ata advanced host controller interface specification, rev 1.0 and many optional features, such as hardware assisted native command queuing, aggressive power mana gement, led indicator support, and hot-plug thru the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). note: for reliable device removal notification while in ahci operation without the use of interlock switches (surprise removal), interface power mana gement should be disabled for the associated port. see section 7.3.1 of the ahci specification for more information.
intel ? i/o controller hub 6 (ich6) family datasheet 191 functional description 5.18 high precision event timers this function provides a set of timers that can be used by the operating system. the timers are defined such that in the future, the operating syst em may be able to assign specific timers to used directly by specific app lications. each timer can be configur ed to cause a separate interrupt. ich6 provides three timers. the three timers are implemented as a single counter each with its own comparator and value register. this counter in creases monotonically. e ach individual timer can generate an interrupt when the value in its value register matches the value in the main counter. the registers associated with these timers ar e mapped to a memory space (much like the i/o apic). however, it is not implemented as a st andard pci function. the bios reports to the operating system the location of the register space. the hardware can support an assignable decode space; however, the bios sets this space prior to handing it over to the operating system (see section 6.4 ). it is not expected that the operating system will move the location of these timers once it is set by the bios. 5.18.1 timer accuracy 1. the timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. the timer is monotonic. it does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). the main counter is clocked by the 14.31818 mhz clock, synchronized into the 66.666 mhz domain. this results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. the accuracy of the main counter is as accu rate as the 14 .3818 mhz clock. 5.18.2 interrupt mapping mapping option #1 (legacy replacement option) in this case, the legacy replacem ent rout bit (leg_rt_cnf) is set. this forces the mapping found in table 5-42 . mapping option #2 (standard option) in this case, the legacy replacem ent rout bit (leg_rt_cn f) is 0. each timer has its own routing control. the supported interrupt values are irq 20, 21, 22, and 23. table 5-42. legacy replacement routing timer 8259 mapping apic mapping comment 0irq0 irq2 in this case, the 8254 timer will not cause any interrupts 1irq8 irq8 in this case, the rtc will not cause any interrupts. 2 per irq routing field. per irq routing field
192 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.18.3 periodic vs. non-periodic modes non-periodic mode timer 0 is configurable to 32 (default) or 64-bit mode, whereas timers 1 and 2 only support 32-bit mode (see section 20.1.5 ). all three timers support non-periodic mode. consult section 2.3.9.2.1 of the ia-pc hpet specification for a description of this mode. periodic mode timer 0 is the only timer that supports periodic mode. consult section 2.3.9.2.2 of the ia-pc hpet specification for a description of this mode. the following usage model is expected: 1. software clears the enable_cnf bit to prevent any interrupts 2. software clears the main counter by writing a value of 00h to it. 3. software sets the timer0_val_set_cnf bit. 4. software writes the new value in the timer0_comparator_val register 5. software sets the enable_cnf bit to enable interrupts. the timer 0 comparator value register cannot be pr ogrammed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. if the actual timer 0 comparator value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. set timer0_val_set_cnf bit 2. set the lower 32 bits of the timer0 comparator value register 3. set timer0_val_set_cnf bit 4. 4) set the upper 32 bits of the timer0 comparator value register 5.18.4 enabling the timers the bios or operating system pnp code should route the interrupts. this includes the legacy rout bit, interrupt rout bit (f or each timer), interrupt type (to select the edge or level type for each timer) the device driver code should do th e following for an available timer: 1. set the overall enable bit (offset 04h, bit 0). 2. set the timer type field (selects one-shot or periodic). 3. set the interrupt enable 4. set the comparator value
intel ? i/o controller hub 6 (ich6) family datasheet 193 functional description 5.18.5 interrupt levels interrupts directed to the internal 8259s are active high. see section 5.10 for information regarding the polarity programming of the i/o apic for detecting internal interrupts. if the interrupts are mapped to the i/o apic and set for level-triggered mode, they can be shared with pci interrupts. this may be shared although it?s unlikely for the operating system to attempt to do this. if more than one timer is configured to shar e the same irq (using the timern_int_rout_cnf fields), then the software must configure the timers to level-triggered mode. edge-triggered interrupts cannot be shared. 5.18.6 handling interrupts if each timer has a unique interrupt and the timer has been configured fo r edge-triggered mode, then there are no specific step s required. no read is required to process the interrupt. if a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. this is done by reading the interrupt stat us register and writing a 1 back to the bit position for the interrupt to be cleared. independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. if timer 0 is set up to generate a periodic interr upt, the software can check to see how much time remains until the next interrupt by checking the timer value register. 5.18.7 issues related to 64-bit timers with 32-bit processors a 32-bit timer can be read directly using processors that are capable of 32-bi t or 64-bit instructions. however, a 32-bit processor may not be able to directly read 64-bit tim er. a race condition comes up if a 32-bit processor reads the 64-bit register usi ng two separate 32-bit reads. the danger is that just after reading one half, the other half rolls over and changes the first half. if a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. if a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by settin g the timern_32mode_cnf bit. this causes the timer to behave as a 32-bit timer. the upper 32-bits are always 0.
194 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.19 usb uhci host controlle rs (d29:f0, f1, f2, and f3) the ich6 contains four usb 2.0 full/low-speed host controllers that support the standard universal host controller interface (uhci), revisi on 1.1. each uhci ho st controller (uhc) includes a root hub with tw o separate usb ports each, for a total of eight usb ports. ? overcurrent detection on all eight usb ports is supported. the overcurrent inputs are not 5 v tolerant, and can be used as gpis if not needed. ? the ich6?s uhci host controllers are arbitrated differently than standard pci devices to improve arbitration latency. ? the uhci controllers use the analog front end (afe) embedded cell that allows support for usb full-speed signaling rates, instead of usb i/o buffers. 5.19.1 data structures in main memory section 3.1 - 3.3 of the universal host controller interface, revision 1.1 specification details the data structures used to commun icate control, status, and data between software and the ich6. 5.19.2 data transfers to/from main memory section 3.4 of the universal host controller interface, revision 1.1 specification describes the details on how hcd and the ich6 communi cate via the schedule data structures. 5.19.3 data encoding and bit stuffing the ich6 usb employs nrzi data encoding (non -return to zero inverted) when transmitting packets. full details on this implementation are given in the universal serial bus revision 2.0 specification . 5.19.4 bus protocol 5.19.4.1 bit ordering bits are sent out onto the bus least significant bit (lsb) first, followed by next lsb, through to the most significant bit (msb) last. 5.19.4.2 sync field all packets begin with a synchronization (sync) field, which is a coded sequence that generates a maximum edge transition density. the sync field appears on the bus as idle followed by the binary string ?kjkjkjkk,? in its nrzi encoding. it is used by the input circuitry to align incoming data with the local clock and is defined to be 8 bits in length. sync serves only as a synchronization mechanism and is not shown in the following packet diagrams. the last two bits in the sync field are a marker that is used to identif y the first bit of the pid. all subsequent bits in the packet must be indexed from this point.
intel ? i/o controller hub 6 (ich6) family datasheet 195 functional description 5.19.4.3 packet field formats all packets have distinct start and end of p acket delimiters. full details are given in the universal serial bus revision 2.0 specification in section 8.3.1. 5.19.4.4 address fields function endpoints are addressed using the function address field and the endpoint field. full details on this are given in the universal serial bus revision 2.0 specification in section 8.3.2. 5.19.4.5 frame number field the frame number field is an 11-b it field that is incremented by th e host on a per frame basis. the frame number field rolls over up on reaching its maximum value of 7ffh, and is sent only for sof tokens at the start of each frame. 5.19.4.6 data field the data field may range from 0 to 1023 bytes and mu st be an integral numbers of bytes. data bits within each byte are shifted out lsb first. 5.19.4.7 cyclic redundancy check (crc) crc is used to protect the all non-pid fields in token and data p ackets. in this context, these fields are considered to be protected fields . full details on this are given in the universal serial bus revision 2.0 specification in section 8.3.5. 5.19.5 packet formats the usb protocol calls out several packet types: token, data, and handshake packets. full details on this are given in the universal serial bus r evision 2.0 specification in section 8.4. 5.19.6 usb interrupts there are two general groups of usb interrupt sources, those resulting from execution of transactions in the schedule, and those resulting from an ich6 operation error. all transaction-based sources can be masked by software through the ich6?s interrupt enable register. additionally, individual transfer descriptors can be marked to generate an interrupt on completion. when the ich6 drives an inte rrupt for usb, it internally drives the pirqa# pin for usb function #0 and usb function #3, pirqd# pin for usb function #1, and the pirqc# pin for usb function #2, until all sources of the interrupt ar e cleared. in order to acco mmodate some operating systems, the interrupt pin register must contai n a different value for each function of this new multi-function device.
196 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.19.6.1 transaction-based interrupts these interrupts are not signaled until after the stat us for the last complete transaction in the frame has been written back to host memory. this guara ntees that software can safely process through (frame list current index -1) when it is servicing an interrupt. crc error / time-out a crc/time-out error occurs when a packet tran smitted from the ich6 to a usb device or a packet transmitted from a usb de vice to the ich6 generates a crc er ror. the ich6 is informed of this event by a time-out from the usb device or by the ich6?s crc checker generating an error on reception of the packet. additionally, a usb bus time-out o ccurs when usb devices do not respond to a transaction phase within 19-bit times of an eop. either of these conditions causes the c_err field of the td to decrement. when the c_err field decrements to 0, the following occurs: ? the active bit in the td is cleared ? the stalled bit in the td is set ? the crc/time-out bit in the td is set. ? at the end of the frame, the usb error interr upt bit is set in the hc status register. if the crc/time out interrupt is enabled in the in terrupt enable register, a hardware interrupt will be signaled to the system. interrupt on completion transfer descriptors contain a bit that can be set to cause an interrupt on their completion. the completion of the transaction asso ciated with that block causes th e usb interrupt bit in the hc status register to be set at the end of the fram e in which the transfer completed. when a td is encountered with the ioc bit set to 1, the ioc bit in the hc status register is set to 1 at the end of the frame if the active bit in the td is set to 0 (even if it was set to 0 when initially read). if the ioc enable bit of interrupt enable register (bit 2 of i/o offset 04h) is set, a hardware interrupt is signaled to the system. the usb interrupt bit in the hc status register is set either when the td completes successfu lly or because of errors. if the comp letion is because of errors, the usb error bit in the hc status register is also set. short packet detect a transfer set is a collection of data which requir es more than one usb transaction to completely move the data across the usb. an example migh t be a large print file which requires numerous tds in multiple frames to completely transfer the da ta. reception of a data packet that is less than the endpoint?s max packet size durin g control, bulk or interrupt tr ansfers signals the completion of the transfer set, even if ther e are active tds remaining for this tr ansfer set. setting the spd bit in a td indicates to the hc to set the usb interrupt bit in the hc status register at the end of the frame in which this event occurs. this feature streamlines the proce ssing of input on these transfer types. if the short packet interrupt enable bit in the interrupt enable register is set, a hardware interrupt is signaled to the system at th e end of the frame wher e the event occurred.
intel ? i/o controller hub 6 (ich6) family datasheet 197 functional description serial bus babble when a device transmits on the usb for a time greater than its assigned max length, it is said to be babbling. since isochrony can be destroyed by a babbling device, this error results in the active bit in the td being cleared to 0 and the stalled and babble bits being set to 1. the c_err field is not decremented for a babble. the usb error interrupt b it in the hc status register is set to 1 at the end of the frame. a hardware interrupt is signaled to the system. if an eof babble was caused by the ich6 (due to incorrect schedule for instance), the ich6 forces a bit stuff error followed by an eop and the start of the next frame. stalled this event indicates that a devi ce/endpoint returned a stall handshake during a transaction or that the transaction ended in an error condition. the tds stalled bit is set and the active bit is cleared. reception of a stall does not decrement the error counter. a hardware interrupt is signaled to the system. data buffer error this event indicates that an ove rrun of incoming data or a under-run of outgoing data has occurred for this transaction. this would generally be cau sed by the ich6 not being able to access required data buffers in memory within necessary latenc y requirements. either of these conditions causes the c_err field of the td to be decremented. when c_err decrements to 0, the active bit in the td is cleared, the stalled bit is set, the usb error interrupt bit in the hc status register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system. bit stuff error a bit stuff error results from the detection of a sequence of more that six 1s in a row within the incoming data stream. this causes the c_err fi eld of the td to be decremented. when the c_err field decrements to 0, the active bit in the td is cleared to 0, the stalled bit is set to 1, the usb error interrupt bit in the hc st atus register is set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
198 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.19.6.2 non-transaction based interrupts if an ich6 process error or syst em error occur, the ich6 halts an d immediately issues a hardware interrupt to the system. resume received this event indicates that the ich6 received a resume signal from a device on the usb bus during a global suspend. if this interrupt is enab led in the interrupt enable register, a hardware interrupt is signaled to the system allowing th e usb to be brought out of the suspend state and returned to normal operation. ich6 process error the hc monitors certain critical fields during operation to ensure that it does not process corrupted data structures. these include checking for a valid pid and verifying that the maxlength field is less than 1280. if it detects a condition that wo uld indicate that it is pr ocessing corrupted data structures, it immediately halts pr ocessing, sets the hc process erro r bit in the hc status register and signals a hardware interrupt to the system. this interrupt cannot be disabled through the interrupt enable register. host system error the ich6 sets this bit to 1 when a parity error, master abort, or target abort occur. when this error occurs, the ich6 clears the run/stop bit in the command register to prevent further execution of the scheduled tds. this interrupt can not be disabled through the interrupt enable register. 5.19.7 usb power management the host controller can be put into a suspended st ate and its power can be removed. this requires that certain bits of information are retained in th e resume power plane of th e ich6 so that a device on a port may wake the system. such a device may be a fax-modem, which will wake up the machine to receive a fax or take a voice message . the settings of the foll owing bits in i/o space will be maintained when the ich6 enters the s3, s4, or s5 states. when the ich6 detects a resume event on any of its ports, it sets the corresponding usb_sts bit in acpi space. if usb is enabled as a wake/b reak event, the system wakes up and an sci generated. table 5-43. bits maintained in low power states register offset bit description command 00h 3 enter global suspend mode (egsm) status 02h 2 resume detect port status and control 10h & 12h 2 port enabled/disabled 6 resume detect 8 low-speed device attached 12 suspend
intel ? i/o controller hub 6 (ich6) family datasheet 199 functional description 5.19.8 usb legacy keyboard operation when a usb keyboard is plugged into the system, and a standard keyboard is not, the system may not boot, and ms-dos legacy softwa re will not run, becau se the keyboard will not be identified. the ich6 implements a series of trapping opera tions which will snoop accesses that go to the keyboard controller, and put the expected data from the usb keyboard into the keyboard controller. note: the scheme described below assumes that the keyboard controller (8042 or equivalent) is on the lpc bus. this legacy operation is pe rformed through smm space. figure 5-9 shows the enable and status path. the latched smi source (60r, 60w, 64r, 64w) is available in the status register. because the enable is after the latch, it is possible to ch eck for other events that didn't necessarily cause an smi. it is the software's responsibility to logically and the value with the appropriate enable bits. note also that the smi is generated before the pci cycle completes (e.g., before trdy# goes active) to ensure that the processor doesn't comp lete the cycle before the smi is observed. this method is used on mpiix and has been validated. the logic also needs to block the accesses to the 8042 . if there is an external 8042, then this is simply accomplished by not activat ing the 8042 cs. this is simply done by logica lly anding the four enables (60r, 60w, 64r, 64 w) with the 4 types of accesses to determine if 8042cs should go active. an additional term is required for the ?pass-through? case. the state table for figure 5-9 is shown in table 5-44 . figure 5-9. usb legacy keyboard flow diagram kbc accesses pci config read, write 60 read clear smi_60_r en_smi_on_60r comb. decoder and same for 60w, 64r, 64w smi or to individual "caused by" "bits" to pirqd# to "caused by" bit and and en_pirqd# usb_irq clear usb_irq en_smi_on_irq s d r s d r
200 intel ? i/o controller hub 6 (i ch6) family datasheet functional description table 5-44. usb legacy keyboard state transitions current state action data value next state comment idle 64h / write d1h gatestate1 standard d1 command. cycle passed through to 8042. smi# doesn't go active. pstate (offset c0, bit 6) goes to 1. idle 64h / write not d1h idle bit 3 in configuration regi ster determines if cycle passed through to 8042 and if smi# generated. idle 64h / read n/a idle bit 2 in configuration regi ster determines if cycle passed through to 8042 and if smi# generated. idle 60h / write don't care idle bit 1 in configuration regi ster determines if cycle passed through to 8042 and if smi# generated. idle 60h / read n/a idle bit 0 in configuration regi ster determines if cycle passed through to 8042 and if smi# generated. gatestate1 60h / write xxh gatestate2 cycle passed through to 8042, even if trap enabled in bit 1 in configuration register. no smi# generated. pstate remains 1. if data value is not dfh or ddh then the 8042 may chose to ignore it. gatestate1 64h / write d1h gatestate1 cycle passed through to 8042, even if trap enabled via bit 3 in configuration register. no smi# generated. pstate remains 1. stay in gatestate1 because this is part of the double-trigger sequence. gatestate1 64h / write not d1h ilde bit 3 in configuration space determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in configuration register is set, then smi# should be generated. gatestate1 60h / read n/a idle this is an invalid sequence. bit 0 in configuration register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in configuration register is set, then smi# should be generated. gatestate1 64h / read n/a gatestate1 just stay in same state. generate an smi# if enabled in bit 2 of configuration register. pstate remains 1. gatestate2 64 / write ffh idle standard end of sequence. cycle passed through to 8042. pstate goes to 0. bit 7 in configuration space determines if smi# should be generated. gatestate2 64h / write not ffh idle improper end of sequence. bit 3 in configuration register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in configuration register is set, then smi# should be generated. gatestate2 64h / read n/a gatestate2 just stay in same state. generate an smi# if enabled in bit 2 of configuration register. pstate remains 1. gatestate2 60h / write xxh idle improper end of sequence. bit 1 in configuration register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in configuration register is set, then smi# should be generated. gatestate2 60h / read n/a idle improper end of sequence. bit 0 in configuration register determines if cycle passed through to 8042 and if smi# generated. pstate goes to 0. if bit 7 in configuration register is set, then smi# should be generated.
intel ? i/o controller hub 6 (ich6) family datasheet 201 functional description 5.20 usb ehci host controller (d29:f7) the ich6 contains an enhanced host controller interface (ehci) compliant host controller which supports up to eight usb 2.0 high-speed compliant ro ot ports. usb 2.0 allows data transfers up to 480 mb/s using the same pins as the eight usb full-speed/low-speed port s. the ich6 contains port-routing logic that determines whether a usb port is controlled by one of the uhci controllers or by the ehci controller. usb 2.0 based debug port is also implemented in the ich6. a summary of the key architectur al differences between the usb uhci host controllers and the ehci host controller are shown in table 5-45 . 5.20.1 ehc initialization the following descriptions step through the expected ich6 enhanced host controller (ehc) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off. 5.20.1.1 bios initialization bios performs a number of plat form customization steps after the core well has powered up. contact your intel field representative for additional ich6 bios information. 5.20.1.2 driver initialization see chapter 4 of the enhanced host controller interface sp ecification for univer sal serial bus, revision 1.0 . table 5-45. uhci vs. ehci parameter usb uhci usb ehci accessible by i/o space memory space memory data structure single linked list se parated in to periodic and asynchronous lists differential signaling voltage 3.3 v 400 mv ports per controller 2 8
202 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.20.1.3 ehc resets in addition to the standard ich6 hardware rese ts, portions of the ehc are reset by the hcreset bit and the transition from the d3 hot device power management state to the d0 state. the effects of each of these resets are shown in the following table: if the detailed register descript ions give exceptions to these rule s, those exceptions override these rules. this summary is provided to help explain the reasons for the reset policies. 5.20.2 data structures in main memory see section 3 and appendix b of the enhanced host controller interface specification for universal serial bus, revision 1.0 for details. 5.20.3 usb 2.0 enhanced host controller dma the ich6 usb 2.0 ehc implements three sources of usb packets. they are, in order of priority on usb during each microframe: 1. the usb 2.0 debug port (see section usb 2.0 based debug port), 2. the periodic dma engine, and 3. the asynchronous dma engine. the ich6 always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. if there is time left in the microframe, then the ehc performs any pending asynchronous traffic until the end of th e microframe (eof1). note that the debug port traffic is only presented on one port (port #0), while the other por ts are idle during this time. 5.20.4 data encoding and bit stuffing see chapter 8 of the universal serial bus specification, revision 2.0. 5.20.5 packet formats see chapter 8 of the universal serial bus specification, revision 2.0 . reset does reset does not reset comments hcreset bit set. memory space registers except structural parameters (which is written by bios). configuration registers. the hcreset must only affect registers that the ehci driver controls. pci configuration space and bios-programmed parameters can not be reset. software writes the device power state from d3 hot (11b) to d0 (00b). core well registers (except bios- programmed registers). suspend well registers; bios- programmed core well registers. the d3-to-d0 transition must not cause wake information (suspend well) to be lost. it also must not clear bios-programmed registers because bios may not be invoked following the d3-to-d0 transition.
intel ? i/o controller hub 6 (ich6) family datasheet 203 functional description the ich6 ehci allows entrance to usb test modes, as defined in the usb 2.0 specification, including test j, test packet, etc. however note that the ich6 test packet test mode interpacket gap timing may not meet the usb2.0 specification. 5.20.6 usb 2.0 interrupt s and error conditions section 4 of the enhanced host controller interface specification for universal serial bus, revision 1.0 goes into detail on the ehc interrupts and the error conditions that cause them. all error conditions that the ehc det ects can be reported through the ehci interrupt status bits. only ich6-specific interrupt and error-reporting behavi or is documented in this section. the ehci interrupts section must be read first, followed by this section of the datasheet to fully comprehend the ehc interrupt and error-reporting functionality. ? based on the ehc?s buffer sizes and buffer management policies, the data buffer error can never occur on the ich6. ? master abort and target abort responses from hub interface on ehc-initiated read packets will be treated as fatal host errors. the ehc halts when these conditions are encountered. ? the ich6 may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. the requirement in the enhanced host controller interface specification for universal serial bu s, revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on dmi before the interrupt is asserted. ? since the ich6 supports the 102 4-element frame list size, the frame list rollover interrupt occurs every 1024 milliseconds. ? the ich6 delivers interrupts using pirqh#. ? the ich6 does not modify the cerr count on an interrupt in when the ?do complete-split? execution criteria are not met. ? for complete-split transactions in the periodic list, the ?missed microframe? bit does not get set on a control-structure-fetch that fails the late-start test. if subsequent accesses to that control structure do not fail the late-start test, then the ?missed microframe? bit will get set and written back. 5.20.6.1 aborts on usb 2.0- initiated memory reads if a read initiated by the ehc is aborted, the ehc treats it as a fatal host error. the following actions are taken when this occurs: ? the host system erro r status bit is set ? the dma engines are halted after completing up to one more transaction on the usb interface ? if enabled (by the host system error enable), then an interrupt is generated ? if the status is master abort, then the received master abor t bit in configur ation space is set ? if the status is target abort, then the received target abort bi t in configuration space is set ? if enabled (by the serr enable bit in the func tion?s configuration space), then the signaled system error bit in configuration bit is set.
204 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.20.7 usb 2.0 power management 5.20.7.1 pause feature this feature allows platforms (e specially mobile systems) to d ynamically enter low-power states during brief periods when the system is idle (i.e., between keystrokes). this is useful for enabling power management features like intel speedstep technology in the ich6. the policies for entering these states typically are based on the recent histor y of system bus activity to incrementally enter deeper power management states . normally, when the ehc is enabled, it regularly accesses main memory while traversing the dma schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the usb ports that makes this unacceptable for the purpose of dynamic power manage ment. as a result, the ehci software drivers are allowe d to pause the ehc?s dma engines when it knows that the traffic patterns of the attached devices can afford th e delay. the pause only prevents the ehc from generating memory accesses; the sof packets conti nue to be generated on the usb ports (unlike the suspended state). 5.20.7.2 suspend feature the enhanced host controller interface (ehc i) for universal seri al bus specification , section 4.3 describes the details of port suspend and resume. 5.20.7.3 acpi device states the usb 2.0 function only supports the d0 and d3 pci power management states. notes regarding the ich6 implemen tation of the device states: 1. the ehc hardware does not inherently consume any more power when it is in the d0 state than it does in the d3 state. however, software is required to suspend or disable all ports prior to entering the d3 state such that the maximum power consumption is reduced. 2. in the d0 state, all implem ented ehc features are enabled. 3. in the d3 state, accesses to the ehc memory-map ped i/o range will mast er abort. note that, since the debug port uses the same memory range, the debug port is only operational when the ehc is in the d0 state. 4. in the d3 state, the ehc interrupt must never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power state field is written to d0 from d3, an in ternal reset is generated. see section ehc resets for general rules on the effects of this reset. 6. attempts to write any other value into the device power state field other than 00b (d0 state) and 11b (d3 state) will complete normally with out changing the current value in this field.
intel ? i/o controller hub 6 (ich6) family datasheet 205 functional description 5.20.7.4 acpi system states the ehc behavior as it relates to other power mana gement states in the sy stem is summarized in the following list: ? the system is always in the s0 state when th e ehc is in the d0 state. however, when the ehc is in the d3 state, the system may be in any power management state (including s0). ? when in d0, the pause feature (see section 5.20.7.1 ) enables dynamic processor low- power states to be entered. ? the pll in the ehc is di sabled when entering the s3 hot state (48 mhz clock stops), or the s3 cold /s4/s5 states (core power turns off). ? all core well logic is reset in the s3/s4/s5 states. 5.20.7.5 mobile considerations the ich6 usb 2.0 implementation does not behave di fferently in the mobile configurations versus the desktop configurations. however, some featur es may be especially useful for the mobile configurations. ? if a system (e.g., mobile) do es not implement all eight usb 2.0 ports, the ich6 provides mechanisms for changing the structural parameters of the ehc and hiding unused uhci controllers. see ich6 bios specification on how bios should configure the ich6. ? mobile systems may want to minimize the conditions that will wake the system. the ich6 implements the ?wake enable? bits in the port status and control registers, as specified in the ehci spec, for this purpose. ? mobile systems may want to cut suspend well power to some or all usb ports when in a low-power state. the ich6 implem ents the optional port wake capability register in the ehc configuration space for this plat form-specific information to be communicated to software. 5.20.8 interaction with uhci host controllers the enhanced host controller shares the eight us b ports with four uhci host controllers in the ich6. the uhc at d29:f0 shares ports 0 and 1; the uhc at d29:f1 shares ports 2 and 3; the uhc at d29:f2 shares ports 4 and 5; and the uhc at d29:f3 shares ports 6 and 7 with the ehc. there is very little interaction between the enhanced and the uhci controllers other than the multiplexing control which is provided as part of the ehc. figure 5-10 shows the usb port connections at a conceptual level.
206 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.20.8.1 port-routing logic integrated into the ehc functionality is port-rou ting logic, that performs the multiplexing between the uhci and ehci host controllers. the ich6 con ceptually implements this logic as described in section 4.2 of the enhanced host controller interface specification for universal serial bus, revision 1.0. if a device is connected that is not cap able of usb 2.0?s high-speed signaling protocol or if the ehci software drivers are not present as indicated by th e configured flag, then the uhci controller owns the port. owning the port means that the differential output is driven by the owner and the input stream is only visible to the owner. the host controller that is not the owner of the port internally s ees a disconnected port. note that the port-routing logic is the only block of logic within the ich6 that observes the physical (real) connect/dis connect information. the port stat us logic inside each of the host controllers observes the electrical connect/disco nnect information that is generated by the port-routing logic. only the differential signal pairs are multiplexed/demultiplexed between the uhci and ehci host controllers. the other usb functional signals are handled as follows: ? the overcurrent inputs (oc[7:0]#) are directly routed to both controllers. an overcurrent event is recorded in both c ontrollers? status registers. the port-routing logic is implemented in the su spend power well so th at re-enumeration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. the ich6 also allows the usb debug port traffic to be routed in and out of port #0. when in this mode, the enhanced host controller is the owner of port #0. figure 5-10. intel ? ich6-usb port connections uhci #3 (d29:f3) uchi #0 (d29:f0) uhci #1 (d29:f1) uhci #2 (d29:f2) enhanced host controller logic debug port port 7 port 3 port 4 port 5 port 6 port 2 port 1 port 0
intel ? i/o controller hub 6 (ich6) family datasheet 207 functional description 5.20.8.2 device connects the enhanced host controller inte rface specification for universa l serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are four general scenarios that are summarized below. 1. configure flag = 0 and a full-speed /low-speed-only device is connected ? in this case, the uhc is the owner of the po rt both before and after the connect occurs. the ehc (except for the port -routing logic) never sees the connect occur. the uhci driver handles the connection and initialization process. 2. configure flag = 0 and a high-s peed-capable device is connected ? in this case, the uhc is the owner of the po rt both before and after the connect occurs. the ehc (except for the port -routing logic) never sees the connect occur. the uhci driver handles the connection and initializatio n process. since the uhc does not perform the high-speed chirp handshake, the de vice operates in compatible mode. 3. configure flag = 1 and a full-speed /low-speed-only device is connected ? in this case, the ehc is the ow ner of the port before the c onnect occurs. the ehci driver handles the connection and performs the port re set. after the reset process completes, the ehc hardware has cleared (not set) the port enable bit in the ehc?s portsc register. the ehci driver then writes a 1 to the port owner bit in the same register, causing the uhc to see a connect event and the ehc to see an ?electrical? disconnect event. the uhci driver and hardware handle the connection and initialization process from that point on. the ehci driver and hardware handle the perceived disconnect. 4. configure flag = 1 and a high-s peed-capable device is connected ? in this case, the ehc is the owner of the port before, and remains the owner after, the connect occurs. the ehci driver handles the connection and performs the port reset. after the reset process completes, the ehc hardware has set the port enable bit in the ehc?s portsc register. the port is functional at this point. the uhc continues to see an unconnected port. 5.20.8.3 device disconnects the enhanced host controller inte rface specification for universa l serial bus, revision 1.0 describes the details of handling device connects in section 4.2. there are three general scenarios that are summarized below. 1. configure flag = 0 and the device is disconnected ? in this case, the uhc is the owner of the po rt both before and after the disconnect occurs. the ehc (except for the port -routing logic) never sees a device attached. the uhci driver handles disconnection process. 2. configure flag = 1 and a full-speed/low -speed-capable device is disconnected ? in this case, the uhc is the owner of th e port before the disconnect occurs. the disconnect is reported by the uhc and serv iced by the associated uhci driver. the port-routing logic in the ehc cluster forces the port owner bit to 0, indicating that the ehc owns the unconnected port. 3. configure flag = 1 and a high-spe ed-capable device is disconnected ? in this case, the ehc is the owner of the port before, and remains the owner after, the disconnect occurs. the ehci hardware and dr iver handle the disconnection process. the uhc never sees a device attached.
208 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.20.8.4 effect of reset s on port-routing logic as mentioned above, the port routing logic is implemented in the suspend power well so that remuneration and re-mapping of the usb ports is not required following entering and exiting a system sleep state in which the core power is turned off. 5.20.9 usb 2.0 legacy keyboard operation the ich6 must support the possibility of a keyboard downstream from either a full-speed/low- speed or a high-speed port. the description of the legacy keyboard support is unchanged from usb 1.1 (see section 5.19.8 ). the ehc provides the basic ability to generate smis on an interrupt ev ent, along with more sophisticated control of the generation of smis. 5.20.10 usb 2.0 based debug port the ich6 supports the elimination of the legacy com ports by providing the ability for new debugger software to interact with devices on a usb 2.0 port. high-level restrictions and features are: ? operational before usb 2.0 drivers are loaded. ? functions even when the port is disabled. ? works even though non-configured port is defa ult-routed to the uhci. note that the debug port can not be used to debug an issue that requires a full-speed/low-s peed device on port #0 using the uhci drivers. ? allows normal system usb 2.0 traffic in a system that may only have one usb port. ? debug port device (dpd) must be high-speed capable and connect directly to port #0 on ich6 systems (e.g., the dpd cannot be co nnected to port #0 thru a hub). ? debug port fifo always makes forward progress (a bad status on usb is simply presented back to software). ? the debug port fifo is only gi ven one usb access per microframe. reset event effect on configure flag effect on port owner bits suspend well reset cleared (0) set (1) core well reset no effect no effect d3-to-d0 reset no effect no effect hcreset cleared (0) set (1)
intel ? i/o controller hub 6 (ich6) family datasheet 209 functional description the debug port facilit ates operating system and device driv er debug. it allows the software to communicate with an external c onsole using a usb 2.0 connection. because the interface to this link does not go through the normal usb 2.0 stack , it allows communication with the external console during cases where the operating system is not loaded, the usb 2.0 software is broken, or where the usb 2.0 software is being debugged. specif ic features of this implementation of a debug port are: ? only works with an external usb 2.0 debug device (console) ? implemented for a specific po rt on the host controller ? operational anytime the port is not suspended and the host controller is in d0 power state. ? capability is interrupted when port is driving usb reset 5.20.10.1 theory of operation there are two operational m odes for the usb debug port: 1. mode 1 is when the usb port is in a disabled state from the viewpoint of a standard host controller driver. in mode 1, the debug port controller is required to generate a ?keepalive? packets less than 2 ms apart to keep the attached debug device from suspending. the keepalive packet should be a standalone 32-bit sync field. 2. mode 2 is when the host controller is running (i.e., host controller?s run/stop# bit is 1). in mode 2, the normal transmission of sof packet s will keep the debug device from suspending. behavioral rules 1. in both modes 1 and 2, the debug port controller must check for software requested debug transactions at least every 125 microseconds. 2. if the debug port is enabled by the debug driver, and the standard host controller driver resets the usb port, usb debug transacti ons are held off for the duration of the reset and until after the first sof is sent. 3. if the standard host controller driver suspe nds the usb port, then usb debug transactions are held off for the duration of the suspend/resume sequence and until after the first sof is sent. 4. the enabled_cnt bit in the debug register space is inde pendent of the similar port control bit in the associated port status and control register.
210 intel ? i/o controller hub 6 (i ch6) family datasheet functional description table 5-46 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated port status and control register. 5.20.10.1.1 out transactions an out transaction sends data to the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is set the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ? data_buffer[63:0] ? token_pid_cnt[7:0] ? send_pid_cnt[15:8] ? data_len_cnt ? write_read#_cnt (note: this will always be 1 for out transactions) ? go_cnt (note: this will always be 1 to initiate the transaction) table 5-46. debug port behavior owner_cnt enabled_ct port enable run / stop suspend debug port behavior 0xxxx debug port is not being used. normal operation. 10xxx debug port is not being used. normal operation. 1100x debug port in mode 1. sync keepalives sent plus debug traffic 1101x debug port in mode 2. sof (and only sof) is sent as keepalive. debug traffic is also sent. note that no other normal traffic is sent out this port, because the port is not enabled. 11100 illegal. host controller driver should never put controller into this state (enabled, not running and not suspended). 11101 port is suspended. no debug traffic sent. 11110 debug port in mode 2. debug traffic is interspersed with normal traffic. 11111 port is suspended. no debug traffic sent.
intel ? i/o controller hub 6 (ich6) family datasheet 211 functional description 2. the debug port controller sends a token packet consisting of: ?sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field 3. after sending the token packet, the debug port controller sends a data packet consisting of: ?sync ? send_pid_cnt field ? the number of data bytes indicated in data_len_cnt from the data_buffer ? 16-bit crc note: a data_len_cnt value of 0 is valid in which case no data bytes would be included in the packet. 4. after sending the data packet, the controller waits for a handshake response from the debug device. ? if a handshake is received, the debug port controller: ? a. places the received pid in the received_pid_sts field ? b. resets the error_good#_sts bit ? c. sets the done_sts bit ? if no handshake pid is received, the debug port controller: ? a. sets the exception_sts field to 001b ? b. sets the error_good#_sts bit ? c. sets the done_sts bit 5.20.10.1.2 in transactions an in transaction receives data from the debug device. it can occur only when the following are true: ? the debug port is enabled ? the debug software sets the go_cnt bit ? the write_read#_cnt bit is reset the sequence of the transaction is: 1. software sets the appropriate values in the following bits: ? usb_address_cnf ? usb_endpoint_cnf ? token_pid_cnt[7:0] ? data_len_cnt ? write_read#_cnt (note: this will always be 0 for in transactions) ? go_cnt (note: this will always be 1 to initiate the transaction)
212 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 2. the debug port controller sends a token packet consisting of: ? sync ? token_pid_cnt field ? usb_address_cnt field ? usb_endpoint_cnt field ? 5-bit crc field. 3. after sending the token packet, the debug port controller waits for a response from the debug device. if a response is received: ? the received pid is placed into the received_pid_sts field ? any subsequent bytes are placed into the data_buffer ? the data_len_cnt field is updated to show the number of bytes that were received after the pid. 4. if valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: ? resets the error_good#_sts bit ? sets the done_sts bit 5. if valid packet was received fr om the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: ? transmits an ack handshake packet ? resets the error_good#_sts bit ? sets the done_sts bit 6. if no valid packet is received, then the debug port controller: ? sets the exception_sts field to 001b ? sets the error_good#_sts bit ? sets the done_sts bit. 5.20.10.1.3 debug software enabling the debug port there are two mutually exclusive conditions that debu g software must address as part of its startup processing: ? the ehci has been initial ized by system software ? the ehci has not been init ialized by system software debug software can determine the current ?ini tialized? state of the eh ci by examining the configure flag in the ehci usb 2. 0 command register. if this flag is set, then system software has initialized the ehci. otherwise the ehci should not be considered initialized. debug software will initialize the debug port registers depending on the state the ehci. however, before this can be accomplished, debug software must determine wh ich root usb port is designated as the debug port.
intel ? i/o controller hub 6 (ich6) family datasheet 213 functional description determining the debug port debug software can easily determine which usb root port has been designated as the debug port by examining bits 20:23 of the ehci host controll er structural parameters register. this 4-bit field represents the numeric value assigned to the debug port (i.e., 0000=port 0). debug software startup with non-initialized ehci debug software can attempt to use the debug port if after setting the owner_cnt bit, the current connect status bit in the appropriate (s ee determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. if a device is connected to the port , then debug software must reset/enable the port. debug software does this by setting and then clearing the port re set bit the portsc register. to guarantee a successful reset, debug software should wait at least 50 ms before clearing the port reset bit. due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. software must not continue until this bit reads 0. if a high-speed device is attached, the ehci will automatically set the port enabled/disabled bit in the portsc register and the debug software can proceed. debug software should set the enabled_cnt bit in the debug port control/status register, and then reset (clear) the port enabled/disabled bit in the portsc register (so th at the system host contro ller driver does not see an enabled port when it is first loaded). debug software startup with initialized ehci debug software can attempt to use the debug port if the current connect status bit in the appropriate (see determining the debug port) portsc register is set. if the current connect status bit is not set, then debug software may c hoose to terminate or it may choose to wait until a device is connected. if a device is connected, then debug software must set the owner_cnt bit and then the enabled_cnt bit in the debug port control/status register. determining debug peripheral presence after enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. if all attempts result in an error (exception bits in the debug port control/status re gister indicates a transa ction error), then the attached device is not a debug peripheral. if the debug port peripheral is not present, then debug software may choose to terminate or it may choo se to wait until a debug peripheral is connected.
214 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.21 smbus controller (d31:f3) the ich6 provides a system management bus (smbus) 2.0 compliant host controller as well as a smbus slave interface. the host controller provi des a mechanism for the processor to initiate communications with smbus peripherals (slaves). the ich6 is also capable of operating in a mode in which it can communicate with i 2 c compatible devices. the ich6 can perform smbus messages with ei ther packet error checking (pec) enabled or disabled. the actual pec calculation and checking is performed in hardware by the ich6. the slave interface allows an external master to r ead from or write to th e ich6. write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. the ich6?s internal host controller cannot access the ich6?s internal slave interface. the ich6 smbus logic exists in device 31:func tion 3 configuration space, and consists of a transmit data path, and host controller. the transmit data path provides the data flow logic needed to implement the seven different smbus command protocols and is controlled by the host controller. the ich6 smbus controller logic is clocked by rtc clock. the smbus address resolution protocol (arp) is supported by using the existing host controller commands through software, except for the new ho st notify command (which is actually a received message). the programming model of the host controller is combined into two portions: a pci configuration portion, and a system i/o mapped portion. all static configuration, such as th e i/o base address, is done via the pci configuration space. real-time programming of the host interface is done in system i/o space. the ich6 smbus host controller ch ecks for parity errors as a target . if an error is detected, the detected parity error bit in the pci status register (device 31:function 3:offset 06h:bit 15) is set. if bit 6 and bit 8 of the pci command register (device 31:function 3:offs et 04h) are set, an serr# is generated and the signaled serr# bit in the pci status register (bit 14) is set. unless otherwise specified, all of the smbus logic and its regist ers are reset by either rsmrst# or a similar reset via cf9h. 5.21.1 host controller the smbus host controller is used to send comman ds to other smbus slave devices. software sets up the host controller with an addr ess, command, and, for writes, data and optional pec; and then tells the controller to start. when the contro ller has finished transmitting data on writes, or receiving data on reads, it generates an smi# or interrupt, if enabled. the host controller supports eight comman d protocols of the smbus interface (see system management bus (smbus) specification, version 2.0 ): quick command, send byte, receive byte, write byte/word, read byte/word, process call, block read/write, block write?block read process call, and host notify. the smbus host controller requires that the various data and command fields be setup for the type of command to be sent. when so ftware sets the start bit, the smbus host controller performs the requested transaction, and in terrupts the processor (or generate s an smi#) when the transaction is completed. once a start command has been issu ed, the values of the ?active registers? (host control, host command, transmit slave address, data 0, data 1) should not be changed or read
intel ? i/o controller hub 6 (ich6) family datasheet 215 functional description until the interrupt status bit (intr) has been set (indicating the completion of the command). any register values needed for computation purposes should be saved prior to issuing of a new command, as the smbus host co ntroller updates all registers while completing the new command. using the smb host controller to send commands to the ich6?s smb slave port is supported. the ich6 is fully compliant with the system management bus (smbus) specification, version 2.0 . slave functionality, including the host notify protocol, is available on the smbus pins. the smlink and smbus signals should not be tied together externally. 5.21.1.1 command protocols in all of the following commands, a host status register is used to determine the progress of the command. while the command is in operation, the host_busy bit is set. if the command completes successfully, the intr bit will be set in the host status register . if the device does not respond with an acknowledge, and the transaction ti mes out, the dev_err bit is set. if software sets the kill bit in the host control register while the command is running, the transaction will stop and the failed bit will be set. quick command when programmed for a quick command, the transm it slave address register is sent. the pec byte is never appended to the quick protocol. so ftware should force the pec_en bit to 0 when performing the quick command. software must force the i2c_en bit to 0 when running this command. see section 5.5.1 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. send byte / receive byte for the send byte command, the transmit slav e address and device comm and registers are sent for the receive byte command, the transmit slave address register is sent . the data received is stored in the data0 register. software must force the i2c_en bit to 0 when running this command. the receive byte is similar to a send byte, the only difference is the directio n of data transfer. see sections 5.5.2 and 5.5.3 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. write byte/word the first byte of a write byte/word access is the co mmand code. the next 1 or 2 bytes are the data to be written. when programmed for a write byte/word command, the transmit slave address, device command, and data0 registers are sent. in a ddition, the data1 register is sent on a write word command. software must force the i2c_en bit to 0 when running this command. see section 5.5.4 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. read byte/word reading data is slightly more complicated than writing data. first the ich6 must write a command to the slave device. then it must follow that command with a rep eated start condition to denote a read from that device's address. th e slave then returns 1 or 2 bytes of data. software must force the i2c_en bit to 0 when running this command.
216 intel ? i/o controller hub 6 (i ch6) family datasheet functional description when programmed for the read byte/word command, the tran smit slave address and device command registers are sent. data is received into the data0 on the read byte, and the dat0 and data1 registers on the read word. see section 5.5.5 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. process call the process call is so named because a command se nds data and waits for the slave to return a value dependent on that data. the protocol is simply a write word followed by a read word, but without a second command or stop condition. when programmed for the process call command, th e ich6 transmits the tr ansmit slave address, host command, data0 and data1 registers. data received from the device is stored in the data0 and data1 registers. the process call co mmand with i2c_en set and the pec_en bit set produces undefined results. software must for ce either i2c_en or pec_en to 0 when running this command. see section 5.5.6 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for process call command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. note: if the i2c_en bit is set, the protocol sequence changes slightly: the command code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). block read/write the ich6 contains a 32-byte buffer for read and write data that can be enabled by setting bit 1 of the auxiliary control regist er at offset 0dh in i/o space, as o pposed to a single byte of buffering. this 32-byte buffer is filled with write data before transmission, and filled with read data on reception. in the ich6, the interrupt is generated only after a tran smission or receptio n of 32 bytes, or when the entire byte coun t has been transmitted/received. the byte count field is transmitted but ignored by the ich6 as software will end the transfer after all bytes it cares about have been sent or received. for a block write, software must either force the i2c_en bit or both the pec_en and aac bits to 0 when running this command. the block write begins with a slave address and a write condition. after the command code the ich6 issues a byte count describing how many more bytes will follow in the message. if a slave had 20 bytes to send, the first byte would be th e number 20 (14h), followed by 20 bytes of data. the byte count may not be 0. a block read or write is allowed to transfer a maximum of 32 data bytes. when programmed for a block write command, the transmit slave address, device command, and data0 (count) registers are sent. data is then sent from the block data byte register; the total data sent being the value stored in the data0 register. on block read commands, the first byte received is stored in the data0 register, and the re maining bytes are stored in the block data byte register. see section 5.5.7 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. note: for block write, if the i2c_en bit is set, the format of the command changes slightly. the ich6 will still send the number of bytes (on writes) or recei ve the number of bytes (on reads) indicated in the data0 register. however, it will not send the contents of the data0 register as part of the
intel ? i/o controller hub 6 (ich6) family datasheet 217 functional description message. also, the block write protocol sequence changes slightly: the byte count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence). i 2 c read this command allows the ich6 to perform block reads to certain i 2 c devices, such as serial e 2 proms. the smbus block read supports the 7-bit addressing mode only. however, this does not allow access to devices using the i 2 c ?combined format? that has data bytes after the address. typically these data bytes co rrespond to an offset (address) within the serial memory chips. note: this command is supported independent of the setting of the i2c_en bit. the i 2 c read command with the pec_en bit set produces undefined results. software must force both the pec_en and aac bit to 0 when running this command. for i 2 c read command, the value written into bit 0 of the transmit slave address register (smb i/o register, offset 04h) needs to be 0. the format that is used fo r the command is shown in table 5-47 . the ich6 will continue reading data from the peripheral until the nak is received. table 5-47. i 2 c block read bit description 1start 8:2 slave address ? 7 bits 9write 10 acknowledge from slave 18:11 send data1 register 19 acknowledge from slave 20 repeated start 27:21 slave address ? 7 bits 28 read 29 acknowledge from slave 37:30 data byte 1 from slave ? 8 bits 38 acknowledge 46:39 data byte 2 from slave ? 8 bits 47 acknowledge ? data bytes from slave / acknowledge ? data byte n from slave ? 8 bits ? not acknowledge ?stop
218 intel ? i/o controller hub 6 (i ch6) family datasheet functional description block write?block read process call the block write-block read proces s call is a two-part message. the call begins with a slave address and a write condition. after the command code the ho st issues a write byte count (m) that describes how many more bytes will be written in the first part of the message. if a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. the write byte count (m) cannot be 0. the second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a read bit. the next byte is th e read byte count (n), which may differ from the write byte count (m). the read byte count (n) cannot be 0. the combined data payload must not exceed 32 bytes. the byte lengt h restrictions of this process call are summarized as follows: ? m 1 byte ? n 1 byte ? m + n 32 bytes the read byte count does not include the pec byte. the pec is computed on the total message beginning with the first slave ad dress and using the normal pec computational rules. it is highly recommended that a pec byte be used with the block write-bloc k read process call. software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. note that there is no stop condition before the repeated start condition, and that a nack signifies the end of the read transfer. note: e32b bit in the auxiliary control register must be set when using this protocol. see section 5.5.8 of the system management bus (smbus) specification, version 2.0 for the format of the protocol. 5.21.2 bus arbitration several masters may attempt to get on the bus at the same time by driving the smbdata line low to signal a start condition. the ich6 continuously monitors the smbdata line. when the ich6 is attempting to drive the bus to a 1 by letting go of the smbdata line, and it samples smbdata low, then some other master is driving the bus and the ich6 will stop transferring data. if the ich6 sees that it has lost arbitration, the condition is called a collision. the ich6 will set the bus_err bit in the host status register, and if enabled, genera te an interrupt or smi#. the processor is responsible fo r restarting the transaction. when the ich6 is a smbus master, it drives th e clock. when the ich6 is sending address or command as an smbus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. it will not start toggling the clock until the start or stop condition meets proper setup and hold time. the ich6 will also guarantee minimum time between smbus transactions as a master. note: the ich6 supports the same arbitration protocol for both the smbus and the system management (smlink) interfaces.
intel ? i/o controller hub 6 (ich6) family datasheet 219 functional description 5.21.3 bus timing 5.21.3.1 clock stretching some devices may not be able to handle their clock toggling at the rate that the ich6 as an smbus master would like. they have the capability of stretching the low ti me of the clock. when the ich6 attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. the ich6 monitors the smbus clock line after it re leases the bus to determ ine whether to enable the counter for the high time of the clock. while the bus is still low, the high time counter must not be enabled. similarly, the low period of the clock can be stretched by an smbus master if it is not ready to send or receive data. 5.21.3.2 bus time out (intel ? ich6 as smbus master) if there is an error in the trans action, such that an smbus devi ce does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. the ich6 will discard the cycle and se t the dev_err bit. the time out minimum is 25 ms (800 rtc clocks). the time-out counter inside the ich6 will st art after the last bit of data is transferred by the ich6 and it is waiting for a response. the 25 ms timeout counter will not count under the following conditions: 1. byte_done_status bit (smbus i/o offset 00h, bit 7) is set 2. the second_to_sts bit (tco i/o offset 06h, bit 1) is not set (this indicates that the system has not locked up)
220 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.21.4 interrupts / smi# the ich6 smbus controller uses pirqb# as it s interrupt pin. howe ver, the system can alternatively be set up to generate smi# instead of an interrupt, by setting the smbus_smi_en bit (device 31:function 0:offset 40h:bit 1). table 5-49 and table 5-50 specify how the various enable bits in the smbus function control the generation of the interrupt, host and slave smi, an d wake internal signals. the rows in the tables are additive, which means th at if more than one row is true for a particular scenario then the results for all of the activat ed rows will occur. table 5-48. enable for smbalert# event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit 1) smbalert_dis (slave command i/o register, offset 11h, bit 2) result smbalert# asserted low (always reported in host status register, bit 5) x x x wake generated x1 0 slave smi# generated (smbus_smi_sts) 1 0 0 interrupt generated table 5-49. enables for smbus slave write and smbus host events event intren (host control i/o register, offset 02h, bit 0) smb_smi_en (host configuration register, d31:f3:offset 40h, bit1) event slave write to wake/ smi# command xx wake generated when asleep. slave smi# generated when awake (smbus_smi_sts). slave write to smlink_slave_smi command xx slave smi# generated when in the s0 state (smbus_smi_sts) any combination of host status register [4:1] asserted 0 x none 1 0 interrupt generated 1 1 host smi# generated table 5-50. enables for the host notify command host_notify_intren (slave control i/o register, offset 11h, bit 0) smb_smi_en (host configuration register, d31:f3:off40h, bit 1) host_notify_wken (slave control i/o register, offset 11h, bit 1) result 0 x 0 none x x 1 wake generated 1 0 x interrupt generated 11x slave smi# generated (smbus_smi_sts)
intel ? i/o controller hub 6 (ich6) family datasheet 221 functional description 5.21.5 smbalert# smbalert# is multiplexed with gpi[11]. when en able and the signal is asserted, the ich6 can generate an interrupt, an smi#, or a wake event from s1 ? s5. note: any event on smbalert# (regardless whether it is programmed as a gp i or not), causes the event message to be se nt in heartbeat mode. 5.21.6 smbus crc generation and checking if the aac bit is set in the auxiliary control regi ster, the ich6 automatically calculates and drives crc at the end of the transmitted packet for write cycles, and will check the crc for read cycles. it will not transmit the contents of the pec register for crc. the pec bit must not be set in the host control register if this bit is set, or unspecified behavior will result. if the read cycle results in a crc error, the dev_ err bit and the crce bit in the auxiliary status register at offset 0ch will be set. 5.21.7 smbus slave interface the ich6?s smbus slave interface is accessed via the smbus. the smbus slave logic will not generate or handle receiving the pec byte and will only act as a legacy alerting protocol device. the slave interface allows the ich6 to decode cycles, and allows an external microcontroller to perform specific actions. key feat ures and capabilities include: ? supports decode of three types of messages: byte write, byte read, and host notify. ? receive slave address register: th is is the address that the ich6 decodes. a default value is provided so that the slave interface can be used without the processor having to pr ogram this register. ? receive slave data register in the smbus i/o space that in cludes the data written by the external microcontroller. ? registers that the external microcontroller can read to get the state of the ich6. ? status bits to indicate that the smbus slave logic caused an interrupt or smi# due to the reception of a message that matched the slave address. ? bit 0 of the slave status regist er for the host notify command ? bit 16 of the smi status register ( section 10.8.3.13 ) for all others if a master leaves the clock and data bits of th e smbus interface at 1 for 50 s or more in the middle of a cycle, the ich6 slave logic's behavior is undefined. this is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. note: when an external microcont roller accesses the smbus slav e interface over the smbus a translation in the address is n eeded to accommodate the least si gnificant bit used for read/write control. for example, if the ich6 slave address ( rcv_slva) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read).
222 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.21.7.1 format of slave write cycle the external master performs byte write comm ands to the ich6 smbus slave interface. the ?command? field (bits 11 : 18) indicate which register is bein g accessed. the data field (bits 20 : 27) indicate the value that should be written to that register. table 5-51 has the values associated with the registers. note: the external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. t he ich6 overwrites the old value with any new value received. a race condition is pos sible where the new value is being written to the register just at the time it is being read. i ch6 will not attempt to cover this race condition (i.e., unpredictable results in this case). . table 5-51. slave write registers register function 0 command register. see table 5-52 below for legal values written to this register. 1?3 reserved 4 data message byte 0 5 data message byte 1 6?7 reserved 8 reserved 9?ffh reserved table 5-52. command types (sheet 1 of 2) command type description 0reserved 1 wake/smi#. this command wakes the system if it is not already awake. if system is already awake, an smi# is generated. note: the smb_wak_sts bit will be set by this command, even if the system is already awake. the smi handler should then clear this bit. 2 unconditional powerdown. this command sets the pwrbtnor_sts bit, and has the same effect as the powerbutton override occurring. 3 hard reset without cycling: this command causes a hard reset of the system (does not include cycling of the power s upply). this is equivalent to a wr ite to the cf9h register with bits 2:1 set to 1, but bit 3 set to 0. 4 hard reset system. this command causes a hard reset of the system (including cycling of the power supply). this is equival ent to a write to the cf9h register with bits 3:1 set to 1. 5 disable the tco messages. this command will disable the intel ? ich6 from sending heartbeat and event messages (as described in section 5.15.2 ). once this command has been executed, heartbeat and event message reporting can only be re-enabled by assertion and de- assertion of the rsmrst# signal. 6 wd reload: reload watchdog timer. 7reserved
intel ? i/o controller hub 6 (ich6) family datasheet 223 functional description 5.21.7.2 format of read command the external master performs byte read co mmands to the ich6 smbus slave i/f. the ?command? field (bits 18 : 11) indicate which register is be ing accessed. the data field (bits 30 : 37) contain the value that should be read from that register. table 5-53 shows the read cycle format. table 5-54 shows the register mapping for the data byte. 8 smlink_slv_smi. when ich6 detects this command type while in the s0 state, it sets the smlink_slv_smi_sts bit (see section 10.9.5 ). this command should only be used if the system is in an s0 state. if the message is received during s1?s5 states, the ich6 acknowledges it, but the smlink_s lv_smi_sts bit does not get set. note: it is possible that the system tr ansitions out of the s0 state at the same time that the smlink_slv_smi command is received. in this case, the smlink_slv_smi_sts bit may get set but not serviced before the system goes to sleep. once the system returns to s0, the smi associated with this bit woul d then be generated. software must be able to handle this scenario. 9?ffh reserved table 5-52. command types (sheet 2 of 2) command type description table 5-53. read cycle format bit description driven by comment 1 start external microcontroller 8:2 slave address - 7 bits external microcontroller must match value in receive slave address register 9 write external microcontroller always 0 10 ack intel ? ich6 18:11 command code - 8 bits external microcontroller indicates which register is being accessed see ta b l e 5 - 5 4 19 ack ich6 20 repeated start external microcontroller 27:21 slave address - 7 bits external microcontroller must match value in receive slave address register 28 read external microcontroller always 1 29 ack ich6 37:30 datay byte ich6 value depends on register being accessed. see ta b l e 5 - 5 4 38 not ack external microcontroller 39 stop external microcontroller
224 intel ? i/o controller hub 6 (i ch6) family datasheet functional description table 5-54. data values for slave read registers register bits description 07:0reserved 12:0 system power state 000 = s0 001 = s1 010 = reserved 011 = s3 100 = s4 101 = s5 110 = reserved 111 = reserved 17:3reserved 2 3:0 frequency strap register 27:4reserved 3 5:0 watchdog timer current value 37:6reserved 40 1 = the intruder detect (intrd_det) bit is set. this indicates that the system cover has probably been opened. 41 1 = bti temperature event occurred. this bit will be set if the intel ? ich6?s thrm# input signal is active. n eed to take after polarity control. 42 boot-status. this bit will be 1 when t he processor does not fetch the first instruction. 43 this bit will be set after the tco timer times out a second time (both timeout and second_to_sts bits set). 46:4reserved 47 the bit will reflect the state of the gpi11/smbalert# signal, and will depend on the gp_inv11 bit. it does not matter if the pin is configured as gpi11 or smbalert#. ? if the gp_inv11 bit is 1, the value of register 4 bit 7 will equal the level of the gpi11/smbalert# pin (high = 1, low = 0). ? if the gp_inv11 bit is 0, the value of register 4 bit 7 will equal the inverse of the level of the gpi11/smbalert# pin (high = 1, low = 0). 50 unprogrammed flash bios bit. this bit will be 1 to indicate that the first bios fetch returned ffh, that indicates t hat the flash bios is probably blank. 51reserved 52 processor power failure status. 1 if the cpupwr_flr bit in the gen_pmcon_2 register is set. 57:3reserved 6 7:0 contents of the message 1 register. 7 7:0 contents of the message 2 register. 8 7:0 contents of the wdstatus register. 9-ffh 7:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 225 functional description 5.21.7.2.1 behavioral notes according to smbus protocol, read and write messages always begin with a start bit ? address ? write bit sequence. when the ich6 detects that the address matche s the value in the receive slave address register, it will assume that the protocol is always followed and ignore the write bit (bit 9) and signal an acknowledge during bit 10. in other words, if a start ? address ? read occurs (which is illegal for smbus read or write protocol), an d the address matches the ich6?s slave address, the ich6 will still grab the cycle. also according to smbus protocol, a r ead cycle contains a repeated start ? address ? read sequence beginning at bit 20. once again, if the address matches the ich6?s receive slave address, it will assume that the protocol is foll owed, ignore bit 28, and proceed with the slave read cycle. note: an external microcontroll er must not attempt to access the ich6 ?s smbus slave logic until at least 1 second after both rtcrst# and rsmrst# are de-asserted (high). 5.21.7.3 format of host notify command the ich6 tracks and responds to the standard host notify command as specified in the system management bus (smbus) specification, version 2.0 . the host address for this command is fixed to 0001000b. if the ich6 already has data for a previously-received host notify command that has not been serviced yet by the host software (as indicated by the host_no tify_sts bit), then it will nack following the host address byte of the protocol. this allows the host to communicate non-acceptance to the master and retain the host no tify address and data values for the previous cycle until host software completely services the interrupt. note: host software must always clear the host_notif y_sts bit after completing any necessary reads of the address and data registers. table 5-55 shows the host notify format. table 5-55. host notify format bit description driven by comment 1 start external master 8:2 smb host address ? 7 bits external master always 0001_000 9 write external master always 0 10 ack (or nack) intel ? ich6 ich6 nacks if host_notify_sts is 1 17:11 device address ? 7 bits external master indicates the address of the master; loaded into the notify device address register 18 unused ? always 0 external master 7-bit-only address; this bit is inserted to complete the byte 19 ack ich6 27:20 data byte low ? 8 bits external master loaded into the notify data low byte register 28 ack ich6 36:29 data byte high ? 8 bits external master loaded into the notify data high byte register 37 ack ich6 38 stop external master
226 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.22 ac ?97 controller (audio d30:f2, modem d30:f3) note: all references to ac ?97 in this document refer to the ac ?97 specification , version 2.3 . for further information on the operation of the ac-link protocol, see the ac ?97 specification , version 2.3 . the ich6 ac ?97 contro ller features include: ? independent pci functions for audio and modem. ? independent bus master logic for dual microphone input, dual pcm audio input (2-channel stereo per input), pcm audio output (2-, 4- or 6-channel audio), modem input, modem output and s/pdif output. ? 20-bit sample resolution ? multiple sample rates up to 48 khz ? support for 16 codec-implemented gpios ? single modem line ? configure up to three codecs with three acz_sdin pins table 5-56 shows a detailed list of features supported by the ich6 ac ?97 digital controller. . table 5-56. features supported by intel ? ich6 (sheet 1 of 2) feature description system interface ? isochronous low latency bus master memory interface ? scatter/gather support for word-aligned buffers in memory (all mono or stereo 20-bit and 16-bit data types are supported, no 8-bit data types are supported) ? data buffer size in system memory from 3 to 65535 samples per input ? data buffer size in system memory from 0 to 65535 samples per output ? independent pci audio and modem functions with configuration and i/o spaces ? ac ?97 codec registers are shadow ed in system memory via driver ? ac ?97 codec register accesses are seri alized via semaphore bit in pci i/o space (new accesses are not allowed while a prior access is still in progress) power management ? power management via pci power management pci audio function ? read/write access to audio codec regist ers 00h?3ah and vendor registers 5ah?7eh ? 20-bit stereo pcm output, up to 48 khz (l,r, center, sub-woofer, l-rear and r-rear channels on slots 3,4,6,7,8,9,10,11) ? 16-bit stereo pcm input, up to 48 khz (l,r channels on slots 3,4) ? 16-bit mono mic in w/ or w/o mono mix, up to 48 khz (l,r channel, slots 3,4) (mono mix supports mono hardware aec reference for speakerphone) ? 16-bit mono pcm input, up to 48 khz from dedicated mic adc (slot 6) (supports speech recognition or stereo hardware aec ref for speakerphone) ? during cold reset acz_rst# is held low until after post and software de-assertion of acz_rst# (supports passive pc_ beep to speaker connection during post)
intel ? i/o controller hub 6 (ich6) family datasheet 227 functional description note: throughout this document, references to d31:f5 indicate that the audio function exists in pci device 31, function 5. references to d31:f6 indicate that the modem function exists in pci device 31, function 6. note: throughout this document references to tertiary, th ird, or triple codecs refer to the third codec in the system connected to the acz_sdin2 pin. the ac ?97 v2.3 specification refers to non-primary codecs as multiple secondary codecs. to avoid co nfusion and excess verbiage, this datasheet refers to it as the third or tertiary codec. pci modem function ? read/write access to modem codec registers 3ch?58h and vendor registers 5ah?7eh ? 16-bit mono modem line 1 output and input, up to 48 khz (slot 5) ? low latency gpio[15:0] via hardwired update between slot 12 and pci i/o register ? programmable pci interrupt on modem gpio input changes via slot 12 gpio_int ? sci event generation on acz_sdin[2:0] wake-up signal ac-link ? ac ?97 2.3 ac-link interface ? variable sample rate output support via ac ?97 slotreq protocol (slots 3,4,5,6,7,8,9,10,11) ? variable sample rate input support via monito ring of slot valid tag bits (slots 3,4,5,6) ? 3.3 v digital operation meets ac ?97 2.3 dc switching levels ? ac-link i/o driver capability meets ac ?97 2.3 triple codec specifications ? codec register status reads must be returned with data in the next ac-link frame, per ac ?97 v2.3 specification . multiple codec ? triple codec addressing: all ac ?97 audio c odec register accesses are addressable to codec id 00 (primary), codec id 01 (s econdary), or codec id 10 (tertiary). ? modem codec addressing: all ac ?97 m odem codec register accesses are addressable to codec id 00 (prima ry) or codec id 01 (secondary). ? triple codec receive capabi lity via acz_sdin[2:0] pins (acz_sdin[2:0] frames are internally validated, synchroni zed, and or?d depending on the steer enable bit status in the sdm register) ? acz_sdin mapping to dma engine mapping ca pability allows for simultaneous input from two different audio codecs. notes: 1. audio codec ids are remappable and not limited to 00,01,10. 2. modem codec ids are remappable and limited to 00, 01. 3. when using multiple codecs, the modem codec must be id 01. figure 5-11. intel ? ich6-based audio codec ?97 specification, version 2.3 table 5-56. features supported by intel ? ich6 (sheet 2 of 2) feature description a udio in (record) a udio out (6 channel playback) pc mic.2 s/pdif* output mic.1 modem
228 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.22.1 pci power management this power management section applies for all ac ?97 controller functions. after a power management event is detected, the ac ?97 cont roller wakes the host system. the following sections describe these events and the ac ?97 controller power states. device power states the ac ?97 controller supports d0 and d3 pci power management states. the following are notes regarding the ac ?97 controller im plementation of the device states: 1. the ac ?97 controller hardware does not inherently consume any more power when it is in the d0 state than it does in d3 st ate. however, software can halt the dma engine prior to entering these low power states such that the maximum power consumption is reduced. 2. in the d0 state, all implemented ac ?97 controller feat ures are enabled. 3. in d3 state, accesses to the ac ?97 controller memory-mapped or i/o range results in master abort. 4. in d3 state, the ac ?97 controller interrupt will never assert for any reason. the internal pme# signal is used to signal wake events, etc. 5. when the device power stat e field is written from d3 hot to d0, an internal reset is generated. see section 17.1 for general rules on the effects of this reset. 6. ac97 sts bit is set only when the audio or modem resume events were detected and their respective pme enable bits were set. 7. gpio status change interrupt no longer has a direct path to the ac97 sts bit. this causes a wake up event only if the modem controller was in d3 8. resume events on acz_sdin[2:0] cause resume in terrupt status bits to be set only if their respective controllers are not in d3. 9. edge detect logic prevents the interrupts from being asserted in case the ac97 controller is switched from d3 to d0 after a wake event. 10. once the interrupt status bits are set, they will cause pirqb# if their respective enable bits were set. one of the audio or the modem drivers will handle the interrupt. 5.22.2 ac-link overview the ich6 is an ac ?97 2.3 contro ller that communicates with compan ion codecs via a digital serial link called the ac-link. all digital audio/mode m streams and command/st atus information is communicated over the ac-link. the ac-link is a bi-directional, serial pcm digital stream. it handles multiple input and output data streams, as well as control register accesses, employing a time divi sion multiplexed (tdm) scheme. the ac-link architecture provides for data transfer through indivi dual frames transmitted in a serial fashion. each frame is divided into 12 outgoing and 12 incoming data streams, or slots. the architecture of the ich6 ac -link allows a maximum of th ree codecs to be connected. figure 5-12 shows a three codec topology of the ac-link for the ich6. the ac-link consists of a five signal interface between the ich6 and codec(s). note: the ich6?s ac ?97 controller shares the signal interface with the intel high definition audio controller. however, only one controller may be enabled at a time.
intel ? i/o controller hub 6 (ich6) family datasheet 229 functional description ich6 core well outputs may be used as strapping options for the ich6, sampled during system reset. these signals may have weak pullups/pulldow ns; however, this will not interfere with link operation. ich6 inputs integrate weak pulldowns to prevent floating traces when a secondary and/ or tertiary codec is not attached. wh en the shut off bit in the control register is set, all buffers will be turned off and the pins will be held in a steady state, based on these pullups/pulldowns. acz_bit_clk is fixed at 12.288 mhz and is s ourced by the primary codec. it provides the necessary clocking to support the tw elve 20-bit time slots. ac-link serial data is transitioned on each rising edge of acz_bit_clk. the receiver of ac-link data samples each serial bit on the falling edge of acz_bit_clk. if acz_bit_clk makes no transitions for four consecutive pci clocks, the ich6 assumes the primary codec is not present or not working. it sets bit 28 of the global status register (i/o offset 30h). all accesses to cod ec registers with this bit set will return data of ffh to prevent system hangs. figure 5-12. ac ?97 2.3 controller-codec connection intel ? ich6 primary codec ac / mc / amc ac97 ich6 codec conn acz_sdin2 acz_sdin1 acz_rst# acz_sdout acz_sync acz_bit_clk secondary codec ac / mc / amc tertiary codec ac / mc / amc acz_sdin0
230 intel ? i/o controller hub 6 (i ch6) family datasheet functional description synchronization of all ac-link data transactions is signaled by the ac ?97 controller via the acz_sync signal, as shown in figure 5-13 . the primary codec drives th e serial bit clock onto the ac-link, which the ac ?97 controller then qualifie s with the acz_sync signal to construct data frames. acz_sync, fixed at 48 khz, is derived by dividing down acz_bit_clk. acz_sync remains high for a total duration of 16 acz_bi t_clk at the beginning of each frame. the portion of the frame where acz_sync is high is define d as the tag phase. the remainder of the frame where acz_sync is low is defined as the data pha se. each data bit is sampled on the falling edge of acz_bit_clk. the ich6 has three acz_sdin pins allowing a single, dual, or trip le codec configuration. when multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any acz_sdin line. the ich6 does not distinguish between codecs on its acz_sdin[2:0] pins, however the registers do distinguish between acz_sdin[0], acz_sdin[1], and acz_sdin[2] for wake events, etc. if using a modem codec it is recommended to connect it to acz_sdin1. see your platform design guide for a matrix of valid codec configurations. the ich6 does not support optional test modes as outlined in the ac ?97 specification, version 2.3 . 5.22.2.1 register access in the ich6 implementation of the ac-link, up to three codecs can be connected to the sdout pin. the following mechanism is used to addre ss the primary, secondary, and tertiary codecs individually. the primary device uses bit 19 of slot 1 as the direc tion bit to specify read or write. bits [18:12] of slot 1 are used for the register i ndex. for i/o writes to the primary codec, the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in table 5-57 . slot 1 is used to transmit the register address, and slot 2 is used to transmit data. for i/o reads to the primary co dec, only slot 1 should be valid since only an address is transmitted. for i/o reads only slot 1 valid bit is set, while for i/o writes both slots 1 and 2 valid bits are set. the secondary and tertiary codec registers are accessed using slots 1 and 2 as described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec id bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non-zero valu e. this allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine if the access is directed to the secondary or tertiary codec. if the register access is targeted to the secondary or tertiary codec, slot 1 and 2 will contain the addr ess and data for the register access. since slots 1 and 2 are marked invalid, the prim ary codec will ignore these accesses. figure 5-13. ac-link protocol sync bit_clk sdin slot ( 1 ) time slot "valid" bits 20.8us (48 khz) slot 1 slot 2 019 019 0 19 0 slot 3 slot 12 81.4 ns 12.288 mhz slot ( 2 ) "0" "0" "0" slot ( 12 ) ("1" = time slot contains valid pcm 19 codec ready end of previous audio frame tag phase data phase
intel ? i/o controller hub 6 (ich6) family datasheet 231 functional description when accessing the codec registers, only one i/o cycle can be pending across the ac-link at any time. the ich6 implements write posting on i/o writ es across the ac-link (i.e., writes across the link are indicated as complete before they are actua lly sent across the link). in order to prevent a second i/o write from occurring before the first one is complete, software must monitor the cas bit in the codec access semaphore register whic h indicates that a codec access is pending. once the cas bit is cleared, th en another codec access (read or write ) can go through. the exception to this being reads to offset 54h/d4h/154h (slot 12) which are returned immediately with the most recently received slot 12 data. writes to offset 54h, d4h, and 154h (primary , secondary and tertiary codecs), get transmitted across the ac-link in slots 1 and 2 as a norm al register access. slot 12 is also updated immediately to reflect the data being written. the controller does not issue back to back reads. it must get a response to the first read before issuing a second. in addition, co dec reads and writes are only execu ted once across the link, and are not repeated. 5.22.3 ac-link low power mode the ac-link signals can be placed in a low-power mode. when the ac ?97 powerdown register (26h), is programmed to the appropriate valu e, both acz_bit_clk and acz_sdin will be brought to, and held at a logic low voltage level. table 5-57. output tag slot 0 bit primary access example secondary access example description 15 1 1 frame valid 14 1 0 slot 1 valid, command addr ess bit (primary codec only) 13 1 0 slot 2 valid, command da ta bit (primary codec only) 12:3 x x slot 3?12 valid 2 0 0 reserved 1:0 00 01 codec id (00 reserved for primary; 01 indicate secondary; 10 indicate tertiary) figure 5-14. ac-link powerdown timing acz_sdout tag a cz_sync a cz_bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 prev. frame acz_sdin[2:0] note: acz_bit_clk not to scale
232 intel ? i/o controller hub 6 (i ch6) family datasheet functional description acz_bit_clk and acz_sdin transition low immediately after a write to the powerdown register (26h) with pr4 enabled. when the ac ?97 controller driver is at the point where it is ready to program the ac-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. the ac ?97 controller also drives acz_sync , and acz_sdout low after programming ac ?97 to this low power, halted mode once the codec has been instructed to halt, acz_ bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode si nce normal output and input frames can not be communicated in the absence of acz_bit_clk. once in a low-power mode, the ich6 provides three methods for waking up the ac-link; extern al wake event, cold reset and warm reset. note: before entering any low-power mode where the link interface to the cod ec is expected to be powered down while the rest of the system is awake, the software must set the ?shut off? bit in the control register. 5.22.3.1 external wake event codecs can signal the controller to wake the ac-link, and wake the system using acz_sdin. the minimum acz_sdin wake up pulse width is 1 us. the rising edge of acz_sdin[0], acz_sdin[1] or acz_sdin[2] causes the ich6 to sequence through an ac-link warm reset and set the ac97_sts bit in the gpe0_sts register to wake the system. the primary codec must wait to sample acz_sync high and low before restarting acz_bit_clk as diagrammed in figure 5-15 . the codec that signaled the wake event must keep its acz_sdin high until it has sampled acz_sync having gone high, and then low. the ac-link protocol provides for a cold reset and a warm reset. the type of reset used depends on the system?s current power down state. unless a cold or register reset (a write to the reset register in the codec) is performed, wh erein the ac ?97 codec registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, activation of the ac-link via re-assertion of the acz_sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when ac-link powers up, it in dicates readiness via the codec ready bit. figure 5-15. sdin wake signaling acz_ sdout tag acz_sync acz_bit_clk write to 0x20 data pr4 slot 12 prev. frame tag slot 12 p rev. frame acz_ sdin[2:0] tag slot 1 slot 2 power down frame wake event sleep state new audio frame tag slot 1 slot 2
intel ? i/o controller hub 6 (ich6) family datasheet 233 functional description 5.22.4 ac ?97 cold reset a cold reset is achieved by asserting acz_rst# for 1 s. by driving acz_rst# low, acz_bit_clk, and acz_sdout will be activated and all codec regi sters will be initialized to their default power on reset values. acz_rst# is an asynchronous ac ?97 input to the codec. 5.22.5 ac ?97 warm reset a warm reset re-activates the ac -link without altering the current codec register values. a warm reset is signaled by driving acz_sync high for a minimum of 1 s in the absence of acz_bit_clk. within normal frames, acz_sync is a synchronous ac ?97 input to the codec. however, in the absence of acz_bit_clk, acz_sync is treated as an asynchronous input to the codec used in the generation of a warm reset. the codec must not respond with the activation of acz_bit_clk until acz_sync has been sampled low again by the codec. this prev ents the false detection of a new frame. note: on receipt of wake up signaling from the codec, the digital controller issues an interr upt if enabled. software then has to issue a warm or cold reset to the codec by setting th e appropriate bit in the global control register. 5.22.6 hardware assist to dete rmine acz_sdin used per codec software first performs a read to one of th e audio codecs. the read request goes out on acz_sdout. since the ich6 allows one read to be performed at a time on the link, eventually the read data will come back in on one of the acz_sdin[2:0] lines. the codec does this by indicating th at status data is valid in its tag, then echoes the read address in slot 1 followed by the read data in slot 2. the new function of the ich6 hardware is to notice which acz_sdin line contains the read return data, and to set new bits in the new register indi cating which acz_sdin line the register read data returned on. if it returned on acz_sdin[0], bits [1:0] contain the value 00. if it returned on acz_sdin[1], the bits c ontain the value 01, etc. ich6 hardware can set these bits every time regist er read data is returned from a function 5 read. no special command is necessary to cause the bits to be set. th e new driver/bios software reads the bits from this register wh en it cares to, and can ignore it otherwise. when software is attempting to establish the codec- to-acz_sdin mapping, it will single feed the read request and not pipeline to ensure it gets the right mappin g, we cannot ensure the serialization of the access.
234 intel ? i/o controller hub 6 (i ch6) family datasheet functional description 5.23 intel ? high definition audio (d27:f0) 5.23.1 link protocol overview the intel high definition audio link is the digi tal serial interface that connects hd audio codecs to the ich6 hd audio controller. the hd audio link protocol is synchronous with the controller based on a fixed 24.000 mhz clock (acz_bit_clk), and is purely isochronous (no flow control), with a 48 khz framing period. separate input and output serial digital signals support multiple inbound and outbound streams, as well as fixed command and response channels. since the hd audio link is purely an isochronou s transport mechanism, all link data transmission occurs within periodic time fram es. a frame is defined as a 20.833 ms window of time marked by the falling edge of the frame sync marker, iden tifying the start of each frame. the hd audio controller is responsible for generating the frame sync marker, which is a high-going pulse on the acz_sync signal, exactly 4 ac z_bit_clk cycles in width. 5.23.1.1 frame composition basic inbound and outbound frames are made up of three major components: command/response field, stream packet s, and null fields. 5.23.1.1.1 command/response field this field is used for link and codec management . one of these fields appears exactly once per frame, most significant bit first, and is always the first field in the frame. it is composed of a 40-bit command field on each outbound frame and a 36-bit response field on each inbound frame. 5.23.1.1.2 stream packet a stream packet is the l ogical ?envelop? in which data is transf erred on the link. since all data is associated with a given st ream, each stream packet is delineated with an associated stream tag, which provides the stream id or stream number of the packet data. the stream packet is made up with zero or more sample blocks each of which ha s the same length (or sample size) and same time reference (or sample point). a sample block contains one or more samples, the number of which is specified by a control register. as an example, a monaural stream has one sample per sample block; a stereo stream has two samples per sample bloc k; a 5.1multi-channel stream has 6 samples per sample block, and so forth. figure 5-16. intel ? high definition audio link protocol example command stream stream 1 data stream 5 data t frame_sync = 20.833 s (48khz) response stream stream ?b? data tag frame sync tag next frame previous frame acz_bit_clk (24.00 mhz) acz_sync acz_sdout acz_sdin acz_rst#
intel ? i/o controller hub 6 (ich6) family datasheet 235 functional description 5.23.1.1.3 null field the remainder of bits contained in each inbound or outbound frame that are not used for command / response fields or for stream packets, are a null field. a null field is transmitted as logical zeros. 5.23.2 link reset a link reset is signaled on the hd audio link by assertion of the acz_rst# signal. link reset results in all hd audio codec and c ontroller interface lo gic, including registers, being initialized to their default state. note however, that codecs ma y contain critical logic associated with power management functions, such as power state information or caller id in a modem codec, that may or may not be reset depending on the state of the codec at the time that acz_rst# was asserted. the link reset sequence occurs in re sponse to three classes of events: ? reset occurring on the hd audio controller?s host bus, including system power-up sequencing. ? software initiating link reset. ? certain software-initiated power management sequences. regardless of the reason for entering the link reset state, the link may be existed only under software control. 5.23.3 link power management the hd audio link is designed to support all relevant power management features. in most cases, all power management state changes are driven by software, either through controller control registers, or command verbs to codecs. the excepti on to this is when a codec is put into a low power mode awaiting an extern al wake up event, such as a ring indication on a modem. when the hd audio link is comma nded to enter a low power state, it enters the link reset state.
236 intel ? i/o controller hub 6 (i ch6) family datasheet functional description
intel ? i/o controller hub 6 (ich6) family datasheet 237 register and memory mapping 6 register and memory mapping the ich6 contains registers th at are located in the processo r?s i/o space and memory space and sets of pci configuration regist ers that are located in pci c onfiguration space. this chapter describes the ich6 i/o and memory maps at th e register-set level. register access is also described. register-level address maps and individual register bit descriptions are provided in the following chapters. the following notations and definitions are used in the register/instruction description chapters. ro read only. in some cases, if a register is read only, writes to this register location have no effect. however, in other cases, two separate registers are located at the same location wher e a read accesses one of the registers and a write accesses the other regist er. see the i/o and memory map tables for details. wo write only. in some cases, if a register is write only, reads to this register location have no effect. however, in other cases, two separate registers are located at the same location wher e a read accesses one of the registers and a write accesses the other regist er. see the i/o and memory map tables for details. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/wo read/write-once. a register bit with this attribute can be written only once after power up. after the first write, the bit becomes read only. r/wlo read/write, lock-once. a register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. after the locked value has been written, the bit becomes read only. default when ich6 is reset, it sets its regi sters to predetermined default states. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the ich6 registers accordingly. bold register bits that are highlighted in bold text indicate that the bit is implemented in the ich6. register bi ts that are not implemented or are hardwired will remain in plain text.
238 intel ? i/o controller hub 6 (i ch6) family datasheet register and memory mapping 6.1 pci devices and functions the ich6 incorporates a variety of pci functions as shown in table 6-1 . these functions are divided into six logical devices (b0:d30, b0:d31, b0:d29, b0:d28, b0:d27 and b1:d8). d30 contains the dmi interface-to-pci bridge an d the ac ?97 audio and modem controller. d31 contains the pci-to-lpc bridge, ide controller, sata controller, and the smbus controller. d29 contains the four usb uhci controllers and one usb ehci controller. d27 contains the intel high definition audio controller. b1:d8 is the integrated lan controller. note: from a software perspective, the integrated lan controll er resides on the ich6?s external pci bus. this is typically bus 1, but may be assigned a di fferent number depending on system configuration. if for some reason, the particular system platform does not want to support any one of the device functions, with the exception of d30:f0, they can individually be disabled. the integrated lan controller will be disabled if no platform lan connect component is detected (see chapter 5.3 ). when a function is disabled, it does not appear at all to the software. a disabled function will not respond to any register reads or writes, insuring that these devices app ear hidden to software. b notes: 1. the lpc controller contains regi sters that control lpc, power management, system management, gpio, processor interface, rtc, interrupts, timers, dma. table 6-1. pci devices and functions bus:device:function function description bus 0:device 30:function 0 pci-to-pci bridge bus 0:device 30:function 2 ac ?97 audio controller bus 0:device 30:function 3 ac ?97 modem controller bus 0:device 31:function 0 lpc controller 1 bus 0:device 31:function 1 ide controller bus 0:device 31:function 2 sata controller bus 0:device 31:function 3 smbus controller bus 0:device 29:function 0 usb uhci controller 1 bus 0:device 29:function 1 usb uhci controller 2 bus 0:device 29:function 2 usb uhci controller 3 bus 0:device 29:function 3 usb uhci controller 4 bus 0:device 29:function 7 usb 2.0 ehci controller bus 0:device 28:function 0 pci express* port 1 bus 0:device 28:function 1 pci express port 2 bus 0:device 28:function 2 pci express port 3 bus 0:device 28:function 3 pci express port 4 bus 0:device 27:function 0 intel high definition audio controller bus n:device 8:function 0 lan controller
intel ? i/o controller hub 6 (ich6) family datasheet 239 register and memory mapping 6.2 pci configuration map each pci function on the ich6 has a set of pci co nfiguration registers. the register address map tables for these register sets are included at the beginning of the chapter for the particular function. configuration space registers ar e accessed through configuration cycles on the pci bus by the host bridge using configuration mechanism #1 detailed in the pci local bus specification, revision 2.3 . some of the pci registers contain reserved bits. so ftware must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on wr ites, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, write oper ation for the configurat ion address register. in addition to reserved bits within a register, the configuration space cont ains reserved locations. software should not write to reserved pci config uration locations in the device-specific region (above address offset 3fh). 6.3 i/o map the i/o map is divided into fixed and variable a ddress ranges. fixed ranges cannot be moved, but in some cases can be disabled. variable ra nges can be moved and can also be disabled. 6.3.1 fixed i/o address ranges table 6-2 shows the fixed i/o decode ranges from the processor perspective. note that for each i/ o range, there may be separate behavior for read s and writes. dmi (direct media interface) cycles that go to target ranges that are marked as ?reserved? will not be decoded by the ich6, and will be passed to pci unless the substractive decode policy bit is set (d31:f0:offset 42h, bit 0). if a pci master targets one of the fixed i/o target ranges, it will be positively decoded by the ich6 in medium speed. address ranges that are not listed or marked ?reserved? are not decoded by the ich6 (unless assigned to one of the variable ranges).
240 intel ? i/o controller hub 6 (i ch6) family datasheet register and memory mapping table 6-2. fixed i/o ranges decoded by intel ? ich6 (sheet 1 of 2) i/o address read target write target internal unit 00h?08h dma controller dma controller dma 09h?0eh reserved dma controller dma 0fh dma controller dma controller dma 10h?18h dma controller dma controller dma 19h?1eh reserved dma controller dma 1fh dma controller dma controller dma 20h?21h interrupt controller interrupt controller interrupt 24h?25h interrupt controller interrupt controller interrupt 28h?29h interrupt controller interrupt controller interrupt 2ch?2dh interrupt controller interrupt controller interrupt 2e?2f lpc sio lpc sio forwarded to lpc 30h?31h interrupt controller interrupt controller interrupt 34h?35h interrupt controller interrupt controller interrupt 38h?39h interrupt controller interrupt controller interrupt 3ch?3dh interrupt controller interrupt controller interrupt 40h?42h timer/counter timer/counter pit (8254) 43h reserved timer/counter pit 4e?4f lpc sio lpc sio forwarded to lpc 50h?52h timer/counter timer/counter pit 53h reserved timer/counter pit 60h microcontroller microcontroller forwarded to lpc 61h nmi controller nmi controller processor i/f 62h microcontroller microcontroller forwarded to lpc 64h microcontroller microcontroller forwarded to lpc 66h microcontroller microcontroller forwarded to lpc 70h reserved nmi and rtc controller rtc 71h rtc controller rtc controller rtc 72h rtc controller nmi and rtc controller rtc 73h rtc controller rtc controller rtc 74h rtc controller nmi and rtc controller rtc 75h rtc controller rtc controller rtc 76h rtc controller nmi and rtc controller rtc 77h rtc controller rtc controller rtc 80h dma controller, or lpc, or pci dma controller and lpc or pci dma 81h?83h dma controller dma controller dma 84h?86h dma controller dma controller and lpc or pci dma 87h dma controller dma controller dma
intel ? i/o controller hub 6 (ich6) family datasheet 241 register and memory mapping notes: 1. a read to this address will subtractivel y go to pci, where it will master abort. 2. only if ide i/o space is enabled (d31:f1:40 bit 15) and the ide controller is in legacy mode. otherwise, the target is pci. 88h dma controller dma controller and lpc or pci dma 89h?8bh dma controller dma controller dma 8ch?8eh dma controller dma controller and lpc or pci dma 08fh dma controller dma controller dma 90h?91h dma controller dma controller dma 92h reset generator reset generator processor i/f 93h?9fh dma controller dma controller dma a0h?a1h interrupt controller interrupt controller interrupt a4h?a5h interrupt controller interrupt controller interrupt a8h?a9h interrupt controller interrupt controller interrupt ach?adh interrupt controller interrupt controller interrupt b0h?b1h interrupt controller interrupt controller interrupt b2h?b3h power management power management power management b4h?b5h interrupt controller interrupt controller interrupt b8h?b9h interrupt controller interrupt controller interrupt bch?bdh interrupt controller interrupt controller interrupt c0h?d1h dma controller dma controller dma d2h?ddh reserved dma controller dma deh?dfh dma controller dma controller dma f0h pci and master abort 1 ferr#/ignne# / interrupt controller processor i/f 170h?177h ide controller, sata controller, or pci ide controller, sata controller, or pci forwarded to ide or sata 1f0h?1f7h ide controller, sata controller, or pci 2 ide controller, sata controller, or pci forwarded to ide or sata 376h ide controller, sata controller, or pci ide controller, sata controller, or pci forwarded to ide or sata 3f6h ide controller, sata controller, or pci 2 ide controller, sata controller, or pci forwarded ide or sata 4d0h?4d1h interrupt controller interrupt controller interrupt cf9h reset generator reset generator processor i/f table 6-2. fixed i/o ranges decoded by intel ? ich6 (sheet 2 of 2) i/o address read target write target internal unit
242 intel ? i/o controller hub 6 (i ch6) family datasheet register and memory mapping 6.3.2 variable i/o decode ranges table 6-3 shows the variable i/o decode ranges. th ey are set using base address registers (bars) or other configuration bi ts in the various pci configura tion spaces. the pnp software (pci or acpi) can use their configuration mech anisms to set and adjust these values. warning: the variable i/o ranges should not be set to conflict with the fixed i/o ranges. unpredictable results if the configuration software allows conflicts to occur. the ich6 does not perform any checks for conflicts. note: 1. decode range size determined by d31:f0:adh:bits 5:4 table 6-3. variable i/o decode ranges range name mappable size (bytes) target acpi anywhere in 64 kb i/o space 64 power management ide bus master anywhere in 64 kb i/o space 16 ide unit native ide command anywhere in 64 kb i/o space 8 ide unit native ide control anywhere in 64 kb i/o space 4 ide unit usb uhci controller #1 anywhere in 64 kb i/o space 32 usb unit 1 usb uhci controller #2 anywhere in 64 kb i/o space 32 usb unit 2 usb uhci controller #3 anywhere in 64 kb i/o space 32 usb unit 3 usb uhci controller #4 anywhere in 64 kb i/o space 32 usb unit 4 smbus anywhere in 64 kb i/o space 32 smb unit ac ?97 audio mixer anywhere in 64 kb i/o space 256 ac ?97 unit ac ?97 audio bus master anywhere in 64 kb i/o space 64 ac ?97 unit ac ?97 modem mixer anywhere in 64 kb i/o space 256 ac ?97 unit ac ?97 modem bus master anywhere in 64 kb i/o space 128 ac ?97 unit tco 96 bytes above acpi base 32 tco unit gpio anywhere in 64 kb i/o space 64 gpio unit parallel port 3 ranges in 64 kb i/o space 8 lpc peripheral serial port 1 8 ranges in 64 kb i/o space 8 lpc peripheral serial port 2 8 ranges in 64 kb i/o space 8 lpc peripheral floppy disk controll er 2 ranges in 64 kb i/o space 8 lpc peripheral lan anywhere in 64 kb i/o space 64 lan unit lpc generic 1 anywhere in 64 kb i/o space 128 lpc peripheral lpc generic 2 anywhere in 64 kb i/o space 16, 32, or 641 lpc peripheral i/o trapping ranges anywhere in 64 kb i/o space 1 to 256 trap on backbone
intel ? i/o controller hub 6 (ich6) family datasheet 243 register and memory mapping 6.4 memory map table 6-4 shows (from the processor perspective) th e memory ranges that the ich6 decodes. cycles that arrive from dmi that are not directed to any of the inte rnal memory targets that decode directly from dmi will be driven out on pci unl ess the substractive deco de policy bit is set (d31:f0:offset 42h, bit 0). the ich6 may then claim the cycle for the in ternal lan controller. pci cycles generated by external pci masters will be positively decoded unless they fall in the pci-to-pci bridge memory forwarding ranges (tho se addresses are reserved for pci peer-to-peer traffic). if the cycle is not in th e internal lan cont roller?s range, it will be forwarded up to dmi. software must not attempt locks to the ich6?s memory-mapped i/o ranges for ehci and hpet. if attempted, the lock is not honored which means potential deadlock conditions may occur. table 6-4. memory decode ranges from processor perspective (sheet 1 of 2) memory range target dependency/comments 0000 0000h?000d ffffh 0010 0000h?tom (top of memory) main memory tom registers in host controller 000e 0000h?000e ffffh firmware hub bit 6 in firmware hub decode enable register is set 000f 0000h?000f ffffh firmware hub bit 7 in firmware hub decode enable register is set fec0 0000h?fec0 0100h i/o apic inside ich6 ffc0 0000h?ffc7 ffffh ff80 0000h?ff87 ffffh firmware hub (or pci) 3 bit 8 in firmware hub decode enable register is set ffc8 0000h?ffcf ffffh ff88 0000h?ff8f ffffh firmware hub (or pci) 3 bit 9 in firmware hub decode enable register is set ffd0 0000h?ffd7 ffffh ff90 0000h?ff97 ffffh firmware hub (or pci) 3 bit 10 in firmware hub decode enable register is set ffd8 0000h?ffdf ffffh ff98 0000h?ff9f ffffh firmware hub (or pci) 3 bit 11 in firmware hub decode enable register is set ffe0 000h?ffe7 ffffh ffa0 0000h?ffa7 ffffh firmware hub (or pci) 3 bit 12 in firmware hub decode enable register is set ffe8 0000h?ffef ffffh ffa8 0000h?ffaf ffffh firmware hub (or pci) 3 bit 13 in firmware hub decode enable register is set fff0 0000h?fff7 ffffh ffb0 0000h?ffb7 ffffh firmware hub (or pci) 3 bit 14 in firmware hub decode enable register is set fff8 0000h?ffff ffffh ffb8 0000h?ffbf ffffh firmware hub (or pci) 3 always enabled. the top two, 64 kb blocks of this range can be swapped, as described in section 7.4.1 . ff70 0000h?ff7f ffffh ff30 0000h?ff3f ffffh firmware hub (or pci) 3 bit 3 in firmware hub decode enable register is set ff60 0000h?ff6f ffffh ff20 0000h?ff2f ffffh firmware hub (or pci) 3 bit 2 in firmware hub decode enable register is set ff50 0000h?ff5f ffffh ff10 0000h?ff1f ffffh firmware hub (or pci) 3 bit 1 in firmware hub decode enable register is set ff40 0000h?ff4f ffffh ff00 0000h?ff0f ffffh firmware hub (or pci) 3 bit 0 in firmware hub decode enable register is set
244 intel ? i/o controller hub 6 (i ch6) family datasheet register and memory mapping notes: 1. only lan cycles can be seen on pci. 2. software must not attempt locks to memory m apped i/o ranges for usb ehci or high precision event timers. if attempted, the lock is not honored, which means potential deadloc k conditions may occur. 3. pci is the target when the boot bios destination select ion bit is low (chipset conf iguration registers:offset 3401:bit 3). when pci selected, the firmware hub decode enable bits have no effect. 6.4.1 boot-block update scheme the ich6 supports a ?top-block sw ap? mode that has the ich6 swap the top block in the firmware hub (the boot block) with another location. this al lows for safe update of the boot block (even if a power failure occurs). when the ?top_swap? enable bit is set, the ich6 will invert a16 for cycles targeting firmware hub space. when this bit is 0, the ich6 wi ll not invert a 16. this bit is automatically set to 0 by rtcrst#, but not by pltrst#. the scheme is based on the concept that the top bloc k is reserved as the ?boot? block, and the block immediately below the top block is reserved for doing boot-block updates. the algorithm is: 1. software copies the top block to the block immediately below the top 2. software checks that the copied block is correct. this could be done by performing a checksum calculation. 3. software sets the top_swap bit. this will invert a16 for cycles going to the firmware hub. processor access to ffff_0000h through ffff_ ffffh will be directed to fffe_0000h through fffe_ffffh in the firm ware hub, and processor accesses to fffe_0000h through fffe_ffff will be directed to ffff_0000h through ffff_ffffh. 4. software erases the top block 5. software writes the new top block 6. software checks the new top block 7. software clears the top_swap bit 8. software sets the top_swap lock-down bit 4 kb anywhere in 4-gb range integrated lan controller 1 enable via bar in device 29:function 0 (integrated lan controller) 1 kb anywhere in 4-gb range usb ehci controller 2 enable via standard pci me chanism (device 29, function 7) 512 b anywhere in 4-gb range ac ?97 host controller (mixer) enable via standard pci me chanism (device 30, function 2) 256 b anywhere in 4-gb range ac ?97 host controller (bus master) enable via standard pci me chanism (device 30, function 3) 512 b anywhere in 64-bit addressing space intel high definition audio host controller enable via standard pci me chanism (device 30, function 1) fed0 x000h?fed0 x3ffh high precision event timers 2 bios determines the ?fixed? location which is one of four, 1-kb ranges where x (in the first column) is 0h, 1h, 2h, or 3h. all other pci none table 6-4. memory decode ranges from processor perspective (sheet 2 of 2) memory range target dependency/comments
intel ? i/o controller hub 6 (ich6) family datasheet 245 register and memory mapping if a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. this is because the top_swap bit is backed in the rtc well. note: the top-block swap mode may be forced by an external strapping option (see section 2.22.1 ). when top-block swap mode is forced in this manner, the top_swap bit cannot be cleared by software. a re-boot with the strap removed will be required to exit a forced top-block swap mode. note: top-block swap mode only affects accesses to the firmware hub space, not feature space. note: the top-block swap mode has no effect on accesses below fffe_0000h.
246 intel ? i/o controller hub 6 (i ch6) family datasheet register and memory mapping
intel ? i/o controller hub 6 (ich6) family datasheet 247 chipset configuration registers 7 chipset configuration registers this section describes all registers and base func tionality that is related to chipset configuration and not a specific interface (such as lpc, pci, or pci express*). it contains the root complex register block, which describes the be havior of the upstream internal link. this block is mapped into memory space, us ing register rcba of the pci-to-lpc bridge. accesses in this space must be limited to 32-( dw) bit quantities. burst accesses are not allowed. 7.1 chipset configuration registers (memory space) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). . table 7-1. chipset configuration register memory map (memory space) (sheet 1 of 3) offset mnemonic register name default type 0000?0003h vch virtual channel capability header 10010002h ro 0004?0007h vcap1 virtual channel capability #1 00000801h ro 0008?000bh vcap2 virtual channel capability #2 00000001h ro 000c?000dh pvc port vc control 0000h r/w, ro 000e?000fh pvs port vc status 0000h ro 0010?0013h v0cap vc 0 resource capability 00000001h ro 0014?0017h v0ctl vc 0 resource control 800000ffh r/w, ro 001a?001bh v0sts vc 0 resource status 0000h ro 0100?0103h rctcl root complex topology capability list 1a010005h ro 0104?0107h esd element self description 00000602h r/wo, ro 0110?0113h uld upstream link descriptor 00000001h r/wo, ro 0118?011fh ulba upstream link base address 0000000000000000h r/wo 0120?0123h rp1d root port 1 descriptor 01xx0002h r/wo, ro 0128?012fh rp1ba root port 1 base address 00000000000e0000h ro 0130?0133h rp2d root port 2 descriptor 02xx0002h r/wo, ro 0138?013fh rp2ba root port 2 base address 00000000000e1000h ro 0140?0143h rp3d root port 3 descriptor 03xx0002h r/wo, ro 0148?014fh rp3ba root port 3 base address 00000000000e2000h ro 0150?0153h rp4d root port 4 descriptor 04xx0002h r/wo, ro 0158?015fh rp4ba root port 4 base address 00000000000e3000h ro 0160?0163h hdd intel high definition audio descr iptor 05xx0002h r/wo, ro 0168?016fh hdba intel high definition audio base address 00000000000d8000h ro 01a0?01a3h ilcl internal link capability list 00010006h ro
248 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 01a4?01a7h lcap link capabilities 00012441h ro, r/wo 01a8?01a9h lctl link control 0000h r/w 01aa?01abh lsts link status 0041h ro 0200?0203h csir5 chipset initialization register 5 01100220h r/w 020c?020fh csir6 chipset initialization register 6 00201004h r/w 0220?0223h bcr backbone configuration register 00008000h r/w 0224?0227h rpc root port configuration 0000000xh r/w, ro 1d40?1d43h csir7 chipset initialization register 7 00000000 r/w 1e00?1e03h trsr trap status register 00h r/wc, ro 1e10?1e17h trcr trapped cycle register 0000000000000000h ro 1e18?1e1fh twdr trapped write data register 0000000000000000h ro 1e80?1e87h iotr0 i/o trap register 0 0000000000000000h r/w, ro 1e88?1e8fh iotr1 i/o trap register 1 0000000000000000h r/w, ro 1e90?1e97h iotr2 i/o trap register 2 0000000000000000h r/w, ro 1e98?1e9fh iotr3 i/o trap register 3 0000000000000000h r/w, ro 2010-2013h dmc dmi misc. control (mobile only) n/a r/w 2020?2023h cscr1 chipset configuration register 1 00c4b0dbh r/w 2027h cscr2 chipset configuration register 2 0ah r/w 2078-207bh pllmc pll misc. control (mobile only) n/a r/w 3000?3001h tctl tco control 00h r/w 3100?3103h d31ip device 31 interrupt pin 00042210h r/w, ro 3104?3107h d30ip device 30 interrupt pin 00002100h r/w, ro 3108?310bh d29ip device 29 interrupt pin 10004321h r/w 310c?310fh d28ip device 28 interrupt pin 00004321h r/w 3110?3113h d27ip device 27 interrupt pin 00000001h r/w 3140?3141h d31ir device 31 interrupt route 3210h r/w 3142?3143h d30ir device 30 interrupt route 3210h r/w 3144?3145h d29ir device 29 interrupt route 3210h r/w 3146?3147h d28ir device 28 interrupt route 3210h r/w 3148?3149h d27ir device 27 interrupt route 3210h r/w 31ff?31ffh oic other interrupt control 00h r/w 3400?3403h rc rtc configuration 00000000h r/w, r/wlo 3404?3407h hptc high precision timer configuration 00000000h r/w 3410?3413h gcs general control and status 0000000xh r/w, r/wlo 3414?3414h buc backed up control 0000001xb (mobile) 0000000xb (desktop) r/w 3418?341bh fd function disable see bit description r/w, ro table 7-1. chipset configurat ion register memory map (memory space) (sheet 2 of 3) offset mnemonic register name default type
intel ? i/o controller hub 6 (ich6) family datasheet 249 chipset configuration registers 7.1.1 vch?virtual channel capability header register offset address: 0000?0003h attribute: ro default value: 10010002h size: 32-bit 7.1.2 vcap1?virtual channel capability #1 register offset address: 0004?0007h attribute: ro default value: 00000801h size: 32-bit 341c?341fh cg clock gating 00000000h r/w, ro 3e08?3e09h csir1 chipset initialization register 1 0000h r/w 3e0eh csir3 chipset initialization register 4 00h r/w 3e48?3e49h csir2 chipset initialization register 2 0000h r/w 3e4eh csir4 chipset initialization register 4 00h r/w table 7-1. chipset configuration register memory map (memory space) (sheet 3 of 3) offset mnemonic register name default type bit description 31:20 next capability offset (nco) ? ro. this field indicates the next item in the list. 19:16 capability version (cv) ? ro . this field indicates support as a version 1 capability structure. 15:0 capability id (cid) ? ro. this field indicates this is the virtual channel capability item. bit description 31:12 reserved 11:10 port arbitration table entry size (pats) ? ro. this field indicates the size of the port arbitration table is 4 bits (to allow up to 8 ports). 9:8 reference clock (rc) ? ro. fixed at 100 ns. 7 reserved 6:4 low priority extended vc count (lpevc) ? ro. this field indicates that there are no additional vcs of low priority with extended capabilities. 3:0 reserved
250 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.3 vcap2?virtual channel capability #2 register offset address: 0008?000bh attribute: ro default value: 00000001h size: 32-bit 7.1.4 pvc?port virtual ch annel control register offset address: 000c?000dh attribute: r/w, ro default value: 0000h size: 16-bit 7.1.5 pvs?port virtual channel status register offset address: 000e?000fh attribute: ro default value: 0000h size: 16-bit bit description 31:24 vc arbitration table offset (ato) ? ro. this bi t indicates that no table is present for vc arbitration since it is fixed. 23:0 reserved bit description 15:04 reserved 3:1 vc arbitration select (as) ? ro. this bit indi cates which vc should be programmed in the vc arbitration table. the root complex takes no ac tion on the setting of this field since there is no arbitration table. 0 load vc arbitration table (lat) ? ro. this bit indicates that the t able programmed should be loaded into the vc arbitration table. this bit is defined as read/write with always returning 0 on reads. bit description 15:01 reserved 0 vc arbitration table status (vas) ? ro. this bit indicates the coherency status of the vc arbitration table when it is being updated. this fiel d is always 0 in the root complex since there is no vc arbitration table.
intel ? i/o controller hub 6 (ich6) family datasheet 251 chipset configuration registers 7.1.6 v0cap?virtual channel 0 resource capability register offset address: 0010?0013h attribute: ro default value: 00000001h size: 32-bit 7.1.7 v0ctl?virtual channel 0 resource control register offset address: 0014?0017h attribute: r/w, ro default value: 800000ffh size: 32-bit bit description 31:24 port arbitration table offset (at) ? ro. this vc implements no port arbitration table since the arbitration is fixed. 23 reserved 22:16 maximum time slots (mts) ? ro. this vc implem ents fixed arbitration, and therefore this field is not used. 15 reject snoop transactions (rts) ? ro. this vc must be able to take snoopable transactions. 14 advanced packet switching (aps) ? ro. this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved 7:0 port arbitration capability (pac) ? ro. this field indicates that th is vc uses fixed port arbitration. bit description 31 virtual channel enable (en) ? ro. always set to 1. vc0 is always enabled and cannot be disabled. 30:27 reserved 26:24 virtual channel identifier (id) ? ro. this field indicates the id to use for this virtual channel. 23:20 reserved 19:17 port arbitration select (pas) ? r/w. indicates which port tabl e is being programmed. the root complex takes no action on this setting since the arbitration is fixed and there is no arbitration table. 16 load port arbitration table (lat) ? ro. the root complex does not implement an arbitration table for this virtual channel. 15:8 reserved 7:1 transaction class / virtual channel map (tvm) ? r/w. this field indicates which transaction classes are mapped to this virtual channel. when a bit is set, this transac tion class is mapped to the virtual channel. 0 reserved
252 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.8 v0sts?virtual channel 0 resource status register offset address: 001a?001bh attribute: ro default value: 0000h size: 16-bit 7.1.9 rctcl?root complex topolo gy capabilities list register offset address: 0100?0103h attribute: ro default value: 1a010005h size: 32-bit 7.1.10 esd?element self description register offset address: 0104?0 107h attribute: r/wo, ro default value: 00000602h size: 32-bit bit description 15:02 reserved 1 vc negotiation pending (np) ? ro. 1 = virtual channel is still being negotiated with ingress ports. 0 port arbitration tables status (ats ) ? ro. there is no port arbitration table for this vc, so this bit is reserved at 0. bit description 31:20 next capability (next) ? ro. this fi eld indicates the next item in the list. 19:16 capability version (cv) ? ro . this field indicates the versi on of the capability structure. 15:0 capability id (cid) ? ro. this fi eld indicates this is a pci expres s* link capability section of an rcrb. bit description 31:24 port number (pn) ? ro. a value of 0 to indicate the egress port for the intel ? ich6. 23:16 component id (cid) ? r/wo. this field indicates the co mponent id assigned to this element by software. this is written once by platform bios and is locked until a platform reset. 15:8 number of link entries (nle) ? ro. this fiel d indicates that one link entry (corresponding to dmi), 4 root port entries (for the downstream ports), and the intel high definition a udio device are described by this rcrb. 7:4 reserved 3:0 element type (et) ? ro. this field indicates t hat the element type is a root complex internal link.
intel ? i/o controller hub 6 (ich6) family datasheet 253 chipset configuration registers 7.1.11 uld?upstream link descriptor register offset address: 0110?0113h attribute: r/wo, ro default value: 00000001h size: 32-bit 7.1.12 ulba?upstream link base address register offset address: 0118?011fh attribute: r/wo default value: 0000000000000000h size: 64-bit 7.1.13 rp1d?root port 1 descriptor register offset address: 0120?0123h attribute: r/wo, ro default value: 01xx0002h size: 32-bit bit description 31:24 target port number (pn) ? r/wo. this field is programmed by platform bios to match the port number of the (g)mch rcrb that is attached to this rcrb. 23:16 target component id (tcid) ? r/wo. this field is programmed by platform bios to match the component id of the (g)mch rcrb that is attached to this rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicates that t he link points to the (g)mch rcrb. 0 link valid (lv) ? ro. this bit indicates th at the link entry is valid. bit description 63:32 base address upper (bau) ? r/wo. this field is programmed by platform bios to match the upper 32-bits of base address of the (g)mch rcrb that is attached to this rcrb. 31:0 base address lower (bal) ? r/wo. this field is programmed by platform bios to match the lower 32-bits of base address of the (g)m ch rcrb that is attached to this rcrb. bit description 31:24 target port number (pn) ? ro. this field indicates the target port number is 1h (root port #1). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicates that the link points to a root port. 0 link valid (lv) ? ro. when fd.pe1d (offset 3418h, bit 16) is set, this link is not valid (returns 0). when fd.pe1d is cleared, this link is valid (returns 1).
254 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.14 rp1ba?root port 1 base address register offset address: 0128?012fh attribute: ro default value: 00000000000e0000h size: 64-bit 7.1.15 rp2d?root port 2 descriptor register offset address: 0130?0 133h attribute: r/wo, ro default value: 02xx0002h size: 32-bit 7.1.16 rp2ba?root port 2 base address register offset address: 0138?013fh attribute: ro default value: 00000000000e1000h size: 64-bit bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. this field indicates the root port is on bus #0. 19:15 device number (dn) ? ro. this field indicates the root port is on device #28. 14:12 function number (fn) ? ro. this field indicates the root port is on function #0. 11:0 reserved bit description 31:24 target port number (pn) ? ro. this field indicates the target port number is 2h (root port #2). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programm ed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicate s that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1: 0) is ?01?, ?10?, or ?11?, or fd.pe2d (offset 3418h, bit 17) is set, the link for this root port is not valid (return 0). when rpc.pc is ?00? and fd.pe2d is cleared, the link for this root port is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. this field indicates the root port is on bus #0. 19:15 device number (dn) ? ro. this field indicates the root port is on device #28. 14:12 function number (fn) ? ro. this field indicates the root port is on function #1. 11:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 255 chipset configuration registers 7.1.17 rp3d?root port 3 descriptor register offset address: 0140?0143h attribute: r/wo, ro default value: 03xx0002h size: 32-bit 7.1.18 rp3ba?root port 3 base address register offset address: 0148?014fh attribute: ro default value: 00000000000e2000h size: 64-bit 7.1.19 rp4d?root port 4 descriptor register offset address: 0150?0153h attribute: r/wo, ro default value: 04xx0002h size: 32-bit bit description 31:24 target port number (pn) ? ro. this field indicates the target port number is 3h (root port #3). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1: 0) is ?11?, or fd.pe3d (offset 3418h, bit 18) is set, the link for this root port is not va lid (return 0). when rpc.pc is ?00?, ?01?, or ?10?, and fd.pe3d is cleared, the link for th is root port is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. this field indicates the root port is on bus #0. 19:15 device number (dn) ? ro. this fiel d indicates the root port is on device #28. 14:12 function number (fn) ? ro. this field indicates the root port is on function #2. 11:0 reserved bit description 31:24 target port number (pn) ? ro. this field indicates the target port number is 4h (root port #4). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicates that the link points to a root port. 0 link valid (lv) ? ro. when rpc.pc (offset 0224h, bits 1:0) is ?10? or ?11?, or fd.pe4d (offset 3418h, bit 19) is set, the link for this root port is not valid (return 0). when rpc.pc is ?00? or ?01? and fd.pe4d is cleared, the link for th is root port is valid (return 1).
256 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.20 rp4ba?root port 4 base address register offset address: 0158?015fh attribute: ro default value: 00000000000e3000h size: 64-bit 7.1.21 hdd?intel ? high definition audi o descriptor register offset address: 0160?0 163h attribute: r/wo, ro default value: 05xx0002h size: 32-bit 7.1.22 hdba?intel ? high definition audi o base address register offset address: 0168?016fh attribute: ro default value: 00000000000d8000h size: 64-bit bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. this field indicates the root port is on bus #0. 19:15 device number (dn) ? ro. this field indicates the root port is on device #28. 14:12 function number (fn) ? ro. this field indicates the root port is on function #3. 11:0 reserved bit description 31:24 target port number (pn) ? ro. this field indicates the target port number is 5h (intel high definition audio). 23:16 target component id (tcid) ? r/wo. this field returns the value of the esd.cid (offset 0104h, bits 23:16) field programm ed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved 1 link type (lt) ? ro. this bit indicate s that the link points to a root port. 0 link valid (lv) ? ro. when fd.zd (offset 3418h, bit 4) is set, the link to intel high definition audio is not valid (return 0). when fd.zd is cleared, the link to intel high definition audio is valid (return 1). bit description 63:32 reserved 31:28 reserved 27:20 bus number (bn) ? ro. this field indicates the root port is on bus #0. 19:15 device number (dn) ? ro. this field indicates the root port is on device #27. 14:12 function number (fn) ? ro. this field indicates the root port is on function #0. 11:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 257 chipset configuration registers 7.1.23 ilcl?internal link capabilities list register offset address: 01a0?01a3h attribute: ro default value: 00010006h size: 32-bit 7.1.24 lcap?link capabilities register offset address: 01a4?01a7h attribute: ro, r/wo default value: 00012441h size: 32-bit 7.1.25 lctl?link control register offset address: 01a8?01a9h attribute: r/w default value: 0000h size: 16-bit bit description 31:20 next capability offset (next) ? ro. this fiel d indicates this is the last item in the list. 19:16 capability version (cv) ? ro. this field i ndicates the version of the capability structure. 15:0 capability id (cid) ? ro. this field indicates this is capability for dmi. bit description 31:18 reserved 17:15 l1 exit latency (el1) ? l1 not supported on dmi. 14:12 l0s exit latency (el0) ? r/wo. this field indicate s that exit latency is 128 ns to less than 256 ns. 11:10 active state link pm support (apms) ? r/wo. this field indicates that l0s is supported on dmi. 9:4 maximum link width (mlw) ? this field indicates the maximum link width is 4 ports. 3:0 maximum link speed (mls) ? this field indicates the link speed is 2.5 gb/s. bit description 15:8 reserved 7 extended synch (es) ? r/w. when set, forces extended transmission of fts ordered sets when exiting l0s prior to entering l0. 6:2 reserved 1:0 active state link pm control (apmc) ? r/w. this field indicate s whether dmi should enter l0s. 00 = disabled 01 = l0s entry enabled 10 = reserved 11 = reserved
258 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.26 lsts?link status register offset address: 01aa?01abh attribute: ro default value: 0041h size: 16-bit 7.1.27 csir5?chipset init ialization register 5 offset address: 0200?0203h attribute: r/w default value: 01100220h size: 32-bit 7.1.28 csir6?chipset init ialization register 6 offset address: 020c?020fh attribute: r/w default value: 00201004h size: 32-bit bit description 15:10 reserved 9:4 negotiated link width (nlw) ? ro. negotiated link width is x4 (000100b). ich6-m may also indicate x2 (000010b), depending on (g)mch configuration. 3:0 link speed (ls) ? ro. link is 2.5 gb/s. bit description 31:14 reserved 13:8 chipset initialization register bits[13:8] ? r/w. bios programs this field to 100000b. 7:6 reserved 5:0 chipset initialization register bits[5:0] ? r/w. bios programs this field to 001000b. bit description 31:22 reserved 21:16 chipset initialization register bits[21:16] ? r/w. bios programs this field to 000100b. 15:14 reserved 13:8 chipset initialization register bits[13:8] ? r/w. bios programs this field to 000010b. 7:6 reserved 5:0 chipset initialization register bits[5:0] ? r/w. bios programs this field to 000001b.
intel ? i/o controller hub 6 (ich6) family datasheet 259 chipset configuration registers 7.1.29 bcr?backbone co nfiguration register offset address: 0220?0223h attribute: r/w default value: 000008000h size: 32-bit 7.1.30 rpc?root port configuration register offset address: 0224?0227h attribute: r/w, ro default value: 0000000xh size: 32-bit bit description 31:8 reserved 7:5 backbone configuration register bits[8:5] ? r/w. bios sets this field to 111b. 4 reserved 3:0 backbone configuration register bits[3:0] ? r/w. bios sets this field to 0101b. bit description 31:8 reserved 7 high priority port enable (hpe) ? r/w. 0 = the high priority path is not enabled. 1 = the port selected by the hpp field in this r egister is enabled for hi gh priority. it will be arbitrated above all other vc0 (includi ng integrated vc0) devices. 6 reserved 5:4 high priority port (hpp) ? r/w. this field controls which port is enabled for high priority when the hpe bit in this register is set. 11 = port 4 10 = port 3 01 = port 2 00 = port 1 3:2 reserved 1:0 port configuration (pc) ? ro. this field controls how the pci bridges are organized in various modes of operation. for the following mappings, if a port is not shown, it is considered a x1 port with no connection. these bits represent the strap values of acz_ sdout (bit 1) and acz_sync (bit 0) when tp[3] is not pulled low at the rising edge of pwrok. 11 = 1 x4, port 1 (x4) (e nterprise applications only) 10 = reserved 01 = reserved 00 = 4 x1s, port 1 (x1), port 2 (x1), port 3 (x1), port 4 (x1) these bits live in the resume well and are only reset by rsmrst#.
260 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.31 csir7?chipset init ialization register 7 offset address: 1d40?1d43h attribute: r/w default value: 00000000h size: 32-bit 7.1.32 trsr?trap status register offset address: 1e00?1e03h attribute: r/wc, ro default value: 00000000h size: 32-bit 7.1.33 trcr?trapped cycle register offset address: 1e10?1e17h attribute: ro default value: 0000000000000000h size: 64-bit this register saves information about the i/o cy cle that was trapped and generated the smi# for software to read. bit description 31:1 reserved 0 chipset initialization register 7 bit[0] ? r/w. bios sets this bit to 1. bit description 31:4 reserved 3:0 cycle trap smi# status (ctss) ? r/wc. these bits are set by hardware when the corresponding cycle trap regist er is enabled and a matching cy cle is received (and trapped). these bits are or?ed together to create a singl e status bit in the power management register space. note that the smi# and trapping must be enabled in order to set these bits. these bits are set before the completion is generated for the trapped cycle, thereby guaranteeing that the processor can enter the smi# handler when the instruction completes. each status bit is cleared by writing a 1 to the correspo nding bit location in this register. bit description 63:25 reserved 24 read/write# (rwi) ? ro. 0 = trapped cycle was a write cycle. 1 = trapped cycle was a read cycle. 23:20 reserved 19:16 active-high byte enables (ahbe) ? ro. this is the dword-al igned byte enables associated with the trapped cycle. a 1 in any bit location i ndicates that the corresponding byte is enabled in the cycle. 15:2 trapped i/o address (tioa) ? ro. this is the dword-aligned address of the trapped cycle. 1:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 261 chipset configuration registers 7.1.34 twdr?trapped write data register offset address: 1e18?1e1fh attribute: ro default value: 0000000000000000h size: 64-bit this register saves the data from i/o write cy cles that are trapped for software to read. 7.1.35 iotrn?i/o trap register(0:3) offset address: 1e80?1e87h re gister 0 attribute: r/w, ro 1e88?1e8fh register 1 1e90?1e97h register 2 1e98?1e9fh register 3 default value: 0000000000000000h size: 64-bit these registers are used to speci fy the set of i/o cycles to be trapped and to enable this functionality. bit description 63:32 reserved 31:0 trapped i/o data (tiod) ? ro. dword of i/o write data. th is field is undefined after trapping a read cycle. bit description 63:50 reserved 49 read/write mask (rwm) ? r/w. 0 = the cycle must match the type specified in bit 48. 1 = trapping logic will operate on both read and write cycles. 48 read/write# (rwio) ? r/w. 0 = write 1 = read note: the value in this field does not matter if bit 49 is set. 47:40 reserved 39:36 byte enable mask (bem) ? r/w. a 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycl e will be treated as a match. the corresponding bit in the byte enables field, below, is ignored. 35:32 byte enables (tbe) ? r/w. active-high dword-aligned byte enables. 31:24 reserved 23:18 address[7:2] mask (adma) ? r/w. a 1 in any bit position indicates that any value in the corresponding address bit in a rece ived cycle will be treated as a match. the corresponding bit in the address field, below, is ignored. the mask is only provided for the lower 6 bits of the dword address, allowing for traps on address ranges up to 256 bytes in size. 17:16 reserved 15:2 i/o address[15:2] (ioad) ? r/w. dword-aligned address 1 reserved 0 trap and smi# enable (trse) ? r/w. 0 = trapping and smi# logic disabled. 1 = the trapping logic specified in this register is enabled.
262 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.36 dmc?dmi miscellaneous co ntrol register (mobile only) offset address: 2010?2013h attribute: r/w default value: n/a size: 32-bit 7.1.37 cscr1?chipset configuration register 1 offset address: 2020?2023h attribute: r/w default value: 00c4b0dbh size: 32-bits 7.1.38 cscr2?chipset configuration register 2 offset address: 2027h attribute: r/w default value: 0ah size: 8-bits bit description 31:2 reserved 1 dmi misc. control field 1 ? r/w. bios shall always program this field as per the bios specification. 0 = disable dmi power savings. 1 = enable dmi power savings. 0reserved bit description 31:28 chipset configuration register 1 bits[31:28] ? r/w. refer to the ich6 bios specification for the programming of this field. 27:9 reserved 8:6 chipset configuration register 1 bits[8:6] ? r/w. bios programs this field to 001b. 5:0 reserved bit description 7:0 chipset configuration register 2 bits[7:0] ? r/w. bios programs this field to 0dh.
intel ? i/o controller hub 6 (ich6) family datasheet 263 chipset configuration registers 7.1.39 pllmc?pll miscellaneous co ntrol register (mobile only) offset address: 2078?207bh attribute: r/w default value: n/a size: 32-bit 7.1.40 tctl?tco conf iguration register offset address: 3000?3000h attribute: r/w default value: 00h size: 8-bit bit description 31:25 reserved 24 pll misc. control field 2 ? r/w. bios shall always program this field as per the bios specification. 0 = disable clock gating. 1 = enable clock gating.. 23 reserved 22 pll misc. control field 1 ? r/w. bios shall always program this field as per the bios specification. 0 = disable clock gating. 1 = enable clock gating.. 21:0 reserved bit description 7 tco irq enable (ie) ? r/w. 0 = tco irq is disabled. 1 = tco irq is enabled, as selected by the tco_irq_sel field. 6:3 reserved 2:0 tco irq select (is) ? r/w. this field specifies on whic h irq the tco will internally appear. if not using the apic, the tco interrupt must be routed to irq9:11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the tco interrupt can also be mapped to irq20: 23, and can be shared with other interrupt. 000 = irq 9 001 = irq 10 010 = irq 11 011 = reserved 100 = irq 20 (only if apic enabled) 101 = irq 21 (only if apic enabled) 110 = irq 22 (only if apic enabled) 111 = irq 23 (only if apic enabled) when setting the these bits, the ie bit should be cleared to prevent glitching. when the interrupt is mapped to apic interrupts 9, 10 or 11, the apic should be programmed for active-high reception. when the interrupt is mapped to apic interrupts 20 through 23, the apic should be programmed for active-low reception.
264 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.41 d31ip?device 31 interrupt pin register offset address: 3100?3 103h attribute: r/w, ro default value: 00042210h size: 32-bit bit description 31:16 reserved 15:12 sm bus pin (smip) ? r/w. this field indicates which pi n the smbus controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 11:8 sata pin (sip) ? r/w. this field indicates which pin t he sata controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 7:4 pata pin (smip) ? r/w. this field indicates which pin t he pata controller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 3:0 pci bridge pin (pip) ? ro. currently, the pci br idge does not generate an interrupt, so this field is read-only and 0.
intel ? i/o controller hub 6 (ich6) family datasheet 265 chipset configuration registers 7.1.42 d30ip?device 30 interrupt pin register offset address: 3104?3107h attribute: r/w, ro default value: 00002100h size: 32-bit bit description 31:16 reserved 15:12 ac ?97 modem pin (amip) ? r/w. this field indicates which pin the ac ?97 modem controller drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 11:8 ac ?97 audio pin (aaip) ? r/w. this field indi cates which pin the ac ? 97 audio controller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 7:4 reserved 3:0 lpc bridge pin (lip) ? ro. currently, the lpc bri dge does not generate an interrupt, so this field is read-only and 0.
266 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.43 d29ip?device 29 interrupt pin register offset address: 3108?310bh attribute: r/w default value: 10004321h size: 32-bit bit description 31:28 ehci pin (eip) ? r/w. this field indicate s which pin the ehci controll er drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved 27:16 reserved 15:12 uhci #3 pin (u3p) ? r/w. this field indica tes which pin the uhci controller #3 (ports 6 and 7) drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# (default) 5h?7h = reserved 11:8 uhci #2 pin (u2p) ? r/w. this field indica tes which pin the uhci controller #2 (ports 4 and 5) drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?7h = reserved 7:4 uhci #1 pin (u1p) ? r/w. this field indica tes which pin the uhci controller #1 (ports 2 and 3) drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 3:0 uhci #0 pin (u0p) ? r/w. this field indica tes which pin the uhci controller #0 (ports 0 and 1) drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved
intel ? i/o controller hub 6 (ich6) family datasheet 267 chipset configuration registers 7.1.44 d28ip?device 28 interrupt pin register offset address: 310c?310fh attribute: r/w default value: 00004321h size: 32-bit 7.1.45 d27ip?device 27 interrupt pin register offset address: 3110?3113h attribute: r/w default value: 00000001h size: 32-bit bit description 31:16 reserved 15:12 pci express #4 pin (p4ip) ? r/w. this field indicates which pin the pci express* port #4 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# 4h = intd# (default) 5h?7h = reserved 11:8 pci express #3 pin (p3ip) ? r/w. this field indicates whic h pin the pci express port #3 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# 3h = intc# (default) 4h = intd# 5h?7h = reserved 7:4 pci express #2 pin (p2ip) ? r/w. this field indicates whic h pin the pci express port #2 drives as its interrupt. 0h = no interrupt 1h = inta# 2h = intb# (default) 3h = intc# 4h = intd# 5h?7h = reserved 3:0 pci express #1 pin (p1ip) ? r/w. this field indicates whic h pin the pci express port #1 drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved bit description 31:4 reserved 3:0 intel high definition audio pin (zip) ? r/w. this field indicates which pin the intel high definition audio c ontroller drives as its interrupt. 0h = no interrupt 1h = inta# (default) 2h = intb# 3h = intc# 4h = intd# 5h?7h = reserved
268 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.46 d31ir?device 31 interrupt route register offset address: 3140?3141h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicates which physical pin on the intel ? ich6 is connected to the intd# pin r eported for device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicates which physical pin on the ich is connected to the intc# pin r eported for device 31 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicates which physical pin on the ich is connected to the intb# pin reported for device 31 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicates which physical pin on the ich is connected to the inta# pin reported for device 31 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
intel ? i/o controller hub 6 (ich6) family datasheet 269 chipset configuration registers 7.1.47 d30ir?device 30 interrupt route register offset address: 3142?3143h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicates which physical pin on the intel ? ich6 is connected to the intd# pin r eported for device 30 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicates wh ich physical pin on the ich is connected to the intc# pin r eported for device 30 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicates wh ich physical pin on the ich is connected to the intb# pin r eported for device 30 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicates wh ich physical pin on the ich is connected to the inta# pin re ported for device 30 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
270 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.48 d29ir?device 29 interrupt route register offset address: 3144?3145h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicates which physical pin on the intel ? ich6 is connected to the intd# pin r eported for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicates wh ich physical pin on the ich6 is connected to the intc# pin r eported for device 29 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicates which physical pin on the ich is connected to the intb# pin reported for device 29 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicates wh ich physical pin on the ich6 is connected to the inta# pin reported for device 29 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
intel ? i/o controller hub 6 (ich6) family datasheet 271 chipset configuration registers 7.1.49 d28ir?device 28 interrupt route register offset address: 3146?3147h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicates which physical pin on the intel ? ich6 is connected to the intd# pin r eported for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicates which physical pin on the ich is connected to the intc# pin r eported for device 28 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7 reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicates which physical pin on the ich is connected to the intb# pin r eported for device 28 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3 reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicates which physical pin on the ich is connected to the inta# pin r eported for device 28 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
272 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.50 d27ir?device 27 interrupt route register offset address: 3148?3149h attribute: r/w default value: 3210h size: 16-bit bit description 15 reserved 14:12 interrupt d pin route (idr) ? r/w. this field indicates which physical pin on the intel ? ich6 is connected to the intd# pin r eported for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# 3h = pirqd# (default) 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 11 reserved 10:8 interrupt c pin route (icr) ? r/w. this field indicates which physical pin on the ich is connected to the intc# pin r eported for device 27 functions. 0h = pirqa# 1h = pirqb# 2h = pirqc# (default) 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 7reserved 6:4 interrupt b pin route (ibr) ? r/w. this field indicates which physical pin on the ich is connected to the intb# pin reported for device 27 functions. 0h = pirqa# 1h = pirqb# (default) 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh# 3reserved 2:0 interrupt a pin route (iar) ? r/w. this field indicates which physical pin on the ich is connected to the inta# pin reported for device 27 functions. 0h = pirqa# (default) 1h = pirqb# 2h = pirqc# 3h = pirqd# 4h = pirqe# 5h = pirqf# 6h = pirqg# 7h = pirqh#
intel ? i/o controller hub 6 (ich6) family datasheet 273 chipset configuration registers 7.1.51 oic?other interrupt control register offset address: 31ff?31ffh attribute: r/w default value: 00h size: 8-bit 7.1.52 rc?rtc configuration register offset address: 3400?3403h attribute: r/w, r/wlo default value: 00000000h size: 32-bit bit description 7:2 reserved 1 coprocessor error enable (cen) ? r/w. 0 = ferr# will not generate irq13 nor ignne#. 1 = if ferr# is low, the intel ? ich6 generates irq13 internally and holds it until an i/o port f0h write. it will also drive ignne# active. 0 apic enable (aen) ? r/w. 0 = the internal ioxapic is disabled. 1 = enables the internal ioxapic and its address decode. bit description 31:5 reserved 4 upper 128 byte lock (ul) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h?3fh in the upper 128-byte bank of rtc ram are locked and cannot be accessed. writes will be dropped and reads will not return any guaranteed data. bit reset on system reset. 3 lower 128 byte lock (ll) ? r/wlo. 0 = bytes not locked. 1 = bytes 38h?3fh in the lower 128-byte bank of rtc ram are locked and cannot be accessed. writes will be dropped and reads will not return any guaranteed data. bit reset on system reset. 2 upper 128 byte enable (ue) ? r/w. 0 = bytes locked. 1 = the upper 128-byte bank of rtc ram can be accessed. 1:0 reserved
274 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.53 hptc?high precision timer configuration register offset address: 3404?3407h attribute: r/w default value: 00000000h size: 32-bit 7.1.54 gcs?general control and status register offset address: 3410?3413h attribute: r/w, r/wlo default value: 0000000yh y=(00x0x000b) size: 32-bit bit description 31:8 reserved 7 address enable (ae) ? r/w. 0 = address disabled. 1 = the intel ? ich6 will decode the high precision time r memory address range selected by bits 1:0 below. 6:2 reserved 1:0 address select (as) ? r/w. this 2-bit field selects 1 of 4 possible memory address ranges for the high precision timer func tionality. the encodings are: 00 = fed0_0000h?fed0_03ffh 01 = fed0_1000h?fed0_13ffh 10 = fed0_2000h?fed0_23ffh 11 = fed0_3000h?fed0_33ffh bit description 31:10 reserved 9 server error reporting mode (serm) ? r/w. 0 = the intel ? ich6 is the final target of all errors. the (g)mch sends a messages to the ich for the purpose of generating nmi. 1 = the (g)mch is the final target of all errors from pci express* and dmi. in this mode, if the ich6 detects a fatal, non-fatal, or correctable error on dmi or its downstream ports, it sends a message to the (g)mch. if the ich6 receiv es an err_* message from the downstream port, it sends that message to the (g)mch. 8reserved 7 (mobile) mobile ide configuration lock down (micld) ? r/wlo. 0 = disabled. 1 = buc.prs (offset 3414h, bit 1) is locked and cannot be written until a system reset occurs. this prevents rogue software from changing the default state of the pata pins during boot after bios configures them. this bit is writ e once, and is cleared by system reset and when returning from the s3/s4/s5 states. 7 (desktop) reserved 6 ferr# mux enable (fme) ? r/w. this bit enables ferr# to be a processor break event indication. 0 = disabled. 1 = the ich6 examines ferr# during a c2 , c3, or c4 state as a break event. see chapter 5.14.5 for a functional description.
intel ? i/o controller hub 6 (ich6) family datasheet 275 chipset configuration registers 5 no reboot (nr) ? r/w. this bit is set when the ?no reboot? strap (spkr pin on ich6) is sampled high on pwrok. this bit may be set or cl eared by software if the strap is sampled low but may not override the strap when it indicates ?no reboot?. 0 = system will reboot upon the second timeout of the tco timer. 1 = the tco timer will count down and generate the smi# on the first timeout, but will not reboot on the second timeout. 4 alternate access mode enable (ame) ? r/w. 0 = disabled. 1 = alternate access read only registers can be written, and write only registers can be read. before entering a low power state, several registers from powered down parts may need to be saved. in the majority of cases, this is not an issue, as regi sters have read and write paths. however, several of the isa compatible registers are either read only or write only. to get data out of write-only registers, and to re store data into read-only registers, the ich implements an alternate access mode. for a list of these registers see section 5.14.10 . 3 boot bios destination (bbd) ? r/w. the default value of this bit is determined by a strap allowing systems with corrupted or unprogrammed fl ash to boot from a pci device. the value of the strap can be overwritten by software. when this bit is 0, the pci-to-pci bridge memo ry space enable bit does not need to be set (nor any other bits) in order for these cycles to go to pci. note that bios enable ranges and the other bios protection and update bits associated with t he fwh interface have no effect when this bit is 0. 0 = the top 16 mb of memory below 4 gb (f f00_0000h to ffff_ffffh) is accepted by the primary side of the pci p2p bridge and forwarded to the pci bus. 1 = the top 16 mb of memory below 4 gb (ff00_0000h to ffff_ffffh) is not decoded to pci and the lpc bridge claims these cycles based on the fwh decode enable bits. note: this functionality intended for debug/testing only. 2 reserved page route (rpr) ? r/w. determines where to send the reserved page registers. these addresses are sent to pci or lpc for the purpose of generating post codes. the i/o addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8ch, 8dh, and 8eh. 0 = writes will be forwarded to lpc, shadowed within the ich, and reads will be returned from the internal shadow 1 = writes will be forwarded to pci, shadowed within the ich, and reads will be returned from the internal shadow. note, if some writes are done to lpc/pci to t hese i/o ranges, and then this bit is flipped, such that writes will now go to the other interface, th e reads will not return what was last written. shadowing is performed on each interface. the aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9ch, 9dh, and 9eh, are always decoded to lpc. 1 reserved 0 top swap lock-down (tsld) ? r/wlo. 0 = disabled. 1 = prevents buc.ts (offset 3414, bit 0) from bei ng changed. this bit can only be written from 0 to 1 once. bit description
276 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.55 buc?backed up control register offset address: 3414?3414h attribute: r/w default value: 0000001xb (mobile) size: 8-bit 0000000xb (desktop) all bits in this register are in th e rtc well and only cleared by rtcrst# bit description 7:3 reserved 2 cpu bist enable (cbe) ? r/w. this bit is in the resume well and is reset by rsmrst#, but not pltrst# nor cf9h writes. 0 = disabled. 1 = the init# signals will be driven active when cpurst# is active. init# and init3_3v# will go inactive with the same timings as the other processor i/f signals (hold time after cpurst# inactive). 1 (mobile) pata reset state (prs) ? r/w. 0 = the reset state of the pata pins will be driven. 1 = the reset state of the pata pins will be tri-state. 1 (desktop) reserved 0 top swap (ts) ? r/w. 0 = intel ? ich6 will not invert a16. 1 = ich6 will invert a16 for cycles going to the bios space (but not the feature space) in the fwh. if ich is strapped for top-swap (gnt[6]# is low at rising edge of pwrok), then this bit cannot be cleared by software. the strap jumper should be removed and the system rebooted.
intel ? i/o controller hub 6 (ich6) family datasheet 277 chipset configuration registers 7.1.56 fd?function disable register offset address: 3418?341bh attribute: r/w, ro default value: see bit description size: 32-bit the uhci functions must be disabled from highes t function number to lo west. for example, if only three uhcis are wanted, software must disable uhci #4 (ud4 bit set). when disabling uhcis, the ehci structural parameters registers must be updated with coherent information in ?number of companion controll ers? and ?n_ports? fields. when disabling a function, only th e configuration space is disabled. software must en sure that all functionality within a controller that is not desired (such as memory spaces, i/o spaces, and dma engines) is disabled prior to disabling the function. when a function is disabled, software must not attempt to re-enable it. a disabled function can only be re-enabled by a platform reset. bit description 31:20 reserved 19 pci express 4 disable (pe4d) ? r/w. default is 0. when disabled, the link for this port is put into the ?link down? state. 0 = pci express* port #4 is enabled. 1 = pci express port #4 is disabled. 18 pci express 3 disable (pe3d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #3 is enabled. 1 = pci express port #3 is disabled. 17 pci express 2 disable (pe2d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #2 is enabled. 1 = pci express port #2 is disabled. 16 pci express 1 disable (pe1d) ? r/w. default is 0. when disabled, the link for this port is put into the link down state. 0 = pci express port #1 is enabled. 1 = pci express port #1 is disabled. 15 ehci disable (ehcid) ? r/w. default is 0. 0 = the ehci is enabled. 1 = the ehci is disabled. 14 lpc bridge disable (lbd) ? r/w. default is 0. 0 = the lpc bridge is enabled. 1 = the lpc bridge is disabled. unlike the other di sables in this register, the following additional spaces will no longer be decoded by the lpc bridge: ? memory cycles below 16 mb (1000000h) ? i/o cycles below 64 kb (10000h) ? the internal i/oxapic at fec0_0000 to fecf_ffff memory cycles in the lpc bios range below 4 gb will still be decoded w hen this bit is set, but the aliases at the top of 1 mb (the e and f segment) no longer will be decoded. 13:12 reserved 11 uhci #4 disable (u4d) ? r/w. default is 0. 0 = the 4th uhci (ports 6 and 7) is enabled. 1 = the 4th uhci (ports 6 and 7) is disabled. 10 uhci #3 disable (u3d) ? r/w. default is 0. 0 = the 3rd uhci (ports 4 and 5) is enabled. 1 = the 3rd uhci (ports 4 and 5) is disabled.
278 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers 7.1.57 cg?clock gating offset address: 341c?341fh attribute: r/w, ro default value: 00000000h size: 32-bit 9 uhci #2 disable (u2d) ? r/w. default is 0. 0 = the 2nd uhci (ports 2 and 3) is enabled. 1 = the 2nd uhci (ports 2 and 3) is disabled. 8 uhci #1 disable (u1d) ? r/w. default is 0. 0 = the 1st uhci (ports 0 and 1) is enabled. 1 = the 1st uhci (ports 0 and 1) is disabled. 7 hide internal lan (hil) ? r/w. default is 0. 0 = the lan controller is enabled. 1 = the lan controller is disabled and will not decode configuration cycles off of pci. 6 ac ?97 modem disable (amd) ? r/w. default is 0. 0 = the ac ?97 modem function is enabled. 1 = the ac ?97 modem function is disabled. 5 ac ?97 audio disable (aad) ? r/w. default is 0. 0 = the ac ?97 audio function is enabled. 1 = the ac ?97 audio function is disabled. 4 intel high definition audio disable (zd) ? r/w. default is 0. 0 = the intel high definition audio controller is enabled. 1 = the intel high definition audio contro ller is disabled and its pci configuration space is not accessible. 3 sm bus disable (sd) ? r/w. default is 0. 0 = the sm bus controller is enabled. 1 = the sm bus controller is disabled. in ich5 and previous, this also dis abled the i/o space. in ich6, it only disables the configuration space. 2 serial ata disable (sad) ? r/w. default is 0. 0 = the sata controller is enabled. 1 = the sata controller is disabled. 1 parallel ata disable (pad) ? r/w. default is 0. 0 = the pata controller is enabled. 1 = the pata controller is disabled and its pci configuration space is not accessible. 0reserved bit description bit description 31:1 reserved 0 pci express root port static clock gate enable (pescg) ? r/w. 0 = static clock gating is disabled for the pci express* root port. 1 = static clock gating is enabled for the pci express root port when the corresponding port is disabled in the function disabl e register (chipset configur ation registers:offset 3418h) fd.pe1d, fd.pe2d, fd.pe3d or fd.pe4d. in addition to the pci express function disable r egister, the pci express root port physical layer static clock gating is also qualified by the root port configuration rpc.pc (chipset configuration registers:offset 0224h:bits 1:0) as the physica l layer may be required by an enabled port in a x4 configuration.
intel ? i/o controller hub 6 (ich6) family datasheet 279 chipset configuration registers 7.1.58 csir1?chipset initialization register 1 offset address: 3e08?3e09h attribute: r/w default value: 0000h size: 16-bits 7.1.59 csir2?chipset initialization register 2 offset address: 3e48?3e49h attribute: r/w default value: 0000h size: 16-bits 7.1.60 csir3?chipset initialization register 3 offset address: 3e0eh attribute: r/w default value: 00h size: 8-bits 7.1.61 csir4?chipset initialization register 4 offset address: 3e4eh attribute: r/w default value: 00h size: 8-bits bit description 15:8 reserved 7 chipset initialization register 1 bit[7] ? r/w. bios sets this bit to 1. 6:0 reserved bit description 15:8 reserved 7 chipset initialization register 2 bit[7] ? r/w. bios sets this bit to 1. 6:0 reserved bit description 7 chipset initialization register 3 bit[7] ? r/w. bios sets this bit to 1. 6:0 reserved bit description 7 chipset initialization register 4 bit[7] ? r/w. bios sets this bit to 1. 6:0 reserved
280 intel ? i/o controller hub 6 (i ch6) family datasheet chipset configuration registers
intel ? i/o controller hub 6 (ich6) family datasheet 281 lan controller registers (b1:d8:f0) 8 lan controller registers (b1:d8:f0) the ich6 integrated lan contro ller appears to reside at pci device 8, function 0 on the secondary side of the ich6?s virtual pci-to-pci bridge. this is typically bus 1, but may be assigned a different number depending upon system configuration. the la n controller acts as both a master and a slave on the pci bus. as a mast er, the lan controller in teracts with the system main memory to access data for tr ansmission or deposit received data . as a slave, some of the lan controller?s control structures are accessed by the host processor to read or write information to the on-chip registers. the processor also provides the l an controller with the necessary commands and pointers that allow it to pr ocess receive and transmit data. 8.1 pci configuration registers (lan controller?b1:d8:f0) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). . table 8-1. lan controller pci register addr ess map (lan controller?b1:d8:f0) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 1065h ro 04?05h pcicmd pci command 0000h ro, r/w 06?07h pcists pci status 0290h ro, r/wc 08h rid revision identification see register description. ro 0ah scc sub class code 00h ro 0bh bcc base class code 02 ro 0ch cls cache line size 00h r/w 0dh pmlt primary master latency timer 00h r/w 0eh headtyp header type 00h ro 10?13h csr_mem_base csr memory?mapped base address 00000008h r/w, ro 14?17h csr_io_base csr i/o?mapped base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h ro 2e?2fh sid subsystem identification 0000h ro 34h cap_ptr capabilities pointer dch ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin 01h ro 3eh min_gnt minimum grant 08h ro 3fh max_lat maximum latency 38h ro dch cap_id capability id 01h ro ddh nxt_ptr next item pointer 00h ro
282 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.1 vid?vendor identification register (lan controller?b1:d8:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 8.1.2 did?device identification register (lan controller?b1:d8:f0) offset address: 02 ? 03h attribute: ro default value: 1065h size: 16 bits de?dfh pm_cap power management capabilities fe21h (desktop) 7e21h (mobile) ro e0?e1h pmcsr power management control/status 0000h r/w, ro, r/wc e3 pcidata pci power management data 00h ro table 8-1. lan controller pci register address map (lan controller?b1:d8:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-bit value assi gned to the ich6 integrated lan controller. 1. if the eeprom is not present (or not properly pr ogrammed), reads to the device id return the default value of 1065h. 2. if the eeprom is present (and properly programmed) and if the value of word 23h is not 0000h or ffffh, the device id is loaded from t he eeprom, word 23h after the hardware reset. (see section 8.1.14 - sid, subsystem id of lan controller for detail)
intel ? i/o controller hub 6 (ich6) family datasheet 283 lan controller registers (b1:d8:f0) 8.1.3 pcicmd?pci command register (lan controller?b1:d8:f0) offset address: 04 ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable. 1 = disables lan controller to assert its inta signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. the integrated lan controller will not run fast back-to-back pci cycles. 8 serr# enable (serr_en) ? r/w. 0 = disable. 1 = enable. allow serr# to be asserted. 7 wait cycle control (wcc) ? ro. hardwired to 0. not implemented. 6 parity error response (per) ? r/w. 0 = the lan controller will ignore pci parity errors. 1 = the integrated lan controller will take norma l action when a pci parity error is detected and will enable generation of parity on dmi. 5 vga palette snoop (vps) ? ro. hardwired to 0. not implemented. 4 memory write and invalidate enable (mwie) ? r/w. 0 = disable. the lan controller will not us e the memory write and invalidate command. 1 = enable. 3 special cycle enable (sce) ? ro. hardwired to 0. the lan controller ignores special cycles. 2 bus master enable (bme) ? r/w. 0 = disable. 1 = enable. the ich6?s integrated lan contro ller may function as a pci bus master. 1 memory space enable (mse) ? r/w. 0 = disable. 1 = enable. the ich6?s integrated lan controller will respond to the memory space accesses. 0 i/o space enable (iose) ? r/w. 0 = disable. 1 = enable. the ich6?s integrated lan controll er will respond to the i/o space accesses.
284 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.4 pcists?pci status register (lan controller?b1:d8:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = the intel ? ich6?s integrated lan controller has detected a parity error on the pci bus (will be set even if parity error response is disabled in the pci command register). 14 signaled system error (sse) ? r/wc. 0 = integrated lan controller has not asserted serr# 1 = the ich6?s integrated lan controller has as serted serr#. serr# can be routed to cause nmi, smi#, or interrupt. 13 master abort status ( rma) ? r/wc. 0 = master abort not generated 1 = the ich6?s integrated lan controller (as a pci master) has generated a master abort. 12 received target abort (rta) ? r/wc. 0 = target abort not received. 1 = the ich6?s integrated lan controller (as a pci master) has received a target abort. 11 signaled target abort (sta) ? ro. hardwired to 0. the device will never signal target abort. 10:9 devsel# timing status (dev_sts) ? ro. 01h = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = parity error not detected (conditions below are not met). 1 = all of the following three conditions have been met: 1.the lan controller is acting as bus master 2.the lan controller has asserted perr# (for reads) or detected perr# asserted (for writes) 3.the parity error response bit in the lan controller?s pci command register is set. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. the device can accept fast back-to- back transactions. 6 user definable features (udf) ? ro. hardwired to 0. not implemented. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. the device does not support 66 mhz pci. 4 capabilities list (cap_list) ? ro. 0 = the eeprom indicates that the integrated lan controller does not support pci power management. 1 = the eeprom indicates that the integrated lan controller supports pci power management. 3 interrupt status (ints) ? ro. this bit indicates that an inte rrupt is pending. it is independent from the state of the interrupt enable bit in the command register. 2:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 285 lan controller registers (b1:d8:f0) 8.1.5 rid?revision identification register (lan controller?b1:d8:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 8.1.6 scc?sub class code register (lan controller?b1:d8:f0) offset address: 0ah attribute: ro default value: 00h size: 8 bits 8.1.7 bcc?base-class code register (lan controller?b1:d8:f0) offset address: 0bh attribute: ro default value: 02h size: 8 bits bit description 7:0 revision id (rid) ? ro. this field is an 8-bit value that indicates the revision number for the integrated lan controller. the thr ee least significant bits in this register may be overridden by the id and rev id fields in the eeprom. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register. bit description 7:0 sub class code (scc) ? ro. this 8-bit value specifies the sub- class of the devic e as an ethernet controller. bit description 7:0 base class code (bcc) ? ro. this 8-bit value specifies the base class of the device as a network controller.
286 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.8 cls?cache line size register (lan controller?b1:d8:f0) offset address: 0ch attribute: r/w default value: 00h size: 8 bits 8.1.9 pmlt?primary master latency timer register (lan controller?b1:d8:f0) offset address: 0dh attribute: r/w default value: 00h size: 8 bits 8.1.10 headtyp?header type register (lan controller?b1:d8:f0) offset address: 0eh attribute: ro default value: 00h size: 8 bits bit description 7:5 reserved 4:3 cache line size (cls) ? r/w. 00 = memory write and invalidate (mwi) command will not be used by the integrated lan controller. 01 = mwi command will be used with cache line size se t to 8 dwords (only set if a value of 08h is written to this register). 10 = mwi command will be used with cache line size set to 16 dwords (only set if a value of 10h is written to this register). 11 = invalid. mwi command will not be used. 2:0 reserved bit description 7:3 master latency timer count (mltc) ? r/w. this field defines t he number of pci clock cycles that the integrated lan controller may own the bus while acting as bus master. 2:0 reserved bit description 7 multi-function device (mfd) ? ro. hardwired to 0 to indicate a single function device. 6:0 header type (htype) ? ro. this 7-bit field identifies the header layout of the configuration space as an ethernet controller.
intel ? i/o controller hub 6 (ich6) family datasheet 287 lan controller registers (b1:d8:f0) 8.1.11 csr_mem_base ? cs r memory-mapped base address register (lan controller?b1:d8:f0) offset address: 10 ? 13h attribute: r/w, ro default value: 00000008h size: 32 bits note: the ich6?s integrated lan c ontroller requires one bar for memory mapping. software determines which bar (memory or i/o) is us ed to access the lan controller?s csr registers. 8.1.12 csr_io_base ? csr i/o-m apped base address register (lan controller?b1:d8:f0) offset address: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits note: the ich6?s integrated lan c ontroller requires one bar for memory mapping. software determines which bar (memory or i/o) is us ed to access the lan controller?s csr registers. 8.1.13 svid ? subsystem vendor identification (lan controller?b1:d8:f0) offset address: 2c ? 2d attribute: ro default value: 0000h size: 16 bits bit description 31:12 base address (mem_addr) ? r/w. this field contains the upper 20 bits of the base address provides 4 kb of memory-mapped space for the lan controller?s control/status registers. 11:4 reserved 3 prefetchable (mem_pf) ? ro. hardwired to 0 to indicate that this is not a pre-fetchable memory- mapped address range. 2:1 type (mem_type) ? ro. hardwired to 00b to indicate the memory-mapped address range may be located anywhere in 32-bit address space. 0 memory-space indicator (mem_space) ? ro. hardwi red to 0 to indicate that this base address maps to memory space. bit description 31:16 reserved 15:6 base address (io_addr) ? r/w. this field provides 64 bytes of i/o-mapped address space for the lan controller?s control/status registers. 5:1 reserved 0 i/o space indicator (io_space) ? ro. hardwired to 1 to indicate that this base address maps to i/o space. bit description 15:0 subsystem vendor id (svid) ? ro. see section 8.1.14 for details.
288 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.14 sid ? subsystem identification (lan controller?b1:d8:f0) offset address: 2e ? 2fh attribute: ro default value: 0000h size: 16 bits note: the ich6?s integrated lan controller provide s support for configurable subsystem id and subsystem vendor id fields. after reset, the lan controller automatically reads addresses ah through ch, and 23h of the eeprom. the lan controller checks bits 15:13 in the eeprom word ah, and functions according to table 8-2 . notes: 1. the revision id is subject to change according to the silicon stepping. 2. the device id is loaded from word 23h only if the value of word 23h is not 0000h or ffffh 8.1.15 cap_ptr ? ca pabilities pointer (lan controller?b1:d8:f0) offset address: 34h attribute: ro default value: dch size: 8 bits 8.1.16 int_ln ? interrupt line register (lan controller?b1:d8:f0) offset address: 3ch attribute: r/w default value: 00h size: 8 bits bit description 15:0 subsystem id (sid) ? ro. table 8-2. configuration of subsystem id and subsystem vendor id via eeprom bits 15:14 bit 13 device id vendor id revision id subsystem id subsystem vendor id 11b, 10b, 00b x 1051h 8086h 00h 0000h 0000h 01b 0b word 23h 8086h 00h word bh word ch 01b 1b word 23h word ch 80h + word ah, bits 10:8 word bh word ch bit description 7:0 capabilities pointer (cap_ptr) ? ro. hardwired to dch to indicate the offset within configuration space for the location of the power management registers. bit description 7:0 interrupt line (int_ln) ? r/w. this field identifies the sy stem interrupt line to which the lan controller?s pci interrupt request pin (as defin ed in the interrupt pin register) is routed.
intel ? i/o controller hub 6 (ich6) family datasheet 289 lan controller registers (b1:d8:f0) 8.1.17 int_pn ? interrupt pin register (lan controller?b1:d8:f0) offset address: 3dh attribute: ro default value: 01h size: 8 bits 8.1.18 min_gnt ? minimum grant register (lan controller?b1:d8:f0) offset address: 3eh attribute: ro default value: 08h size: 8 bits 8.1.19 max_lat ? maxi mum latency register (lan controller?b1:d8:f0) offset address: 3fh attribute: ro default value: 38h size: 8 bits 8.1.20 cap_id ? capability identification register (lan controller?b1:d8:f0) offset address: dch attribute: ro default value: 01h size: 8 bits bit description 7:0 interrupt pin (int_pn) ? ro. hardwired to 01h to indicate that the lan controller?s interrupt request is connected to pirqa#. however, in t he ich6 implementation, when the lan controller interrupt is generated pirqe# will go active, not pi rqa#. note that if the pirqe# signal is used as a gpi, the external visibility will be lost (though pirqe# will still go active internally). bit description 7:0 minimum grant (min_gnt) ? ro. this field indicates the amount of time (in increments of 0.25 s) that the lan controller needs to retain ownership of the pci bus when it initiates a transaction. bit description 7:0 maximum latency (max_lat) ? ro. this field defines how of ten (in increments of 0.25 s) the lan controller needs to access the pci bus. bit description 7:0 capability id (cap_id) ? ro. hardwired to 01h to indicate that the intel ? ich6?s integrated lan controller supports pci power management.
290 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.21 nxt_ptr ? next item pointer (lan controller?b1:d8:f0) offset address: ddh attribute: ro default value: 00h size: 8 bits 8.1.22 pm_cap ? power ma nagement capabilities (lan controller?b1:d8:f0) offset address: de ? dfh attribute: ro default value: fe21h (in desktop) size: 16 bits 7e21h (in mobile) bit description 7:0 next item pointer (nxt_ptr) ? ro. hardwired to 00b to indicate that power management is the last item in the capabilities list. bit description 15:11 pme support (pme_sup) ? ro. hardwired to 11111b. th is 5-bit field indicates the power states in which the lan controller may assert pme#. t he lan controller supports wake-up in all power states. 10 d2 support (d2_sup) ? ro. hardwired to 1 to indicate that the lan controller supports the d2 power state. 9 d1 support (d1_sup) ? ro. hardwired to 1 to indicate that the lan controller supports the d1 power state. 8:6 auxiliary current (aux_cur) ? ro. hardwired to 000b to indicate that the lan controller implements the data registers. the auxiliary pow er consumption is the same as the current consumption reported in the d3 state in the data register. 5 device specific initialization (dsi) ? ro. hardwired to 1 to indicate that special initialization of this function is required (beyond the standard pci conf iguration header) before t he generic class device driver is able to use it. dsi is required fo r the lan controller after d3-to-d0 reset. 4reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to indicate that t he lan controller does not require a clock to generate a power management event. 2:0 version (ver) ? ro. hardwired to 010b to indicate that the lan controller complies with of the pci power management specification, revision 1.1.
intel ? i/o controller hub 6 (ich6) family datasheet 291 lan controller registers (b1:d8:f0) 8.1.23 pmcsr ? power management control/ status register (lan controller?b1:d8:f0) offset address: e0 ? e1h attribute: ro, r/w, r/wc default value: 0000h size: 16 bits bit description 15 pme status (pme_stat) ? r/wc. 0 = software clears this bit by writing a 1 to it. this also de-asserts the pme# signal and clears the pme status bit in the power management drive r register. when the pme# signal is enabled, the pme# signal reflects the state of the pme status bit. 1 = set upon occurrence of a wake-up event, independent of the state of the pme enable bit. 14:13 data scale (dscale) ? ro. this field indicates the data regi ster scaling factor. it equals 10b for registers 0 through 8 and 00b for registers nine th rough fifteen, as selected by the ?data select? field. 12:9 data select (dsel) ? r/w. this field is used to select which data is reported through the data register and data scale field. 8 pme enable (pme_en) ? r/w. this bit enables the ich6?s integr ated lan controller to assert pme#. 0 = the device will not assert pme#. 1 = enable pme# assertion when pme status is set. 7:5 reserved 4 dynamic data (dyn_dat) ? ro. hardwired to 0 to indicate that the device does not support the ability to monitor the power consumption dynamically. 3:2 reserved 1:0 power state (pwr_st) ? r/w. this 2-bit field is used to determine the current power state of the integrated lan controller, and to put it into a new po wer state. the definition of the field values is as follows: 00 = d0 01 = d1 10 = d2 11 = d3
292 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.1.24 pcidata ? pci power management data register (lan controller?b1:d8:f0) offset address: e3h attribute: ro default value: 00h size: 8 bits the data register is an 8-bit read only register that provides a m echanism for the ich6?s integrated lan controller to report state dependent maximum power consumption and heat dissipation. the value reported in this register depends on the valu e written to the data select field in the pmcsr register. the power measurements defined in this register have a dynamic range of 0 w to 2.55 w with 0.01 w resolution, scaled according to the data scale field in the pmcsr. the structure of the data register is given in table 8-3 . bit description 7:0 power management data (pwr_mgt) ? ro. state dependent power consumption and heat dissipation data. table 8-3. data register structure data select data scale data reported 0 2 d0 power consumption 1 2 d1 power consumption 2 2 d2 power consumption 3 2 d3 power consumption 4 2 d0 power dissipated 5 2 d1 power dissipated 6 2 d2 power dissipated 7 2 d3 power dissipated 8 2 common function power dissipated 9?15 0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 293 lan controller registers (b1:d8:f0) 8.2 lan control / status registers (csr) ( lan controller? b1:d8:f0) table 8-4. intel ? ich6 integrated lan controller csr space register address map offset mnemonic register name default type 00h?01h scb_sta system control block status word 0000h r/wc, ro 02h?03h scb_cmd system control block command word 0000h r/w, wo 04h?07h scb_genpnt system control block general pointer 0000 0000h r/w 08h?0bh port port interface 0000 0000h r/w (special) 0ch?0dh ? reserved ? ? 0eh eeprom_cntl eeprom control 00 r/w, ro, wo 0fh ? reserved ? ? 10h?13h mdi_cntl management data interface control 0000 0000h r/w (special) 14h?17h rec_dma_bc receive dma byte count 0000 0000h ro 18h erec_intr early receive interrupt 00h r/w 19?1ah flow_cntl flow control 0000h ro, r/w (special) 1bh pmdr power management driver 00h r/wc 1ch gencntl general control 00h r/w 1dh gensta general status 00h ro 1eh ? reserved ? ? 1fh smb_pci smb via pci 27h r/w, ro 20h?3ch ? reserved ? ?
294 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.1 scb_sta?system control block status word register (lan controller?b1:d8:f0) offset address: 00 ? 01h attribute: r/wc, ro default value: 0000h size: 16 bits the ich6?s integrated lan controller places the status of its command unit (cu) and receive unit (rc) and interrupt indications in th is register for the processor to read. bit description 15 command unit (cu) executed (cx) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = interrupt signaled because the cu has comple ted executing a command with its interrupt bit set. 14 frame received (fr) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = interrupt signaled because the receive unit (ru) has finished receiving a frame. 13 cu not active (cna) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = the command unit left the active state or entered the idle state. there are 2 distinct states of the cu. when configured to generate cna interrupt, the interrupt will be activated when the cu leaves the active state and enters either the idle or the suspended state. when configured to generate ci interrupt, an interrupt will be generated only when the cu enters the idle state. 12 receive not ready (rnr) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = interrupt signaled because the receive unit left the ready state. this may be caused by an ru abort command, a no resources situation, or set suspend bit due to a filled receive frame descriptor. 11 management data interrupt (mdi) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = set when a management data interface read or write cycle has completed. the management data interrupt is enabled through the interrupt enable bit (bit 29 in the management data interface control register in the csr). 10 software interrupt (swi) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = set when software generates an interrupt. 9 early receive (er) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = indicates the occurrence of an early receive interrupt. 8 flow control pause (fcp) ? r/wc. 0 = software acknowledges the interrupt and clear s this bit by writing a 1 to the bit position. 1 = indicates flow control pause interrupt. 7:6 command unit status (cus) ? ro. 00 = idle 01 = suspended 10 = lpq (low priority queue) active 11 = hpq (high priority queue) active
intel ? i/o controller hub 6 (ich6) family datasheet 295 lan controller registers (b1:d8:f0) 5:2 receive unit status (rus) ? ro. 1:0 reserved bit description value status value status 0000b idle 1000b reserved 0001b suspended 1001b suspended with no more rbds 0010b no resources 1010b no resources due to no more rbds 0011b reserved 1011b reserved 0100b ready 1100b ready with no rbds present 0101b reserved 1101b reserved 0110b reserved 1110b reserved 0111b reserved 1111b reserved
296 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.2 scb_cmd?system control block command word register (lan co ntroller?b1:d8:f0) offset address: 02 ? 03h attribute: r/w, wo default value: 0000h size: 16 bits the processor places commands for the command and r eceive units in this register. interrupts are also acknowledged in this register. bit description 15 cx mask (cx_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of a cx interrupt. 14 fr mask (fr_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an fr interrupt. 13 cna mask (cna_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of a cna interrupt. 12 rnr mask (rnr_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an rnr interrupt. 11 er mask (er_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an er interrupt. 10 fcp mask (fcp_msk) ? r/w. 0 = interrupt not masked. 1 = disable the generation of an fcp interrupt. 9 software generated interrupt (si) ? wo. 0 = no effect. 1 = setting this bit causes the lan controller to generate an interrupt. 8 interrupt mask (im) ? r/w. this bit enables or disables the lan controlle r?s assertion of the inta# signal. this bit has higher prec edence that the specific interrupt mask bits and the si bit. 0 = enable the assertion of inta#. 1 = disable the assertion of inta#.
intel ? i/o controller hub 6 (ich6) family datasheet 297 lan controller registers (b1:d8:f0) 7:4 command unit command (cuc) ? r/w. valid values are listed below. all other values are reserved. 0000 = nop: does not affect the current state of the unit. 0001 = cu start : start execution of the first command on the cbl. a pointer to the first cb of the cbl should be placed in the scb general poin ter before issuing this command. the cu start command should only be issued when the cu is in the idle or suspended states (never when the cu is in the active state), and all of the previously issu ed command blocks have been processed and completed by the cu. someti mes it is only possible to determine that all command blocks are completed by checking that the complete bit is set in all previously issued command blocks. 0010 = cu resume: resume operation of the command unit by executing the next command. this command will be ignored if the cu is idle. 0011 = cu hpq start: start execution of the first command on the high priority cbl. a pointer to the first cb of the hpq cbl should be placed in the scb general pointer before issuing this command. 0100 = load dump counters address: indicates to the device where to write dump data when using the dump statistical counters or du mp and reset statistical counters commands. this command must be executed at least once before any usage of the dump statistical counters or dump and reset statistical counters commands. the address of the dump area must be placed in the general pointer register. 0101 = dump statistical counters: tells the device to dump its st atistical counters to the area designated by the load dump counters address command. 0110 = load cu base: the device?s internal cu base register is loaded with the value in the csb general pointer. 0111 = dump and reset statistical counters: indicates to the device to dump its statistical counters to the area designated by the load dump counters address command, and then to clear these counters. 1010 = cu static resume: resume operation of the command unit by executing the next command. this command will be ignored if t he cu is idle. this command should be used only when the cu is in the suspended stat e and has no pending cu resume commands. 1011 = cu hpq resume: resume execution of the first command on the hpq cbl. this command will be ignored if the hpq was never started. 3 reserved 2:0 receive unit command ( ruc) ? r/w. valid values are: 000 = nop: does not affect the current state of the unit. 001 = ru start: enables the receive unit. the pointer to the rfa must be placed in the scb general pointer before using this command. the device pre-fetches the first rfd and the first rbd (if in flexible mode) in preparation to receive incoming frames that pass its address filtering. 010 = ru resume: resume frame reception (only when in suspended state). 011 = rcv dma redirect: resume the rcv dma when configured to ?direct dma mode.? the buffers are indicated by an rbd chain which is pointed to by an offset stored in the general pointer register (this offset will be added to the ru base). 100 = ru abort: abort ru receive operation immediately. 101 = load header data size (hds): this value defines the size of the header portion of the rfds or receive buffers. the hds value is defined by the lower 14 bits of the scb general pointer, so bits 31:15 should always be set to 0? s when using this command. once a load hds command is issued, the device expects only to fi nd header rfds, or be used in ?rcv direct dma mode? until it is reset. note that the value of hds should be an even, non-zero number. 110 = load ru base: the device?s internal ru base register is loaded with the value in the scb general pointer. 111 = rbd resume: resume frame reception into the rfa. this command should only be used when the ru is already in the ?no resource s due to no rbds? state or the ?suspended with no more rbds? state. bit description
298 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.3 scb_genpnt?system cont rol block general pointer register (lan co ntroller?b1:d8:f0) offset address: 04 ? 07h attribute: r/w default value: 0000 0000h size: 32 bits 8.2.4 port?port interface register (lan controller?b1:d8:f0) offset address: 08 ? 0bh attribute: r/w (special) default value: 0000 0000h size: 32 bits the port interface allows the processor to reset the ich6?s internal lan controller, or perform an internal self test. the port dword may be wri tten as a 32-bit entity, two 16-bit entities, or four 8-bit entities. the lan c ontroller will only accept the command afte r the high byte (offset 0bh) is written; therefore, the high byte must be written last. bit description 15:0 scb general pointer ? r/w. the scb general pointer register is programmed by software to point to various data structures in main memory depending on the current scb command word. bit description 31:4 pointer field (port_ptr) ? r/w (special). a 16-byte aligned addre ss must be written to this field when issuing a self-test command to the port interf ace.the results of the self test will be written to the address specified by this field. 3:0 port function selection (port_func) ? r/w (special). valid values are listed below. all other values are reserved. 0000 = port software reset: completely resets the lan contro ller (all csr and pci registers). this command should not be used when the device is active. if a port software reset is desired, software should do a selective rese t (described below), wait for the port register to be cleared (completion of the selective reset), and then issue the port software reset command. software should wait approximately 10 s after issuing this command before attempting to access t he lan controller?s registers again. 0001 = self test: the self-test begins by issuing an inte rnal selective reset followed by a general internal self-test of the lan controller. the resu lts of the self-test are written to memory at the address specified in the pointer field of this register. the format of the self-test result is shown in table 8-5 . after completing the self-test and writing the results to memory, the lan controller will execute a full internal reset and will re-ini tialize to the default configuration. self-test does not generate an interrupt of similar indicator to the host processor upon completion. 0010 = selective reset: sets the cu and ru to the idle state, but otherwise maintains the current configuration parameters (ru and cu base, hdssize, error counters, configure information and individual/multicast addresse s are preserved). software should wait approximately 10 s after issuing this command before attempting to access the lan controller?s registers again.
intel ? i/o controller hub 6 (ich6) family datasheet 299 lan controller registers (b1:d8:f0) 8.2.5 eeprom_cntl?eeprom control register (lan controller?b1:d8:f0) offset address: 0eh attribute: ro, r/w, wo default value: 00h size: 8 bits the eeprom control register is a 16-bit field that enables a read from and a write to the external eeprom. table 8-5. self-test results format bit description 31:13 reserved 12 general self-test result (self_tst) ? r/w (special). 0 = pass 1 = fail 11:6 reserved 5 diagnose result (diag_rslt) ? r/w (special). this bit provi des the result of an internal diagnostic test of the serial subsystem. 0 = pass 1 = fail 4 reserved 3 register result (reg_rslt) ? r/w (special). this bit provides the result of a test of the internal parallel subsystem registers. 0 = pass 1 = fail 2 rom content result (rom_rslt) ? r/w (special). this bit provides the result of a test of the internal microcode rom. 0 = pass 1 = fail 1:0 reserved bit description 7:4 reserved 3 eeprom serial data out (eedo) ? ro. note that this bit represents ?data out? from the perspective of the eeprom device. this bit contains the value read from the eeprom when performing read operations. 2 eeprom serial data in (eedi) ? wo. note that this bit represent s ?data in? from the perspective of the eeprom device. the value of this bit is written to the eeprom when performing write operations. 1 eeprom chip select (eecs) ? r/w. 0 = drives the ich6?s ee_cs signal low to disable the eeprom. this bit must be set to 0 for a minimum of 1 s between consecutive instruction cycles. 1 = drives the ich6?s ee_cs signal high, to enable the eeprom. 0 eeprom serial clock (eesk) ? r/w. toggling this bi t clocks data into or out of the eeprom. software must ensure that this bit is toggled at a rate that meets the eeprom component?s minimum clock freq uency specification. 0 = drives the ich6?s ee_shclk signal low. 1 = drives the ich6?s ee_shclk signal high.
300 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.6 mdi_cntl?management da ta interface (mdi) control register (lan co ntroller?b1:d8:f0) offset address: 10 ? 13h attribute: r/w (special) default value: 0000 0000h size: 32 bits the management data interface (mdi) control regist er is a 32-bit field and is used to read and write bits from the lan connect component. this register may be written as a 32-bit entity, two 16-bit entities, or four 8-bit entities. the lan controller will only accept the command after the high byte (offset 13h) is written; therefore, the high byte must be written last. 8.2.7 rec_dma_bc?receive dma byte count register (lan controller?b1:d8:f0) offset address: 14 ? 17h attribute: ro default value: 0000 0000h size: 32 bits bit description 31:30 these bits are reserved and should be set to 00b. 29 interrupt enable ? r/w (special). 0 = disable. 1 = enables the lan controller to assert an interrupt to indicate the end of an mdi cycle. 28 ready ? r/w (special). 0 = expected to be reset by software at the same time the command is written. 1 = set by the lan controller at the end of an mdi transaction. 27:26 opcode ? r/w (special). these bits define the opcode: 00 = reserved 01 = mdi write 10 = mdi read 11 = reserved 25:21 lan connect address ? r/w (special). this field of bits contains the lan connect address. 20:16 lan connect register address ? r/w (special). this field contains the lan connect register address. 15:0 data ? r/w (special). in a write command, software places the data bits in this field, and the lan controller transfers the data to the external lan connect component. during a read command, the lan controller reads these bits serially from the lan connect, and software reads the data from this location. bit description 31:0 receive dma byte count ? ro. this field keeps track of how many bytes of receive data have been passed into host memory via dma.
intel ? i/o controller hub 6 (ich6) family datasheet 301 lan controller registers (b1:d8:f0) 8.2.8 erec_intr?early receive interrupt register (lan controller?b1:d8:f0) offset address: 18h attribute: r/w default value: 00h size: 8 bits the early receive interrupt register allows the internal l an controller to generate an early interrupt depending on the length of the frame. the lan controller will generate an interrupt at the end of the frame regardless of whether or not early receive interrupts are enabled. note: it is recommended that software not use this register unless receive interrupt latency is a critical performance issue in that particul ar software environment. using this feature may reduce receive interrupt latency, but will also result in the generation of more interrupts, which can degrade system efficiency and performance in some environments. bit description 7:0 early receive count ? r/w. when some non-zero value x is programmed into this register, the lan controller will set the er bit in the scb status word register and assert inta# when the byte count indicates that there are x qwords remaining to be received in the current frame (based on the type/length field of the received frame). no early re ceive interrupt will be generated if a value of 00h (the default value) is programmed into this register.
302 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.9 flow_cntl?flow control register (lan controller?b1:d8:f0) offset address: 19 ? 1ah attribute: ro, r/w (special) default value: 0000h size: 16 bits bit description 15:13 reserved 12 fc paused low ? ro. 0 = cleared when the fc timer reaches 0, or a pause frame is received. 1 = set when the lan controller receives a pause low command with a value greater than 0. 11 fc paused ? ro. 0 = cleared when the fc timer reaches 0. 1 = set when the lan controller receives a paus e command regardless of its cause (fifo reaching flow control threshold, fetching a receive fram e descriptor with its flow control pause bit set, or software writing a 1 to the xoff bit). 10 fc full ? ro. 0 = cleared when the fc timer reaches 0. 1 = set when the lan controller sends a p ause command with a value greater than 0. 9 xoff ? r/w (special). this bit should only be used if the lan controller is configured to operate with ieee frame-based flow control. 0 = this bit can only be cleared by writing a 1 to the xon bit (bit 8 in this register). 1 = writing a 1 to this bit forces the xoff request to 1 and causes the lan co ntroller to behave as if the fifo extender is full. this bit will also be set to 1 when an xoff request due to an ?rfd xoff? bit. 8 xon ? wo. this bit should only be used if the lan cont roller is configured to operate with ieee frame-based flow control. 0 = this bit always returns 0 on reads. 1 = writing a 1 to this bit resets the xoff request to the lan controller, clearing bit 9 in this register. 7:3 reserved 2:0 flow control threshold ? r/w. the lan controller can gene rate a flow control pause frame when its receive fifo is almost full. the value pr ogrammed into this field determines the number of bytes still available in the receive fifo when the pause frame is generated. bits 2:0 free bytes in rx fifo comment 000b 0.50 kb fast system (recommended default) 001b 1.00 kb 010b 1.25 kb 011b 1.50 kb 100b 1.75 kb 101b 2.00 kb 110b 2.25 kb 111b 2.50 kb slow system
intel ? i/o controller hub 6 (ich6) family datasheet 303 lan controller registers (b1:d8:f0) 8.2.10 pmdr?power manage ment driver register (lan controller?b1:d8:f0) offset address: 1bh attribute: r/wc default value: 00h size: 8 bits the ich6?s internal lan controller provides an indication in the pmdr th at a wake-up event has occurred. bit description 7 link status change indication ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the link status change bit is set following a change in link status. 6 magic packet ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when a magic pa cket is received regardless of the magic packet wake-up disable bit in the configuration command and the pme enable bit in the power management control/ status register. 5 interesting packet ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when an ?interesting? packet is received. interesting packets are defined by the lan controller packet filters. 4:3 reserved 2 asf enabled ? ro. this bit is set to 1 when the lan controller is in asf mode. 1 tco request ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set to 1b when the lan c ontroller is busy with tco activity. 0 pme status ? r/wc. this bit is a reflection of the pm e status bit in the power management control/status register (pmcsr). 0 = software clears this bit by wri ting a 1 to it.this also clears the pme status bit in the pmcsr and de-asserts the pme signal. 1 = set upon a wake-up event, independent of the pme enable bit.
304 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.11 gencntl?general control register (lan controller?b1:d8:f0) offset address: 1ch attribute: r/w default value: 00h size: 8 bits 8.2.12 gensta?general status register (lan controller?b1:d8:f0) offset address: 1dh attribute: ro default value: 00h size: 8 bits bit description 7:4 reserved. these bits should be set to 0000b. 3 lan connect software reset ? r/w. 0 = cleared by software to begin normal lan connect operating mode. software must not attempt to access the lan connect interface for at least 1ms after clearing this bit. 1 = software can set this bit to force a reset condition on the lan connect interface. 2 reserved. this bit should be set to 0. 1 deep power-down on link down enable ? r/w. 0 = disable 1 = enable. the ich6?s internal lan controller may enter a deep power-down state (sub-3 ma) in the d2 and d3 power states while the link is dow n. in this state, the lan controller does not keep link integrity. this state is not supported for point-to-point connecti on of two end stations. 0reserved bit description 7:3 reserved 2 duplex mode ? ro. this bit indicates the wire duplex mode. 0 = half duplex 1 = full duplex 1 speed ? ro. this bit indicates the wire speed. 0 = 10 mb/s 1 = 100 mb/s 0 link status indication ? ro. this bit indicates the status of the link. 0 = invalid 1 = valid
intel ? i/o controller hub 6 (ich6) family datasheet 305 lan controller registers (b1:d8:f0) 8.2.13 smb_pci?smb via pci register (lan controller?b1:d8:f0) offset address: 1fh attribute: r/w, ro default value: 27h size: 8 bits software asserts sreq when it wants to isol ate the pci-accessible smbus to the asf registers/ commands. it waits for sgnt to be asserted. at this point scli, sdao, sclo, and sdai can be toggled/read to force asf controller smbus trans actions without affecti ng the external smbus. after all operations are completed, the bus is returned to idle (sclo=1b,sdao=1b, scli=1b, sdai=1b), sreq is released (written 0b). then sg nt goes low to indicate released control of the bus. the logic in the asf controller only asserts or de-asserts sgnt at times when it determines that it is safe to switch (all smbu ses that are switched in/out are idle). when in isolation mode (sgnt=1), software can access the ich6 smbus slaves that allow configuration without aff ecting the external smbus. this incl udes configuratio n register accesses and asf command accesses. however, this capabi lity is not available to the external tco controller. when sgnt=0, the bit-banging and reads are reflected on th e main smbus and the pcisml_sda0, pcisml_scl0 read only bits. bit description 7:6 reserved 5 pcisml_sclo ? ro. smbus clock from the asf controller. 4 pcisml_sgnt ? ro. smbus isolation grant from the asf controller. 3 pcisml_sreq ? r/w. smbus isolation request to the asf controller. 2 pcisml_sdao ? ro. smbus data from the asf controller. 1 pcisml_sdai ? r/w. smbus data to the asf controller. 0 pcisml_scli ? r/w. smbus clock to the asf controller.
306 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.2.14 statistical counters (lan controller?b1:d8:f0) the ich6?s integrated lan controller provides information for network management statistics by providing on-chip statistical counters that count a variety of events associat ed with both transmit and receive. the counters are updated by the lan controller when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). the statistical counters are reported to the software on demand by issuing the dump statistical counter s command or dump and reset statistical counters command in the scb command unit command (cuc) field. table 8-6. statistical counters (sheet 1 of 2) id counter description 0 transmit good frames this counter contains the number of frames that were transmitted properly on the link. it is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the transmit command block status. 4 transmit maximum collisions (maxcol) errors this counter contains the number of frames that were not transmitted because they encountered t he configured maximum num ber of collisions. 8 transmit late collisions (latecol) errors this counter contains the number of frames that were not transmitted since they encountered a collision la ter than the configured slot time. 12 transmit underrun errors a transmit underrun occurs because t he system bus cannot keep up with the transmission. this counter contains the number of frames that were either not transmitted or retransmitted due to a transmit dma underrun. if the lan controller is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. 16 transmit lost carrier sense (crs) this counter contains the number of frames that were transmitted by the lan controller despite the fact that it detected the de-assertion of crs during the transmission. 20 transmit deferred this counter contains the number of frames that were deferred before transmission due to ac tivity on the link. 24 transmit single collisions this counter contains the number of transmitted frames that encountered one collision. 28 transmit multiple collisions this counter contains the number of transmitted frames that encountered more than one collision. 32 transmit total collisions this counter contains the total number of collisions that were encountered while attempting to transmit. this count includes late collisions and frames that encountered maxcol. 36 receive good frames this counter contains the number of frames that were received properly from the link. it is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. 40 receive crc errors this counter contains the number of aligned frames discarded because of a crc error. this counter is updated, if needed, regardless of the receive unit state. the receive crc errors c ounter is mutually exclusive of the receive alignment errors and rece ive short frame errors counters. 44 receive alignment errors this counter contains the number of frames that are both misaligned (for example, crs de-asserts on a non-octal boundary) and contain a crc error. the counter is updated, if needed, regardless of the receive unit state. the receive alignment errors co unter is mutually exclusive of the receive crc errors and receive short frame errors counters.
intel ? i/o controller hub 6 (ich6) family datasheet 307 lan controller registers (b1:d8:f0) the statistical counters are initially set to 0 by the ich6?s integrated lan controller after reset. they cannot be preset to anything other than 0. the lan controller incr ements the counters by internally reading them, incremen ting them and writing them back. this process is invisible to the processor and pci bus. in addition, the counters adhere to the following rules: ? the counters are wrap-around counters. afte r reaching ffffffffh the counters wrap around to 0. ? the lan controller updates the required counters for each frame. it is possible for more than one counter to be updated as multiple errors can occur in a single frame. ? the counters are 32 bits wide and their behavior is fully compatible with the ieee 802.1 standard. the lan controller supports all ma ndatory and recommend statistics functions through the status of the receive header an d directly through these statistical counters. the processor can access the counte rs by issuing a dump statistical counters scb command. this provides a ?snapshot?, in main memory, of the in ternal lan controller st atistical counters. the lan controller supports 21 counters. the dump c ould consist of the either 16, 19, or all 21 counters, depending on the status of the extended statistics counters and tco statistics configuration bits in the configuration command. 48 receive resource errors this counter contains the number of good frames discarded due to unavailability of resources. frames intended for a host whose receive unit is in the no resources state fall into this category. if the lan controller is configured to save bad frames and the status of the received frame indicates that it is a bad frame, the receive resource errors counter is not updated. 52 receive overrun errors this counter contains the number of frames known to be lost because the local system bus was not available. if the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. 56 receive collision detect (cdt) this counter contains the number of frames that encountered collisions during frame reception. 60 receive short frame errors this counter contains the number of received frames that are shorter than the minimum frame length. the receive short frame errors counter is mutually exclusive to the receive alignment errors and receive crc errors counters. a short frame will always increment only the receive short frame errors counter. 64 flow control transmit pause this counter contains the number of flow control frames transmitted by the lan controller. this count includes both the xoff frames transmitted and xon (pause(0)) frames transmitted. 68 flow control receive pause this counter contains the number of flow control frames received by the lan controller. this count includes both the xoff frames received and xon (pause(0)) frames received. 72 flow control receive unsupported this counter contains the number of mac control frames received by the lan controller that are not flow control pause frames. these frames are valid mac control frames that have the predefined mac control type value and a valid address but has an unsupported opcode. 76 receive tco frames this counter contains the number of tco packets received by the lan controller. 78 transmit tco frames this counter contains the number of tco packets transmitted. table 8-6. statistical counters (sheet 2 of 2) id counter description
308 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3 asf configuration registers (lan controller?b1:d8:f0) table 8-7. asf pci configur ation register address map (lan controller?b1:d8:f0) offset mnemonic register name default type e0h asf_rid asf revision identification ech ro e1h smb_cntl smbus control 40h r/w e2h asf_cntl asf control 00h r/w, ro e3h asf_cntl_en asf control enable 00h r/w e4h enable enable 00h r/w e5h apm apm 08h r/w e6?e7h ? reserved ? ? e8h wtim_conf watchdog timer configuration 00h r/w e9h heart_tim heartbeat timer 02h r/w eah retran_int retransmission interval 02h r/w ebh retran_pcl retransmission packet count limit 03h r/w ech asf_wtim1 asf watchdog timer 1 01h r/w edh asf_wtim2 asf watchdog timer 2 00h r/w f0h pet_seq1 pet sequence 1 00h r/w f1h pet_seq2 pet sequence 2 00h r/w f2h sta status 40h r/w f3h for_act forced actions 02h r/w f4h rmcp_snum rmcp sequence number 00h r/w f5h sp_mode special modes x0h r/wc, ro f6h inpoll_tconf inter-poll timer configuration 10h r/w f7h phist_clr poll history clear 00h r/wc f8h pmsk1 polling mask 1 xxh r/w f9h pmsk2 polling mask 2 xxh r/w fah pmsk3 polling mask 3 xxh r/w fbh pmsk4 polling mask 4 xxh r/w fch pmsk5 polling mask 5 xxh r/w fdh pmsk6 polling mask 6 xxh r/w feh pmsk7 polling mask 7 xxh r/w ffh pmsk8 polling mask 8 xxh r/w
intel ? i/o controller hub 6 (ich6) family datasheet 309 lan controller registers (b1:d8:f0) 8.3.1 asf_rid?asf revision identification register (lan controller?b1:d8:f0) offset address: e0h attribute: ro default value: ech size: 8 bits 8.3.2 smb_cntl?smbus control register (lan controller?b1:d8:f0) offset address: e1h attribute: r/w default value: 40h size: 8 bits this register is used to control configurations of the smbus ports. bit description 7:3 asf id ? ro. hardwired to 11101 to identify the asf controller. 2:0 asf silicon revision ? ro. this field provides t he silicon revision. bit description 7 smbus remote control asf enable (smb_rcasf) ? r/w. 0 = legacy descriptors and operations are used. 1 = asf descriptors and operations are used. 6 smbus arp enable (smb_arpen) ? r/w. 0 = disable. 1 = asf enables the smbus arp protocol. 5:4 reserved 3 smbus drive low (smb_drvlo) ? r/w. 0 = asf will not drive the main sm bus signals low while pwr_good = 0. 1 = asf will drive the main smbus signals low while pwr_good = 0. 2:0 reserved
310 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.3 asf_cntl?asf control register (lan controller?b1:d8:f0) offset address: e2h attribute: r/w, ro default value: 00h size: 8 bits this register contains enables for special modes and sos events . ctl_pwrls should be set if asf should be expecting a power loss due to software action. otherwise, an eeprom reload will happen when the power is lost. bit description 7 smbus hang sos enable (ctl_smbhg) ? r/w. 0 = disable 1 = enables smbus hang sos to be sent. 6 watchdog sos enable (ctl_wdg) ? r/w. 0 = disable. 1 = enables watchdog sos to be sent. 5 link loss sos enable (ctl_link) ? r/w. 0 = disable. 1 = enables link loss sos to be sent. 4 os hung status (ctl_oshung) ? ro. 1 = this bit will be set to 1 when asf has detected a watchdog expiration. note: this condition is only clearable by a pci rst# assertion (system reset). 3 power-up sos enable (ctl_pwrup) ? r/w. 0 = disable. 1 = enables power-up sos to be sent. 2reserved 1 receive arp enable (ctl_rxarp) ? r/w. the lan controller interface provides a mode where all packets can be requested. 0 = disable. 1 = enable. asf requests all packets when doing a receive enable. this is necessary in lan controller to get arp packets. note: changes to this bit will not take effect unt il the next receive enable command to the lan. 0 power loss ok (ctl_pwrls) ? r/w. 0 = power loss will reload eeprom 1 = power loss will not reload eeprom
intel ? i/o controller hub 6 (ich6) family datasheet 311 lan controller registers (b1:d8:f0) 8.3.4 asf_cntl_en?asf co ntrol enable register (asf controller?b1:d8:f0) offset address: e3h attribute: r/w default value: 00h size: 8 bits this register is used to enable global processi ng as well as polling. global enable controls all of the smbus processing and packet creation. bit description 7 global enable (cena_all) ? r/w. 0 = disable 1 = all control and polling enabled 6 receive enable (cena_rx) ? r/w. 0 = disable 1 = tco receives enabled. 5 transmit enable (cena_tx) ? r/w. 0 = disable 1 = sos and rmcp transmits enabled 4 asf polling enable (cena_apol) ? r/w. 0 = disable 1 = enable asf sensor polling. 3 legacy polling enable (cena_lpol) ? r/w. 0 = disable 1 = enable legacy sensor polling. 2:0 number of legacy poll devices (cena_nlpol) ? r/w. this 3-bit value indicates how many of the eight possible polling descriptors are active. 000 = first polling descriptor is active. 001 = first two polling descriptors are active. ... 111 = enables all eight descriptors.
312 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.5 enable?enable register (asf controller?b1:d8:f0) offset address: e4h attribute: r/w default value: 00h size: 8 bits this register provides the mechan ism to enable internal sos operations and to enable the remote control functions. bit description 7 enable oshung arps (ena_osharp) ? r/w. 0 = disable 1 = asf will request all packets when in a oshung state. this allows asf to receive arp frames and respond as appropriate. 6 state-based security destination port select (ena_sb0298) ? r/w. 0 = state-based security will be honored on packets received on port 026fh. 1 = packets received on port 0298h will be honored. 5 pet vlan enable (ena_vlan) ? r/w. 0 = disable 1 = indicates a vlan header for pet note: if this bit is set, the pet packet in eeprom must have the vlan tag within the packet. 4reserved 3 system power cycle enable (ena_cycle) ? r/w. 0 = disable 1 = enables rmcp power cycle action. 2 system power-down enable (ena_dwn) ? r/w. 0 = disable 1 = enables rmcp power-down action. 1 system power-up enable (ena_up) ? r/w. 0 = disable 1 = enables rmcp power-up action. 0 system reset enable (ena_rst) ? r/w. 0 = disable 1 = enables rmcp reset action
intel ? i/o controller hub 6 (ich6) family datasheet 313 lan controller registers (b1:d8:f0) 8.3.6 apm?apm register (asf controller?b1:d8:f0) offset address: e5h attribute: r/w default value: 08h size: 8 bits this register contains the configuration bit to disable state-based security. 8.3.7 wtim_conf?watchdog time r configuration register (asf controller?b1:d8:f0) offset address: e8h attribute: r/w default value: 00h size: 8 bits this register contains a single bit that enables the watchdog timer. this bit is not intended to be accessed by software, but should be configured a ppropriately in the eeprom location for this register default. the bit provides real-time control for enabling/disabling the watchdog timer. when set the timer will count down. when cleared the counter will stop. timer start asf smbus messages will set this bit. timer stop asf smbus transactions will clear this bit. bit description 7:4 reserved 3 disable state-based security (apm_dissb) ? r/w. 0 = state-based security on oshung is enabled. 1 = state-based security is disabled and actions are not gated by oshung. 2:0 reserved bit description 7:1 reserved 0 timer enable (wdg_ena) ? r/w. 0 = disable 1 = enable counter
314 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.8 heart_tim?heartbeat timer register (asf controller?b1:d8:f0) offset address: e9h attribute: r/w default value: 02h size: 8 bits the heartbeat timer register implements the hear tbeat timer. this defines the period of the heartbeats packets. it co ntains a down counting value when en abled and the time-out value when the counter is disabled. the timer can be configured a nd enabled in a single write. note: the heartbeat timer controls the heartbeat status packet frequency. the timer is free-running and the configured time is only vali d from one heartbeat to the next . when enabled by software, the next heartbeat may occur in any amount of time less than the configured time. . 8.3.9 retran_int?retransmission interval register (asf controller?b1:d8:f0) offset address: eah attribute: r/w default value: 02h size: 8 bits this register implements the retransmission timer. this is the time between packet transmissions for multiple packets due to a sos. bit description 7:1 heartbeat timer value (hbt_val) ? r/w. heartbeat timer load value in 10.7-second resolution. this field can only be written while the timer is disabled. (10.7 sec ? 23 min range). read as load value when hbt_ena=0. read as decrementing value when hbt_ena=1. timer resolution is 10.7 seconds. a value of 00h is invalid. 0 timer enable (hbt_ena) ? r/w. 0 = disable 1 = enable / reset counter bit description 7:1 retransmit timer value (rtm_val) ? r/w. retransmit timer load value 2.7 second resolution. this field is always writable (2.7 sec ? 5.7 mi n range). timer is accurate to +0 seconds, ? 0.336 seconds. reads always show the load value (decrement value never shown). a value of 00h is invalid. 0reserved
intel ? i/o controller hub 6 (ich6) family datasheet 315 lan controller registers (b1:d8:f0) 8.3.10 retran_pcl?retransmi ssion packet count limit register (asf controller?b1:d8:f0) offset address: ebh attribute: r/w default value: 03h size: 8 bits this register defines the number of packet s that are to be sent due to an sos. 8.3.11 asf_wtim1?asf watchdog timer 1 register (asf controller?b1:d8:f0) offset address: ech attribute: r/w default value: 01h size: 8 bits this register is used to load the low byte of the timer. when read, it reports the decrementing value. this register is not intended to be written by so ftware, but should be configured appropriately in the eeprom location for this register default. timer start asf smbus transactions will load values into this register. once the timer has expired (0000h), the timer will be disabled (edg_ena=0b) and the value in this register will remain at 00h until otherwise changed. 8.3.12 asf_wtim2?asf watchdog timer 2 register (asf controller?b1:d8:f0) offset address: edh attribute: r/w default value: 00h size: 8 bits this register is used to load the high byte of the timer. when read, it reports the decrementing value. this register is not intended to be written by software, but should be configured appropriately in the eeprom location for this register default. timer start asf smbus transactions will load values into this register. once the timer has expired (0000h), the timer will be disabled (edg_ena=0b) and the value in this regi ster will remain at 00h until otherwise changed. bit description 7:0 retransmission packet count limit (rpc_val) ? r/w. this field provides the number of packets to be sent for all sos packe ts that require retransmissions. bit description 7:0 asf watchdog timer 1 (awd1_val) ? r/w. this field provides the low byte of the asf 1-second resolution timer. the timer is accurate to +0 seconds, ?0.336 seconds. bit description 7:0 asf watchdog timer 2 (awd2_val) ? r/w. this field provides the high byte of the asf 1-second resolution timer. the timer is accurate to +0 seconds, ?0.336 seconds.
316 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.13 pet_seq1?pet sequence 1 register (asf controller?b1:d8:f0) offset address: f0h attribute: r/w default value: 00h size: 8 bits this register (low byte) holds the current value of the pet sequ ence number. this field is read/ write-able through this register, and is also automatically incremented by the hardware when new pet packets are generated. by policy, software shou ld not write to this register unless transmission is disabled. 8.3.14 pet_seq2?pet sequence 2 register (asf controller?b1:d8:f0) offset address: f1h attribute: r/w default value: 00h size: 8 bits this register (high byte) holds the current value of the pet sequence number. this field is read/ write-able through this register, and is also automatically incremented by the hardware when new pet packets are generated. by policy, software shou ld not write to this register unless transmission is disabled. bit description 7:0 pet sequence byte 1 (pseq1_val) ? r/w. this field provides the low byte. bit description 7:0 pet sequence byte 2 (pseq2_val) ? r/w. this field provides the high byte.
intel ? i/o controller hub 6 (ich6) family datasheet 317 lan controller registers (b1:d8:f0) 8.3.15 sta?status register (asf controller?b1:d8:f0) offset address: f2h attribute: r/w default value: 40h size: 8 bits this register gives status indication about several aspects of asf. bit description 7 eeprom loading (sta_load) ? r/w. eeprom defaults are in the process of being loaded when this bit is a 1. 6 eeprom invalid checksum indication (sta_icrc) ? r/w. this bit should be read only after the eec_load bit is a 0. 0 = valid 1 = invalid checksum detected for asf portion of the eeprom. 5:4 reserved 3 power cycle status (sta_cycle) ? r/w. 0 = software clears th is bit by writing a 1. 1 = this bit is set when a power cycle operation has been issued. 2 power down status (sta_down) ? r/w. 0 = software clears th is bit by writing a 1 1 = this bit is set when a power down operation has been issued. 1 power up status (sta_up) ? r/w. 0 = software clears th is bit by writing a 1 1 = this bit is set when a powe r up operation has been issued. 0 system reset status (sta_rst) ? r/w. 0 = software clears th is bit by writing a 1 1 = this bit is set when a system reset operation has been issued.
318 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.16 for_act?forced actions register (asf controller?b1:d8:f0) offset address: f3h attribute: r/w default value: 02h size: 8 bits this register contains many diff erent forcible actions including apm functions, flushing internal pending sos operations, software sos operations, software reset, and eeprom reload. writes to this register must only set one bit per-write. setting multiple bits in a single write can have indeterminate results. note: for bits in this register, writing a 1 invokes the operation. the bits self-clear immediately. 8.3.17 rmcp_snum?rmcp sequence number register (asf controller?b1:d8:f0) offset address: f4h attribute: r/w default value: 00h size: 8 bits this register is a means for software to read the current sequence number that hardware is using in rmcp packets. software can also change the value. software should only write to this register while the global enable is off. bit description 7 software reset (frc_rst) ? r/w. this bit is used to reset the asf controller. it performs the equivalent of a hardware reset and re-read the eepr om. this bit self-clears immediately. software should wait for the eec_load bit to clear. 6 force eeprom reload (frc_eeld) ? r/w. force reload of eeprom without affect current monitoring state of the asf controller . this bit self-clears immediately. note: software registers in eeprom are not loaded by this action. software should disable the asf controller before issuing this command and wait for sta_load to clear before enabling again. 5 flush sos (frc_flush) ? r/w. this bit is used to flush any pending soses or history internal to the asf controller. this is necessary because t he status register only shows events that have happened as opposed to sos events sent. also, the hi story bits in the asf controller are not software visible. self-clears immediately. 4reserved 3 force apm power cycle (frc_acyc) ? r/w. this mode forces the asf controller to initiate a power cycle to the system. t he bit self-clears immediately. 2 force apm hard power down (frc_ahdn) ? r/w. this mode forces the asf controller to initiate a hard power down of the system i mmediately. the bit se lf-clears immediately. 1 clear asf polling history (frc_clrapol) ? r/w. writing a 1b to this bit position will clear the poll history associated with all asf polling. writing a 0b has no effec t. this bit self-clears immediately. 0 force apm reset (frc_arst) ? r/w. this mode forces the asf controller to initiate a hard reset of the system immediately. t he bit self-clears immediately. bit description 7:0 rmcp sequence number (rseq_val) ? r/w. this is the current sequence number of the rmcp packet being sent or the sequence number of the next rmcp packet to be sent. this value can be set by software. at reset, it defaults to 00h. if the sequence number is not ffh, the asf controller will automatical ly increment this number by one (or ro llover to 00h if incrementing from feh) after a successful rmcp packet transmission.
intel ? i/o controller hub 6 (ich6) family datasheet 319 lan controller registers (b1:d8:f0) 8.3.18 sp_mode?special modes register (asf controller?b1:d8:f0) offset address: f5h attribute: r/wc, ro default value: x0h size: 8 bits the register contains miscellaneous functions. 8.3.19 inpoll_tconf?inter-poll timer configuration register (asf controller?b1:d8:f0) offset address: f6h attribute: r/w default value: 10h size: 8 bits this register is used to load and hold the value (in increments of 5 ms) for the polling timer. this value determines how often the asf polling timer expires which determines the minimum idle time between sensor polls. bit description 7 smbus activity bit (spe_act) ? ro. 1 = asf controller is active with a smbus transacti on. this is an indicator to software that the asf controller is still processing commands on the smbus. 6 watchdog status (spe_wdg) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when a watchdog expiration occurs. 5 link loss status (spe_lnk) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when a link loss occurs (link is down for more than 5 seconds). 4:0 reserved bit description 7:0 inter-poll timer configuration (iptc_val) ? r/w. this field identifie s the time, in 5.24 ms units that the asf controller will wait between the end of the one asf poll alert message to start on the next. the value 00h is illegal and unsupported.
320 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.20 phist_clr?poll hi story clear register (asf controller?b1:d8:f0) offset address: f7h attribute: r/wc default value: 00h size: 8 bits this register is used to clear the history of the legacy poll operations. asf maintains history of the last poll data for each legacy poll operation to compare against the cu rrent poll to de tect changes. by setting the appropriate bit, the histor y for that legacy poll is cleared to 0s. 8.3.21 pmsk1?polling mask 1 register (asf controller?b1:d8:f0) offset address: f8h attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #1 data mask. bit description 7 clear polling descriptor 8 history (phc_poll8) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #8. writing a 0b has no effect. 6 clear polling descriptor 7 history (phc_poll7) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #7. writing a 0b has no effect. 5 clear polling descriptor 6 history (phc_poll6) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #6. writing a 0b has no effect. 4 clear polling descriptor 5 history (phc_poll5) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #5. writing a 0b has no effect. 3 clear polling descriptor 4 history (phc_poll4) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #4. writing a 0b has no effect. 2 clear polling descriptor 3 history (phc_poll3) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #3. writing a 0b has no effect. 1 clear polling descriptor 2 history (phc_poll2) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #2. writing a 0b has no effect. 0 clear polling descriptor 1 history (phc_poll1) ? r/wc. writing a 1b to this bit position will clear the poll history associ ated with polling descriptor #1. writing a 0b has no effect. bit description 7:0 polling mask for polling descriptor #1 (pol1_msk) ? r/w. this field is used to read and write the data mask for polling descriptor #1. software should only access this register when the asf controller is global disabled.
intel ? i/o controller hub 6 (ich6) family datasheet 321 lan controller registers (b1:d8:f0) 8.3.22 pmsk2?polling mask 2 register (asf controller?b1:d8:f0) offset address: f9h attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #2 data mask. 8.3.23 pmsk3?polling mask 3 register (asf controller?b1:d8:f0) offset address: fah attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #3 data mask. 8.3.24 pmsk4?polling mask 4 register (asf controller?b1:d8:f0) offset address: fbh attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #4 data mask. bit description 7:0 polling mask for polling descriptor #2 (pol2_msk) ? r/w. this field is used to read and write the data mask for polling descriptor #2. software should only access this register when the asf controller is global disabled. bit description 7:0 polling mask for polling descriptor #3 (pol3_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #3. soft ware should only access this register when the asf controller is global disabled. bit description 7:0 polling mask for polling descriptor #4 (pol4_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #4. soft ware should only access this register when the asf controller is global disabled.
322 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0) 8.3.25 pmsk5?polling mask 5 register (asf controller?b1:d8:f0) offset address: fch attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #5 data mask. 8.3.26 pmsk6?polling mask 6 register (asf controller?b1:d8:f0) offset address: fdh attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #6 data mask. 8.3.27 pmsk7?polling mask 7 register (asf controller?b1:d8:f0) offset address: feh attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #7 data mask. bit description 7:0 polling mask for polling descriptor #5 (pol5_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #5. so ftware should only access this register when the asf controller is global disabled. bit description 7:0 polling mask for polling descriptor #6 (pol6_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #6. so ftware should only access this register when the asf controller is global disabled. bit description 7:0 polling mask for polling descriptor #7 (pol7_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #7. so ftware should only access this register when the asf controller is global disabled.
intel ? i/o controller hub 6 (ich6) family datasheet 323 lan controller registers (b1:d8:f0) 8.3.28 pmsk8?polling mask 8 register (asf controller?b1:d8:f0) offset address: ffh attribute: r/w default value: xxh size: 8 bits this register provides software an interface for the polling #8 data mask. bit description 7:0 polling mask for polling descriptor #8 (pol8_msk) ? r/w. this register is used to read and write the data mask for polling descriptor #8. so ftware should only access this register when the asf controller is global disabled.
324 intel ? i/o controller hub 6 (i ch6) family datasheet lan controller registers (b1:d8:f0)
intel ? i/o controller hub 6 (ich6) family datasheet 325 pci-to-pci bridge registers (d30:f0) 9 pci-to-pci bridge registers (d30:f0) the ich6 pci bridge resides in pci device 30, function 0 on bus #0. this implements the buffering and control logic between pci and the backbone. the arbitration for the pci bus is handled by this pci device. 9.1 pci configuration registers (d30:f0) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). . table 9-1. pci bridge register addres s map (pci-pci?d30:f0) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 244eh (desktop) 2448h (ich6-m) ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h psts pci status 0010h r/wc, ro 08h rid revision identification see register description. ro 09-0bh cc class code 060401h ro 0dh pmlt primary master latency timer 00h ro 0eh headtyp header type 81h ro 18-1ah bnum bus number 000000h r/w, ro 1bh smlt secondary master latency timer 00h r/w, ro 1c-1dh iobase_limit i/o base and limit 0000h r/w, ro 1e?1fh secsts secondary status 0280h r/wc, ro 20?23h membase_limit memory base and limit 00000000h r/w, ro 24?27h pref_mem_base _limit prefetchable memory base and limit 00010001h r/w, ro 28?2bh pmbu32 prefetchable memory upper 32 bits 00000000h r/w 2c?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h r/w 34h capp capability list pointer 50h ro 3c-3dh intr interrupt information 0000h r/w, ro 3e?3fh bctrl bridge control 0000h r/wc, ro 40?41h spdh secondary pci device hiding 00h r/w, ro
326 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.1 vid? vendor identificati on register (pci-pci?d30:f0) offset address: 00?01h attribute: ro default value: 8086h size: 16 bits 9.1.2 did? device identification register (pci-pci?d30:f0) offset address: 02?03h attribute: ro default value: 2448h (mobile) size: 16 bits 244eh (desktop) 42h pdpr pci decode policy register 00h r/w 44-47h dtc delayed transaction control 00000000h r/w, ro 48-4b bts bridge proprietary status 00000000h r/wc, ro 4c-4f bpc bridge policy configuration 00000000h r/w ro 50?51h svcap subsystem vendor capability pointer 000dh ro 54-57 svid subsystem vendor ids 00000000 r/wo table 9-1. pci bridge register addres s map (pci-pci?d30:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit va lue assigned to intel. intel vid = 8086h. bit description 15:0 device id ? ro.this is a 16-bit value assigned to the pci bridge. mobile = 2448h (ich6-m) desktop = 244eh (ich6, ich6r)
intel ? i/o controller hub 6 (ich6) family datasheet 327 pci-to-pci bridge registers (d30:f0) 9.1.3 pcicmd?pci command (pci-pci?d30:f0) offset address: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? ro. hardwired to 0. the pci bridge has no interrupts to disable 9 fast back to back enable (fbe) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 8 serr# enable (serr_en) ? r/w. 0 = disable. 1 = enable the ich6 to generate an nmi (or smi# if nmi routed to smi#) when the d30:f0 sse bit (offset 06h, bit 14) is set. 7 wait cycle control (wcc) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 6 parity error response (per) ? r/w. 0 = the ich6 ignores parity errors on the pci bridge. 1 = the ich6 will set the sse bit (d30:f0, offset 06h, bit 14) when parity errors are detected on the pci bridge. 5 vga palette snoop (vps) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a . 4 memory write and invalidate enable (m we) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a 3 special cycle enable (sce) ? ro. hardwired to 0, per the pci express* base specification, revision 1.0a and the pci- to-pci bridge specification. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. allows the pci-to-pci bridge to accept cycles from pci. 1 memory space enable (mse) ? r/w. controls the response as a target for memory cycles targeting pci. 0 = disable 1 = enable 0 i/o space enable (iose) ? r/w. controls the response as a target for i/o cycles targeting pci. 0 = disable 1 = enable
328 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.4 psts?pci status re gister (pci-pci?d30:f0) offset address: 06 ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = indicates that the ich6 detected a parity error on the internal backbone. this bit gets set even if the parity error response bit (d30:f0:04 bit 6) is not set. 14 signaled system error (sse) ? r/wc. several internal and external sources of the bridge can cause serr#. the first clas s of errors is parity errors related to the backbone. the pci bridge captures generic data parity errors (errors it fi nds on the backbone) as well as errors returned on backbone cycles where the bridge was the master. if either of these two conditions is met, and the primary side of the bridge is enabl ed for parity error response, ser r# will be captured as shown below. as with the backbone, the pci bus captures the sa me sets of errors. the pci bridge captures generic data parity errors (errors it finds on pci) as well as errors returned on pci cycles where the bridge was the master. if either of these two c onditions is met, and the secondary side of the bridge is enabled for parity error response, serr# will be captured as shown below. the final class of errors is syste m bus errors. there are three status bits associated with system bus errors, each with a corresponding enable. the diagram capturing this is shown below. after checking for the three above classes of errors, an serr# is generated, and psts.sse logs the generation of serr#, if cmd.see (d30:f0 :04, bit 8) is set, as shown below.
intel ? i/o controller hub 6 (ich6) family datasheet 329 pci-to-pci bridge registers (d30:f0) 9.1.5 rid?revision identificati on register (pci-pci?d30:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 9.1.6 cc?class code register (pci-pci?d30:f0) offset address: 09-0bh attribute: ro default value: 060401h size: 32 bits 13 received master abort (rma) ? r/wc. 0 = no master abort received. 1 = set when the bridge receives a master abort status from the backbone. 12 received target abort (rta) ? r/wc. 0 = no target abort received. 1 = set when the bridge receives a target abort status from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no signaled target abort 1 = set when the bridge generates a completion pa cket with target abort status on the backbone. 10:9 reserved. 8 data parity error detected (dpd) ? r/wc. 0 = data parity error not detected. 1 = set when the bridge receives a completion pa cket from the backbone from a previous request, and detects a parity error, and cmd.pere is set (d30:f0:04 bit 6). 7:5 reserved. 4 capabilities list (clist) ? ro. hardwired to 1. capability list exist on the pci bridge. 3 interrupt status (is) ? ro. hardwired to 0. the pci bridge does not generate interrupts. 2:0 reserved 0 i/o space enable (iose) ? r/w. controls the response as a target for i/o cycles targeting pci. 0 = disable 0 = enable bit description bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 23:16 base class code (bcc) ? ro. hardwired to 06h. indicates this is a bridge device. 15:8 sub class code (scc) ? ro. hardwired to 04h. indicates this device is a pci-to-pci bridge. 7:0 programming interface (pi) ? ro. hardwired to 01h. indicates t he bridge is subtractive decode
330 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.7 pmlt?primary master latency timer register (pci-pci?d30:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 9.1.8 headtyp?header type register (pci-pci?d30:f0) offset address: 0eh attribute: ro default value: 81h size: 8 bits 9.1.9 bnum?bus number re gister (pci-pci?d30:f0) offset address: 18-1ah attribute: r/w, ro default value: 000000h size: 24 bits bit description 7:3 master latency timer count (mltc) ? ro. reserved per the pci express* base specification, revision 1.0a . 2:0 reserved bit description 7 multi-function device (mfd) ? ro. the value reported here depends upon the state of the ac ?97 function hide (fd) register (chipset configurati on registers:offset 3418h), per the following table: 6:0 header type (htype) ? ro. this 7-bit field identifie s the header layout of t he configuration space, which is a pci-to-pci bridge in this case. fd.aad fd.amd mfd 00 1 01 1 10 1 11 0 bit description 23:16 subordinate bus number (sbbn) ? r/w. indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. indicates the bus number of pci. 7:0 primary bus number (pbn) ? ro. hardwired to 00h for legacy software compatibility.
intel ? i/o controller hub 6 (ich6) family datasheet 331 pci-to-pci bridge registers (d30:f0) 9.1.10 smlt?secondary maste r latency timer register (pci-pci?d30:f0) offset address: 1bh attribute: r/w, ro default value: 00h size: 8 bits this timer controls the amount of time the ich6 pc i-to-pci bridge will burst data on its secondary interface. the counter starts counting down from the assertion of frame#. if the grant is removed, then the expiration of this counter will result in the de-assertion of frame#. if the grant has not been removed, then th e ich6 pci-to-pci bridge may continue ownership of the bus. 9.1.11 iobase_limit?i/o base and limit register (pci-pci?d30:f0) offset address: 1c-1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 7:3 master latency timer count (mltc) ? r/w. this 5-bit field indicates th e number of pci clocks, in 8-clock increments, that the ich6 remains as master of the bus. 2:0 reserved bit description 15:12 i/o limit address limit bits [15:12] ? r/w. i/o these base address bi ts corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to fffh. 11:8 ii/o limit address capability (iolc) ? ro. this field indicates that t he bridge does not support 32- bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. these i/o base address bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? ro. this fi eld indicates that the bridge does not support 32- bit i/o addressing.
332 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.12 secsts?secondary statu s register (pci-pci?d30:f0) offset address: 1e ? 1fh attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. 0 = parity error not detected. 1 = intel ? ich6 pci bridge detected an address or data parity error on the pci bus 14 received system error (r se) ? r/wc. 0 = serr# assertion not received 1 = serr# assertion is received on pci. 13 received master abort (rma) ? r/wc. 0 = no master abort. 1 = this bit is set whenever the bridge is acting as an initiator on the pci bus and the cycle is master-aborted. for (g)mch/ich6 interface packe ts that have completion required, this must also cause a target abort to be returned and sets psts.sta. (d30:f0:06 bit 11) 12 received target abort (rta) ? r/wc. 0 = no target abort. 1 = this bit is set whenever the br idge is acting as an initiator on pci and a cycle is target-aborted on pci. for (g)mch/ich6 interface packets that have completion required, this event must also cause a target abort to be returned, and sets psts.sta. (d30:f0:06 bit 11). 11 signaled target abort (sta) ? r/wc. 0 = no target abort. 1 = this bit is set when the bridge is acting as a target on the pci bus and signals a target abort. 10:9 devsel# timing (devt) ? ro. 01h = medium decode timing. 8 data parity error detected (dpd) ? r/wc. 0 = conditions described below not met. 1 = the ich6 sets this bit when all of the following three conditions are met: ? the bridge is the initiator on pci. ? perr# is detected asserted or a parity error is detected internally ? bctrl.pere (d30:f0:3e bit 0) is set. 7 fast back to back capable (fbc) ? ro. hardwired to 1 to indicate that the pci to pci target logic is capable of receiving fast back-to-back cycles. 6reserved 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. this bridge is 33 mhz capable only. 4:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 333 pci-to-pci bridge registers (d30:f0) 9.1.13 membase_limit?memory base and limit register (pci-pci?d30:f0) offset address: 20?23h attribute: r/w, ro default value: 00000000h size: 32 bits this register defines the base and limit, alig ned to a 1-mb boundary, of the non-prefetchable memory area of the bridge. accesses th at are within the ranges specified in this register will be sent to pci if cmd.mse is set. accesses from pci that are outside the ra nges specified will be accepted by the bridge if cmd.bme is set. 9.1.14 pref_mem_base_limit? prefetchable memory base and limit register (pci-pci?d30:f0) offset address: 24?27h attribute: r/w, ro default value: 00010001h size: 32-bit defines the base and limit, aligned to a 1-mb boundary, of the prefetchable memory area of the bridge. accesses that are within the ranges specified in this re gister will be sent to pci if cmd.mse is set. accesses from pc i that are outside the ranges specified will be accepted by the bridge if cmd.bme is set. bit description 31-20 memory limit (ml) ? r/w. these bits are compared wi th bits 31:20 of the incoming address to determine the upper 1-mb aligned value (exclusiv e) of the range. the incoming address must be less than this value. 19-16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb aligned value (inclusive ) of the range. the incoming address must be greater than or equal to this value. 3:0 reserved bit description 31-20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb alig ned value (exclusive) of the range. the incoming address must be less than this value. 19-16 64-bit indicator (i64l) ? ro. this field indicates support for 64-bit addressing. 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb al igned value (inclusive) of the range. the incoming address must be greater than or equal to this value. 3:0 64-bit indicator (i64b) ? ro. this field indicates support for 64-bit addressing.
334 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.15 pmbu32?prefetchable me mory base upper 32 bits register (pci-pci?d30:f0) offset address: 28?2bh attribute: r/w default value: 00000000h size: 32 bits 9.1.16 pmlu32?prefetchable me mory limit upper 32 bits register (pci-pci?d30:f0) offset address: 2c?2fh attribute: r/w default value: 00000000h size: 32 bits 9.1.17 capp?capability list poin ter register (pci-pci?d30:f0) offset address: 34h attribute: ro default value: 50h size: 8 bits 9.1.18 intr?interrupt informat ion register (p ci-pci?d30:f0) offset address: 3c ? 3dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. this field pr ovides the upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. this field provides the upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. this field indicates that the poi nter for the first entry in the capabilities list is at 50h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. the pci bridge does not assert an interrupt. 7:0 interrupt line (iline) ? r/w. software written value to indi cate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. since the bridge does not generate an interrupt, bios should program this val ue to ffh as per the pci bridge specification.
intel ? i/o controller hub 6 (ich6) family datasheet 335 pci-to-pci bridge registers (d30:f0) 9.1.19 bctrl?bridge control register (pci-pci?d30:f0) offset address: 3e ? 3fh attribute: r/wc, ro default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dte ) ? r/w. this bit controls the generation of serr# on the primary interface in response to the dts bit being set: 0 = do not generate serr# on a secondary timer discard 1 = generate serr# in response to a secondary timer discard 10 discard timer status (dts) ? r/wc. this bit is set to 1 wh en the secondary discard timer (see the sdt bit below) expires for a delayed transaction in the hard state. 9 secondary discard timer (sdt) ? r/w. this bit sets the maxi mum number of pci clock cycles that the intel ? ich6 waits for an initiator on pci to repeat a delayed transaction request. the counter starts once the delayed transaction data is has been re turned by the system and is in a buffer in the ich6 pci bridge. if the master has not repeated t he transaction at least once before the counter expires, the ich6 pci bridge discards the transaction from its queue. 0 = the pci master timeout value is between 2 15 and 2 16 pci clocks 1 = the pci master timeout value is between 2 10 and 2 11 pci clocks 8 primary discard timer (pdt ) ? r/w. this bit is r/w for software compatibility only. 7 fast back to back enable (fbe) ? ro. hardwired to 0. the pci logic will not generate fast back-to- back cycles on the pci bus. 6 secondary bus reset (sbr) ? r/w. this bit controls pcirst# assertion on pci. 0 = bridge de-asserts pcirst# 1 = bridge asserts pcirst#. when pcirst# is asse rted, the delayed transaction buffers, posting buffers, and the pci bus are initialized back to reset conditions. the rest of the part and the configuration registers are not affected. note: when pcirst# is asserted by setting this bit, the pci bus will be in reset. pci transactions will not be able to complete while this bit is set. when cleared, the bus will exit the reset state and transactions can be completed. 5 master abort mode (mam ) ? r/w. this bit controls the ic h6 pci bridge?s behavior when a master abort occurs: master abort on (g)mch/ich6 interconnect (dmi): 0 = bridge asserts trdy# on pci. it drives all 1s for reads, and discards data on writes. 1 = bridge returns a target abort on pci. master abort pci (non-locked cycles): 0 = normal completion status will be returned on the (g)mch/ich6 interconnect. 1 = target abort completion status will be returned on the (g)mch/ich6 interconnect. note: all locked reads will return a completer abor t completion status on the (g)mch/ich6 interconnect. 4 vga 16-bit decode (v16d) ? r/w. enables the ich6 pci bri dge to provide 16-bits decoding of vga i/o address precluding the decode of vga alia s addresses every 1 kb. this bit requires the vgae bit in this register be set.
336 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.20 spdh?secondary pci device hiding register (pci-pci?d30:f0) offset address: 40?41h attribute: r/w, ro default value: 00h size: 16 bits this register allows software to hide the pci devices, either plugged into slots or on the motherboard. 3 vga enable (vgae) ? r/w. when set to a 1, the ich6 pci bridge forwards the following transactions to pci regardless of the value of the i/o base and limit registers. the transactions are qualified by cmd.mse (d30:f0:04 bit 1) and cmd.iose (d30:f0:04 bit 0) being set. ? memory addresses: 000a0000h-000bffffh ? i/o addresses: 3b0h-3bbh and 3c0h-3dfh. for the i/o addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (i.e., aliased). the same holds true from secondary accesses to the primary interface in reverse. that is, when the bit is 0, memory and i/o addresses on the se condary interface between the above ranges will be claimed. 2 isa enable (ie) ? r/w. this bit only applies to i/o address es that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o space. if this bit is set, the ich6 pci bridge will block any forwarding from primary to seconda ry of i/o transactions addr essing the last 768 bytes in each 1-kb block (offsets 100h to 3ffh). 1 serr# enable (see) ? r/w. this bit controls the forwarding of secondary interface serr# assertions on the primary interface. when set, the pci bridge will forward serr# pin. ? serr# is asserted on the secondary interface. ? this bit is set. ? cmd.see (d30:f0:04 bit 8) is set. 0 parity error response enable (pere) ? r/w. 0 = disable 1 = the ich6 pci bridge is enabled for parity error reporting based on parity errors on the pci bus. bit description bit description 15:8 reserved 7 hide device 7 (hd7) ? r/w, ro. same as bit 0 of this regist er, except for device 7 (ad[23]) 6 hide device 6 (hd6) ? r/w, ro. same as bit 0 of this register, except for device 6 (ad[22]) 5 hide device 5 (hd5) ? r/w, ro. same as bit 0 of this register, except for device 5 (ad[21]) 4 hide device 4 (hd4) ? r/w, ro. same as bit 0 of this register, except for device 4 (ad[20]) 3 hide device 3 (hd3) ? r/w, ro. same as bit 0 of this register, except for device 3 (ad[19]) 2 hide device 2 (hd2) ? r/w, ro. same as bit 0 of this register, except for device 2 (ad[18]) 1 hide device 1 (hd1) ? r/w, ro. same as bit 0 of this regist er, except for device 1 (ad[17]) 0 hide device 0 (hd0) ? r/w, ro. 0 = the pci configuration cycles for this slot are not affected. 1 = intel ? ich6 hides device 0 on the pci bus. this is done by masking the idsel (keeping it low) for configuration cycles to that device. since the device will not see its idsel go active, it will not respond to pci configuration cycles and the pr ocessor will think the device is not present. ad[16] is used as idsel for device 0.
intel ? i/o controller hub 6 (ich6) family datasheet 337 pci-to-pci bridge registers (d30:f0) 9.1.21 pdpr?pci deco de policy register (pci-pci?d30:f0) offset address: 42h attribute: r/w default value: 00h size: 8 bits bit description 7:1 reserved 0 subtractive decode policy (sdp) ? r/w. 0 = the pci bridge always forwards memory and i/o cycles that are not claimed by any other device on the backbone (primary interface) to the pci bus (secondary interface). 1 = the pci bridge will not claim and forward memo ry or i/o cycles at all unless the corresponding space enable bit is set in the command register. note: the boot bios destination selection str ap can force the bios accesses to pci.
338 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.22 dtc?delayed transaction control register (pci-pci?d30:f0) offset address: 44 ? 47h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31 discard delayed transactions (ddt) ? r/w. 0 = logged delayed transactions are kept. 1 = the ich6 pci bridge will discard any delay ed transactions it has logged. this includes transactions in the pending queue, and any transac tions in the active queue, whether in the hard or soft dt state. the prefetchers will be disabled and return to an idle state. note: if a transaction is running on pci at the time this bit is set, that transacti on will continue until either the pci master disconnects (by de-ass erting frame#) or the pci bridge disconnects (by asserting stop#). this bi t is cleared by the pci bri dge when the delayed transaction queues are empty and have returned to an idle stat e. software sets this bit and polls for its completion 30 block delayed transactions (bdt) ? r/w. 0 = delayed transactions accepted 1 = the ich6 pci bridge will not accept incomi ng transactions which will result in delayed transactions. it will blindly retr y these cycles by asserting stop #. all postable cycles (memory writes) will still be accepted. 29: 8 reserved 7: 6 maximum delayed transactions (mdt) ? r/w. controls the maximum number of delayed transactions that the ich6 pci bridge will run. encodings are: 00 =) 2 active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) reserved 5 reserved 4 auto flush after disconnect enable (afade) ? r/w. 0 = the pci bridge will retain any fetched data until required to discard by producer/consumer rules. 1 = the pci bridge will flush any prefetched data after either the pci master (by de-asserting frame#) or the pci bridge (by asserti ng stop#) disconnects the pci transfer. 3 never prefetch (np) ? r/w. 0 = prefetch enabled 1 = the ich6 will only fetch a single dw and wi ll not enable prefetching, regardless of the command being an memory read (mr), memory read line (mrl), or memory read multiple (mrm). 2 memory read multiple prefetch disable (mrmpd) ? r/w. 0 = mrm commands will fetch multiple cache li nes as defined by the prefetch algorithm. 1 = memory read multiple (mrm) commands will fe tch only up to a single, 64-byte aligned cache line. 1 memory read line prefetch disable (mrlpd) ? r/w. 0 = mrl commands will fetch multiple cache li nes as defined by the prefetch algorithm. 1 = memory read line (mrl) commands will fetch only up to a single, 64-byte aligned cache line. 0 memory read prefetch disable (mrpd) ? r/w. 0 = mr commands will fetch up to a 64-byte aligned cache line. 1 = memory read (mr) commands will fetch only a single dw.
intel ? i/o controller hub 6 (ich6) family datasheet 339 pci-to-pci bridge registers (d30:f0) 9.1.23 bps?bridge propri etary status register (pci-pci?d30:f0) offset address: 48 ? 4bh attribute: r/wc, ro default value: 00000000h size: 32 bits bit description 31:17 reserved 16 perr# assertion detected (pad) ? r/wc. this bit is set by hardware whenever the perr# pin is asserted on the rising edge of pc i clock. this includes cases in which the chipset is the agent driving perr#. it remains asserted until cleared by software writing a 1 to this location. when enabled by the perr#-to-serr# enable bi t (in the bridge policy configuration register), a 1 in this bit can generate an internal serr# and be a source for the nmi logic. this bit can be used by software to deter mine the source of a system problem. 15:7 reserved 6:4 number of pending transactions (npt) ? ro. this read-only indicator tells debug software how many transactions are in the pending queue. possible values are: 000 = no pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110 - 111 = reserved note: this field is not valid if dtc.mdt (offset 44h:bits 7:6) is any value other than ?00?. 3:2 reserved 1:0 number of active transactions (nat) ? ro. this read-onl y indicator tells debug software how many transactions are in the ac tive queue. possible values are: 00 = no active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = reserved
340 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0) 9.1.24 bpc?bridge policy configuration register (pci-pci?d30:f0) offset address: 4c ? 4fh attribute: r/w, ro default value: 00000000h size: 32 bits 9.1.25 svcap?subsystem ve ndor capability register (pci-pci?d30:f0) offset address: 50 ? 51h attribute: ro default value: 000dh size: 16 bits bit description 31:7 reserved 6 perr#-to-serr# enable (pse) ? r/w. when this bit is set, a 1 in the perr# assertion status bit (in the bridge proprietary status register) will re sult in an internal serr# assertion on the primary side of the bridge (if also enabled by the serr# enable bit in the primary command register). serr# is a source of nmi. 5 secondary discard timer testmode (sdtt) ? r/w. 0 = the secondary discard timer expiration will be defined in bctrl.sdt (d30:f0:3e, bit 9) 1 = the secondary discard timer will expire after 128 pci clocks. 4:3 reserved 2reserved 1 reserved 0 received target abort serr# enable (rtae) ? r/w. when set, the pci bridge will report serr# when psts.rta (d30:f0:06 bit 12) or ssts.rta (d30:f0:1e bit 12) are set, and cmd.see (d30:f0:04 bit 8) is set. bit description 15:8 next capability (next) ? ro. value of 00h indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates this is a pci bridge subsystem vendor capability.
intel ? i/o controller hub 6 (ich6) family datasheet 341 pci-to-pci bridge registers (d30:f0) 9.1.26 svid?subsystem vendor ids register (pci-pci?d30:f0) offset address: 54 ? 57h attribute: r/wo default value: 00000000h size: 32 bits bit description 31:16 subsystem identifier (sid) ? r/wo. this field indicates the s ubsystem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. this field indicates the manufacturer of the subsystem. this field is write onc e and is locked down until a bridge reset occurs (not the pci bus reset).
342 intel ? i/o controller hub 6 (i ch6) family datasheet pci-to-pci bridge registers (d30:f0)
intel ? i/o controller hub 6 (ich6) family datasheet 343 lpc interface bridge registers (d31:f0) 10 lpc interface bridge registers (d31:f0) the lpc bridge function of the ich6 resides in pci device 31:function 0. this function contains many other functional units, such as dma and interrupt controllers, timers, power management, system management, gpio, rtc, and lpc configuration registers. registers and functions associat ed with other functional units (ehci, uhci, ide, etc.) are described in their respective sections. 10.1 pci configuration registers (lpc i/f?d31:f0) note: address locations that are not shown should be treated as reserved. . table 10-1. lpc interface pci register addr ess map (lpc i/f?d31:f0) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 2641h ich6-m 2640h ich6/ich6r ro 04?05h pcicmd pci command 0007h r/w, ro 06?07h pcists pci status 0200h r/wc, ro 08h rid revision identification see register description. ro 09h pi programming interface 00h ro 0ah scc sub class code 01h ro 0bh bcc base class code 06h ro 0dh plt primary latency timer 00h ro 0eh headtyp header type 80h ro 2c?2fh ss sub system identifiers 00000000h r/wo 40?43h pmbase acpi base address 00000001h r/w, ro 44h acpi_cntl acpi control 00h r/w 48?4bh gpiobase gpio base address 00000001h r/w, ro 4c gc gpio control 00h r/w 60?63h pirq[ n ]_rout pirq[a?d] routing control 80h r/w 64h sirq_cntl serial irq control 10h r/w, ro 68?6bh pirq[ n ]_rout pirq[e?h] routing control 80h r/w 80h lpc_i/o_dec i/o decode ranges 0000h r/w 82?83h lpc_en lpc i/f enables 0000h r/w
344 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.1 vid?vendor identification register (lpc i/f?d31:f0) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 10.1.2 did?device identificatio n register (lpc i/f?d31:f0) offset address: 02 ? 03h attribute: ro default value: ich6/ich6r: 2640h size: 16-bit ich6-m: 2641h lockable: no power well: core 84?85h gen1_dec lpc i/f generic decode range 1 0000h r/w 88?89h gen2_dec lpc i/f generic decode range 2 0000h r/w a0?cfh power management (see section 10.8.1 ) d0?d3h fwh_sel1 firmware hub select 1 00112233h r/w, ro d4?d5h fwh_sel2 firmware hub select 2 4567h r/w d8?d9h fwh_dec_en1 firmware hub decode enable 1 ffcfh r/w, ro dch bios_cntl bios control 00h r/wlo, r/w f0-f3h rcba root complex base address 00000000h r/w table 10-1. lpc interface pci register address map (lpc i/f?d31:f0) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assi gned to the ich6 lpc bridge.
intel ? i/o controller hub 6 (ich6) family datasheet 345 lpc interface bridge registers (d31:f0) 10.1.3 pcicmd?pci command register (lpc i/f?d31:f0) offset address: 04 ? 05h attribute: r/w, ro default value: 0007h size: 16-bit lockable: no power well: core bit description 15:10 reserved 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. the lpc bridge generates serr# if this bit is set. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response enable (pere) ? r/w. 0 = no action is taken when detecting a parity error. 1 = enables the ich6 lpc bridge to respond to parity errors detected on backbone interface. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. bus masters cannot be disabled. 1 memory space enable (mse) ? ro. memo ry space cannot be disabled on lpc. 0 i/o space enable (iose) ? ro. i/o space cannot be disabled on lpc.
346 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.4 pcists?pci status register (lpc i/f?d31:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0200h size: 16-bit lockable: no power well: core note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? r/wc. set when the lpc bridge detects a parity error on the internal backbone. set even if the pcic md.pere bit (d31:f0:04, bit 6) is 0 0 = parity error not detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. set when the lpc bridge signals a system error to the internal serr# logic. 13 master abort status (rma) ? r/wc. 0 = unsupported request status not received. 1 = the bridge received a completion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = completion with completion abo rt received from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = target abort not generated on the backbone. 1 = lpc bridge generated a completion packet with target abort status on the backbone. 10:9 devsel# timing status (dev_sts) ? ro. 01 = medium timing. 8 data parity error detected (dped) ? r/wc. 0 = all conditions listed below not met. 1 = set when all three of the following conditions are met: ? lpc bridge receives a completion packet fr om the backbone from a previous request, ? parity error has been detected (d31:f0:06, bit 15) ? pcicmd.pere bit (d31:f0:04, bit 6) is set. 7 fast back to back capable (fbc): reserved ? bit has no meaning on the internal backbone. 6 reserved. 5 66 mhz capable (66mhz_cap) ? reserved ? bit has no meaning on internal backbone. 4 capabilities list (clist) ? ro. no ca pability list exis t on the lpc bridge. 3 interrupt status (is) ? ro. the lpc bridge does not generate interrupts. 2:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 347 lpc interface bridge registers (d31:f0) 10.1.5 rid?revision identific ation register (l pc i/f?d31:f0) offset address: 08h attribute: ro default value: see bit description size: 8 bits 10.1.6 pi?programming interfac e register (lpc i/f?d31:f0) offset address: 09h attribute: ro default value: 00h size: 8 bits 10.1.7 scc?sub class code register (lpc i/f?d31:f0) offset address: 0ah attribute: ro default value: 01h size: 8 bits 10.1.8 bcc?base class code register (lpc i/f?d31:f0) offset address: 0bh attribute: ro default value: 06h size: 8 bits bit description 7:0 revision id (rid) ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. bit description 7:0 sub class code ? ro. 8-bit value that indicates t he category of bridge for the lpc bridge. 01h = pci-to-isa bridge. bit description 7:0 base class code ? ro. this field is an 8-bit value that indicates the type of device for the lpc bridge. 06h = bridge device.
348 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.9 plt?primary latency time r register (lpc i/f?d31:f0) offset address: 0dh attribute: ro default value: 00h size: 8 bits 10.1.10 headtyp?header type register (lpc i/f?d31:f0) offset address: 0eh attribute: ro default value: 80h size: 8 bits 10.1.11 ss?sub system identifi ers register (lpc i/f?d31:f0) offset address: 2c ? 2fh attribute: r/wo default value: 00000000h size: 32 bits this register is initialized to logic 0 by the assertion of pltrst#. this register can be written only once after pltrst# de-assertion. bit description 7:3 master latency count (mlc) ? reserved. 2:0 reserved. bit description 7 multi-function device ? ro. this bit is 1 to indi cate a multi-function device. 6:0 header type ? ro. this 7-bit field identifies the header layout of the configuration space. bit description 31:16 subsystem id (ssid) ? r/wo. this field is written by bi os. no hardware action taken on this value. 15:0 subsystem vendor id (ssvid) ? r/wo. this field is written by bi os. no hardware action taken on this value.
intel ? i/o controller hub 6 (ich6) family datasheet 349 lpc interface bridge registers (d31:f0) 10.1.12 pmbase?acpi base addre ss register (lpc i/f?d31:f0) offset address: 40 ? 43h attribute: r/w, ro default value: 00000001h size: 32 bit lockable: no usage: acpi, legacy power well: core sets base address for acpi i/o registers, gpio registers and tc o i/o registers. these registers can be mapped anywhere in the 64-k i/o space on 128-byte boundaries. 10.1.13 acpi_cntl?acpi control register (lpc i/f ? d31:f0) offset address: 44h attribute: r/w default value: 00h size: 8 bit lockable: no usage: acpi, legacy power well: core bit description 31:16 reserved 15:7 base address ? r/w. this field provides 128 bytes of i/o space for acpi, gpio, and tco logic. this is placed on a 128-byte boundary. 6:1 reserved 0 resource type indicator (rte) ? ro. ha rdwired to 1 to indicate i/o space. bit description 7 acpi enable (acpi_en) ? r/w. 0 = disable. 1 = decode of the i/o range pointed to by the acpi base register is enabled, and the acpi power management function is enabled. note that the apm power management ranges (b2/b3h) are always enabled and are not affected by this bit. 6:3 reserved 2:0 sci irq select (sci_irq_sel) ? r/w. this field specifies on wh ich irq the sci will internally appear. if not using the apic, the sci must be routed to irq9?11, and that interrupt is not sharable with the serirq stream, but is shareable with other pci interrupts. if using the apic, the sci can also be mapped to irq20?23, and can be shared with other interrupts. note: when the tco interrupt is mapped to apic interrupts 9, 10 or 11, the signal is in fact active high. when the tco interrupt is mapped to irq 20, 21, 22, or 23, the signal is active low and can be shared with pci interrupts that may be mapped to those same signals (irqs). bits sci map 000b irq9 001b irq10 010b irq11 011b reserved 100b irq20 (only available if apic enabled) 101b irq21 (only available if apic enabled) 110b irq22 (only available if apic enabled) 111b irq23 (only available if apic enabled)
350 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.14 gpiobase?gpio base address register (lpc i/f ? d31:f0) offset address: 48?4bh attribute: r/w, ro default value: 00000001h size: 32 bit 10.1.15 gc?gpio control regi ster (lpc i/f ? d31:f0) offset address: 4ch attribute: r/w default value: 00h size: 8 bit bit description 31:16 reserved. always 0. 15:6 base address (ba) ? r/w. this field provides the 64 bytes of i/o space for gpio. 5:1 reserved. always 0. 0 ro. hardwired to 1 to indicate i/o space. bit description 7:5 reserved. 4 gpio enable (en) ? r/w. this bit enables/disables dec ode of the i/o range pointed to by the gpio base address register (d31: f0:48h) and enables the gpio function. 0 = disable. 1 = enable. 3:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 351 lpc interface bridge registers (d31:f0) 10.1.16 pirq[n]_rout?pirq[a,b,c ,d] routing control register (lpc i/f?d31:f0) offset address: pirqa ? 60h, pirqb ? 61h, attribute: r/w pirqc ? 62h, pirqd ? 63h default value: 80h size: 8 bit lockable: no power well: core bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15
352 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.17 sirq_cntl?serial irq control register (lpc i/f?d31:f0) offset address: 64h attribute: r/w, ro default value: 10h size: 8 bit lockable: no power well: core bit description 7 serial irq enable (sirqen) ? r/w. 0 = the buffer is input only and internally serirq will be a 1. 1 = serial irqs will be rec ognized. the serirq pin will be configured as serirq. 6 serial irq mode select (sirqmd) ? r/w. 0 = the serial irq machine will be in quiet mode. 1 = the serial irq machine will be in continuous mode. note: for systems using quiet mode, this bit should be set to 1 (continuous mode) for at least one frame after coming out of reset before switchi ng back to quiet mode. failure to do so will result in the ich6 not recognizing serirq interrupts. 5:2 serial irq frame size (sirqsz) ? ro. this field is fixed to indi cate the size of the serirq frame as 21 frames. 1:0 start frame pulse width (sfpw) ? r/w. this is the number of pci clocks that the serirq pin will be driven low by the serial irq ma chine to signal a start frame. in continuous mode, the ich6 will drive the start frame for the number of clocks specif ied. in quiet mode, the ich6 will drive the start frame for the number of clocks specified minus one , as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = reserved
intel ? i/o controller hub 6 (ich6) family datasheet 353 lpc interface bridge registers (d31:f0) 10.1.18 pirq[n]_rout?pirq[e,f,g ,h] routing control register (lpc i/f?d31:f0) offset address: pirqe ? 68h, pirqf ? 69h, attribute: r/w pirqg ? 6ah, pirqh ? 6bh default value: 80h size: 8 bit lockable: no power well: core bit description 7 interrupt routing enable (irqen) ? r/w. 0 = the corresponding pirq is routed to one of the isa-compatible interrupts specified in bits[3:0]. 1 = the pirq is not routed to the 8259. note: bios must program this bit to 0 during post for any of the pirqs that are being used. the value of this bit may subsequently be changed by the os when setting up for i/o apic interrupt delivery mode. 6:4 reserved 3:0 irq routing ? r/w. (isa compatible.) value irq value irq 0000b reserved 1000b reserved 0001b reserved 1001b irq9 0010b reserved 1010b irq10 0011b irq3 1011b irq11 0100b irq4 1100b irq12 0101b irq5 1101b reserved 0110b irq6 1110b irq14 0111b irq7 1111b irq15
354 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.19 lpc_i/o_dec?i/o decode ranges register (lpc i/f?d31:f0) offset address: 80h attribute: r/w default value: 0000h size: 16 bit bit description 15:13 reserved 12 fdd decode range ? r/w. this bit determines which range to decode for the fdd port 0 = 3f0h ? 3f5h, 3f7h (primary) 1 = 370h ? 375h, 377h (secondary) 11:10 reserved 9:8 lpt decode range ? r/w. this field determines which range to decode for the lpt port. 00 = 378h ? 37fh and 778h ? 77fh 01 = 278h ? 27fh (port 279h is read only) and 678h ? 67fh 10 = 3bch ?3beh and 7bch ? 7beh 11 = reserved 7 reserved 6:4 comb decode range ? r/w. this field determines whic h range to decode for the comb port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3) 3 reserved 2:0 coma decode range ? r/w. this field determines whic h range to decode for the coma port. 000 = 3f8h ? 3ffh (com1) 001 = 2f8h ? 2ffh (com2) 010 = 220h ? 227h 011 = 228h ? 22fh 100 = 238h ? 23fh 101 = 2e8h ? 2efh (com4) 110 = 338h ? 33fh 111 = 3e8h ? 3efh (com3)
intel ? i/o controller hub 6 (ich6) family datasheet 355 lpc interface bridge registers (d31:f0) 10.1.20 lpc_en?lpc i/f enable s register (lpc i/f?d31:f0) offset address: 82h ? 83h attribute: r/w default value: 0000h size: 16 bit power well: core bit description 15:14 reserved 13 cnf2_lpc_en ? r/w. microcontroller enable # 2. 0 = disable. 1 = enables the decoding of the i/o locations 4eh and 4fh to the lpc interface. this range is used for a microcontroller. 12 cnf1_lpc_en ? r/w. super i/o enable. 0 = disable. 1 = enables the decoding of the i/o locations 2eh and 2fh to the lpc interface. this range is used for super i/o devices. 11 mc_lpc_en ? r/w. microcontroller enable # 1. 0 = disable. 1 = enables the decoding of the i/o locations 62h and 66h to the lpc interface. this range is used for a microcontroller. 10 kbc_lpc_en ? r/w. keyboard enable. 0 = disable. 1 = enables the decoding of the i/o locations 60h and 64h to the lpc interface. this range is used for a microcontroller. 9 gameh_lpc_en ? r/w. high gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 2 08h to 20fh to the lpc interface. this range is used for a gameport. 8 gamel_lpc_en ? r/w. low gameport enable 0 = disable. 1 = enables the decoding of the i/o locations 2 00h to 207h to the lpc interface. this range is used for a gameport. 7:4 reserved 3 fdd_lpc_en ? r/w. floppy drive enable 0 = disable. 1 = enables the decoding of the fdd range to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 12). 2 lpt_lpc_en ? r/w. parallel port enable 0 = disable. 1 = enables the decoding of the lptrange to the lpc interface. this range is selected in the lpc_fdd/lpt decode range register (d31:f0:80h, bit 9:8). 1 comb_lpc_en ? r/w. com port b enable 0 = disable. 1 = enables the decoding of the comb range to t he lpc interface. this range is selected in the lpc_com decode range register (d31:f0:80h, bits 6:4). 0 coma_lpc_en ? r/w. com port a enable 0 = disable. 1 = enables the decoding of the coma range to t he lpc interface. this range is selected in the lpc_com decode range register (d31:f0:80h, bits 3:2).
356 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.21 gen1_dec?lpc i/f generic decode range 1 register (lpc i/f?d31:f0) offset address: 84h ? 85h attribute: r/w default value: 0000h size: 16 bit power well: core 10.1.22 gen2_dec?lpc i/f generic decode range 2 register (lpc i/f?d31:f0) offset address: 88h ? 89h attribute: r/w default value: 0000h size: 16 bit power well: core bit description 15:7 generic i/o decode range 1 base address (gen1_base) ? r/w. this address is aligned on a 128-byte boundary, and must have address lines 31:16 as 0. note: this generic decode is for i/o addresses only, not memory addresses. the size of this range is 128 bytes. 6:1 reserved 0 generic decode range 1 enable (gen1_en) ? r/w. 0 = disable. 1 = enable the gen1 i/o range to be forwarded to the lpc i/f bit description 15:4 generic i/o decode range 2 base address (gen2_base) ? r/w. this address is aligned on a 16-byte, 32-byte, or 64-byte boundary, and must have address lines 31:16 as 0. notes: 1. this generic decode is for i/o addresses only, not memory addresses. the size of this range is 16, 32, or 64 bytes. 2. size of decode range is determined by d31:f0:adh:bits 5:4. 3:1 reserved. read as 0. 0 generic i/o decode range 2 enable (gen2_en) ? r/w. 0 = disable. 1 = accesses to the gen2 i/o range will be forwarded to the lpc i/f
intel ? i/o controller hub 6 (ich6) family datasheet 357 lpc interface bridge registers (d31:f0) 10.1.23 fwh_sel1?firmware hub select 1 register (lpc i/f?d31:f0) offset address: d0h ? d3h attribute: r/w, ro default value: 00112233h size: 32 bits bit description 31:28 fwh_f8_idsel ? ro. idsel for two 512-kb firmware hub memory ranges and one 128-kb memory range. this field is fixed at 0000. th e idsel programmed in this field addresses the following memory ranges: fff8 0000h ? ffff ffffh ffb8 0000h ? ffbf ffffh 000e 0000h ? 000f ffffh 27:24 fwh_f0_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: fff0 0000h ? fff7 ffffh ffb0 0000h ? ffb7 ffffh 23:20 fwh_e8_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffe8 0000h ? ffef ffffh ffa8 0000h ? ffaf ffffh 19:16 fwh_e0_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffe0 0000h ? ffe7 ffffh ffa0 0000h ? ffa7 ffffh 15:12 fwh_d8_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffd8 0000h ? ffdf ffffh ff98 0000h ? ff9f ffffh 11:8 fwh_d0_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffd0 0000h ? ffd7 ffffh ff90 0000h ? ff97 ffffh 7:4 fwh_c8_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffc8 0000h ? ffcf ffffh ff88 0000h ? ff8f ffffh 3:0 fwh_c0_idsel ? r/w. idsel for two 512-kb firmware hub memory ranges. the idsel programmed in this field addresse s the following memory ranges: ffc0 0000h ? ffc7 ffffh ff80 0000h ? ff87 ffffh
358 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.24 fwh_sel2?firmware hub select 2 register (lpc i/f?d31:f0) offset address: d4h ? d5h attribute: r/w default value: 4567h size: 16 bits bit description 15:12 fwh_70_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 11:8 fwh_60_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 7:4 fwh_50_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 3:0 fwh_40_idsel ? r/w. idsel for two, 1-m firmware hub memory ranges. the idsel programmed in this field addresses the following memory ranges: ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh
intel ? i/o controller hub 6 (ich6) family datasheet 359 lpc interface bridge registers (d31:f0) 10.1.25 fwh_dec_en1?firmware hu b decode enable register (lpc i/f?d31:f0) offset address: d8h ? d9h attribute: r/w, ro default value: ffcfh size: 16 bits bit description 15 fwh_f8_en ? ro. this bit enables decoding two 512-kb firmware hub memory ranges, and one 128-kb memory range. 0 = disable 1 = enable the following ranges for the firmware hub fff80000h ? ffffffffh ffb80000h ? ffbfffffh 14 fwh_f0_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: fff00000h ? fff7ffffh ffb00000h ? ffb7ffffh 13 fwh_e8_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: ffe80000h ? ffeffffh ffa80000h ? ffafffffh 12 fwh_e0_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub: ffe00000h ? ffe7ffffh ffa00000h ? ffa7ffffh 11 fwh_d8_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffd80000h ? ffdfffffh ff980000h ? ff9fffffh 10 fwh_d0_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffd00000h ? ffd7ffffh ff900000h ? ff97ffffh 9 fwh_c8_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffc80000h ? ffcfffffh ff880000h ? ff8fffffh 8 fwh_c0_en ? r/w. this bit enables decoding tw o 512-kb firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ffc00000h ? ffc7ffffh ff800000h ? ff87ffffh 7 fwh_legacy_f_en ? r/w. this enables the decoding of the legacy 128-k range at f0000h ? fffffh. 0 = disable. 1 = enable the following legacy ranges for the firmware hub f0000h ? fffffh
360 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.1.26 bios_cntl?bio s control register (lpc i/f?d31:f0) offset address: dch attribute: r/wlo, r/w default value: 00h size: 8 bit lockable: no power well: core 6 fwh_legacy_e_en ? r/w. this bit enables the decoding of the legacy 128-k range at e0000h ? effffh. 0 = disable. 1 = enable the following legacy ranges for the firmware hub e0000h ? effffh 5:4 reserved 3 fwh_70_en ? r/w. this bit enables decoding tw o 1-m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff70 0000h ? ff7f ffffh ff30 0000h ? ff3f ffffh 2 fwh_60_en ? r/w. this bit enables decoding tw o 1-m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff60 0000h ? ff6f ffffh ff20 0000h ? ff2f ffffh 1 fwh_50_en ? r/w. this bit enables decoding two 1-m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff50 0000h ? ff5f ffffh ff10 0000h ? ff1f ffffh 0 fwh_40_en ? r/w. this bit enables decoding tw o 1-m firmware hub memory ranges. 0 = disable. 1 = enable the following ranges for the firmware hub ff40 0000h ? ff4f ffffh ff00 0000h ? ff0f ffffh bit description bit description 7:2 reserved 1 bios lock enable (ble) ? r/wlo. 0 = setting the bioswe will not cause smis. 1 = enables setting the bioswe bit to cause smis . once set, this bit can only be cleared by a pltrst# 0 bios write enable (bioswe) ? r/w. 0 = only read cycles result in firmware hub i/f cycles. 1 = access to the bios space is enabled for bot h read and write cycles. when this bit is written from a 0 to a 1 and bios lock enable (ble) is also set, an smi# is generated. this ensures that only smi code can update bios.
intel ? i/o controller hub 6 (ich6) family datasheet 361 lpc interface bridge registers (d31:f0) 10.1.27 rcba?root comple x base address register (lpc i/f?d31:f0) offset address: f0h attribute: r/w default value: 00000000h size: 32 bit 10.2 dma i/o registers (lpc i/f?d31:f0) bit description 31:14 base address (ba) ? r/w. this field provides the base addre ss for the root complex register block decode range. this address is aligned on a 16-kb boundary. 13:1 reserved 0 enable (en) ? r/w. when set, this bit enables the range s pecified in ba to be claimed as the root complex register block. table 10-2. dma registers (sheet 1 of 2) port alias register name default type 00h 10h channel 0 dma base & current address undefined r/w 01h 11h channel 0 dma base & current count undefined r/w 02h 12h channel 1 dma base & current address undefined r/w 03h 13h channel 1 dma base & current count undefined r/w 04h 14h channel 2 dma base & current address undefined r/w 05h 15h channel 2 dma base & current count undefined r/w 06h 16h channel 3 dma base & current address undefined r/w 07h 17h channel 3 dma base & current count undefined r/w 08h 18h channel 0?3 dma command undefined wo channel 0?3 dma status undefined ro 0ah 1ah channel 0?3 dma write single mask 000001xxb wo 0bh 1bh channel 0?3 dma channel mode 000000xxb wo 0ch 1ch channel 0?3 dma clear byte pointer undefined wo 0dh 1dh channel 0?3 dma master clear undefined wo 0eh 1eh channel 0?3 dma clear mask undefined wo 0fh 1fh channel 0?3 dma write all mask 0fh r/w 80h 90h reserved page undefined r/w 81h 91h channel 2 dma memory low page undefined r/w 82h ? channel 3 dma memory low page undefined r/w 83h 93h channel 1 dma memory low page undefined r/w 84h?86h 94h?96h reserved pages undefined r/w 87h 97h channel 0 dma memory low page undefined r/w 88h 98h reserved page undefined r/w
362 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 89h 99h channel 6 dma memory low page undefined r/w 8ah 9ah channel 7 dma memory low page undefined r/w 8bh 9bh channel 5 dma memory low page undefined r/w 8ch?8eh 9ch?9eh reserved page undefined r/w 8fh 9fh refresh low page undefined r/w c0h c1h channel 4 dma base & current address undefined r/w c2h c3h channel 4 dma base & current count undefined r/w c4h c5h channel 5 dma base & current address undefined r/w c6h c7h channel 5 dma base & current count undefined r/w c8h c9h channel 6 dma base & current address undefined r/w cah cbh channel 6 dma base & current count undefined r/w cch cdh channel 7 dma base & current address undefined r/w ceh cfh channel 7 dma base & current count undefined r/w d0h d1h channel 4?7 dma command undefined wo channel 4?7 dma status undefined ro d4h d5h channel 4?7 dma write single mask 000001xxb wo d6h d7h channel 4?7 dma channel mode 000000xxb wo d8h d9h channel 4?7 dma clear byte pointer undefined wo dah dbh channel 4?7 dma master clear undefined wo dch ddh channel 4?7 dma clear mask undefined wo deh dfh channel 4?7 dma write all mask 0fh r/w table 10-2. dma registers (sheet 2 of 2) port alias register name default type
intel ? i/o controller hub 6 (ich6) family datasheet 363 lpc interface bridge registers (d31:f0) 10.2.1 dmabase_ca?dma b ase and current address registers (lpc i/f?d31:f0) i/o address: ch. #0 = 00h; ch. #1 = 02h attribute: r/w ch. #2 = 04h; ch. #3 = 06h size: 16 bit (per channel), ch. #5 = c4h ch. #6 = c8h but accessed in two 8-bit ch. #7 = cch; quantities default value: undef lockable: no power well: core 10.2.2 dmabase_cc?dma base and current count registers (lpc i/f?d31:f0) i/o address: ch. #0 = 01h; ch. #1 = 03h attribute: r/w ch. #2 = 05h; ch. #3 = 07h size: 16-bit (per channel), ch. #5 = c6h; ch. #6 = cah but accessed in two 8-bit ch. #7 = ceh; quantities default value: undefined lockable: no power well: core bit description 15:0 base and current address ? r/w. this register determines the ad dress for the transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base address register and copied to the current address register. on reads, the value is returned from the current address register. the address increments/decrements in the current address register after each transfer, depending on the mode of the transfer. if the channel is in auto- initialize mode, the current address register will be reloaded from the base address register after a terminal count is generated. for transfers to/from a 16-bit slave (channel?s 5-7), the address is shifted left one bit location. bit 15 will be shifted into bit 16. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing an address register, the byte po inter flip/flop should be cleared to ensure that the low byte is accessed first bit description 15:0 base and current count ? r/w. this register determines the number of transfers to be performed. the address specified points to two separate registers. on writes, the value is stored in the base count register and copied to the current count register. on reads, the value is returned from the current count register. the actual number of transfers is one more than the number programmed in the base count register (i.e., programming a count of 4h results in 5 transfers). the count is decrements in the current count register after each transfer. when the value in the register rolls from 0 to ffffh, a terminal count is generated. if the channel is in auto- initialize mode, the curr ent count register will be reloaded from the base count register after a terminal count is generated. for transfers to/from an 8-bit slave (channels 0?3), th e count register indicates the number of bytes to be transferred. for transfers to/from a 16-bit sl ave (channels 5?7), the count register indicates the number of words to be transferred. the register is accessed in 8 bit quantities. the byte is pointed to by the current byte pointer flip/flop. before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first.
364 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.2.3 dmamem_lp?dma memory low page registers (lpc i/f?d31:f0) i/o address: ch. #0 = 87h; ch. #1 = 83h ch. #2 = 81h; ch. #3 = 82h ch. #5 = 8bh; ch. #6 = 89h ch. #7 = 8ah; attribute: r/w default value: undefined size: 8-bit lockable: no power well: core 10.2.4 dmacmd?dma command register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: wo default value: undefined size: 8-bit lockable: no power well: core bit description 7:0 dma low page (isa address bits [23:16]) ? r/w. this r egister works in conjunction with the dma controller's current address register to define the complete 24-bit address for the dma channel. this register remains static throughout the dma tr ansfer. bit 16 of this register is ignored when in 16 bit i/o count by words mode as it is replaced by the bit 15 shifted out from the current address register. bit description 7:5 reserved. must be 0. 4 dma group arbitration priority ? wo. each channel group is indi vidually assigned ei ther fixed or rotating arbitration priority. at part reset, each group is initialized in fixed priority. 0 = fixed priority to the channel group 1 = rotating priority to the group. 3 reserved. must be 0. 2 dma channel group enable ? wo. both channel groups are enabled following part reset. 0 = enable the dma channel group. 1 = disable. disabling channel group 4?7 also di sables channel group 0?3, which is cascaded through channel 4. 1:0 reserved. must be 0.
intel ? i/o controller hub 6 (ich6) family datasheet 365 lpc interface bridge registers (d31:f0) 10.2.5 dmasta?dma status register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 08h; ch. #4 ? 7 = d0h attribute: ro default value: undefined size: 8-bit lockable: no power well: core 10.2.6 dma_wrsmsk?dma write single mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ah; ch. #4 ? 7 = d4h attribute: wo default value: 0000 01xx size: 8-bit lockable: no power well: core bit description 7:4 channel request status ? ro. when a valid dma reques t is pending for a channel, the corresponding bit is set to 1. when a dma reques t is not pending for a particular channel, the corresponding bit is set to 0. the source of the dreq may be hardware or a software request. note that channel 4 is the cascade channel, so the reques t status of channel 4 is a logical or of the request status for channels 0 through 3. 4 = channel 0 5 = channel 1 (5) 6 = channel 2 (6) 7 = channel 3 (7) 3:0 channel terminal count status ? ro. when a channel reaches terminal count (tc), its status bit is set to 1. if tc has not been reached, the status bit is set to 0. channel 4 is programmed for cascade, so the tc bit response for channel 4 is irrelevant: 0 = channel 0 1 = channel 1 (5) 2 = channel 2 (6) 3 = channel 3 (7) bit description 7:3 reserved. must be 0. 2 channel mask select ? wo. 0 = enable dreq for the selected channel. the channel is selected through bits [1:0]. therefore, only one channel can be mask ed / unmasked at a time. 1 = disable dreq for the selected channel. 1:0 dma channel select ? wo. these bits select the dma channel mode register to program. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7)
366 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.2.7 dmach_mode?dma channel mode register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0bh; ch. #4 ? 7 = d6h attribute: wo default value: 0000 00xx size: 8-bit lockable: no power well: core 10.2.8 dma clear byte pointer register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0ch; ch. #4 ? 7 = d8h attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core bit description 7:6 dma transfer mode ? wo. each dma channel can be programmed in one of four different modes: 00 = demand mode 01 = single mode 10 = reserved 11 = cascade mode 5 address increment/decrement select ? wo. this bit controls address increment/decrement during dma transfers. 0 = address increment. (default after part reset or master clear) 1 = address decrement. 4 autoinitialize enable ? wo. 0 = autoinitialize feature is disabled and dma transfers terminate on a terminal count. a part reset or master clear disabl es autoinitialization. 1 = dma restores the base address and count r egisters to the current registers following a terminal count (tc). 3:2 dma transfer type ? wo. these bits represent the directi on of the dma transfer. when the channel is programmed for cascade mode, (bits[ 7:6] = 11) the transfer type is irrelevant. 00 = verify ? no i/o or memory strobes generated 01 = write ? data transferred from the i/o devices to memory 10 = read ? data transferred from memory to the i/o device 11 = illegal 1:0 dma channel select ? wo. these bits select the dma channel m ode register that will be written by bits [7:2]. 00 = channel 0 (4) 01 = channel 1 (5) 10 = channel 2 (6) 11 = channel 3 (7) bit description 7:0 clear byte pointer ? wo. no specific pattern. command enabled with a write to the i/o port address. writing to this register initializes the by te pointer flip/flop to a known state. it clears the internal latch used to address the upper or lo wer byte of the 16-bit address and word count registers. the latch is also cleared by part re set and by the master clear command. this command precedes the first access to a 16-bit dma controller register. the first access to a 16-bit register will then access the significant byte, and the second acce ss automatically accesse s the most significant byte.
intel ? i/o controller hub 6 (ich6) family datasheet 367 lpc interface bridge registers (d31:f0) 10.2.9 dma master clear re gister (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0dh; ch. #4 ? 7 = dah attribute: wo default value: xxxx xxxx size: 8-bit 10.2.10 dma_clmsk?dma clear ma sk register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0eh; ch. #4 ? 7 = dch attribute: wo default value: xxxx xxxx size: 8-bit lockable: no power well: core 10.2.11 dma_wrmsk?dma write all mask register (lpc i/f?d31:f0) i/o address: ch. #0 ? 3 = 0fh; ch. #4 ? 7 = deh attribute: r/w default value: 0000 1111 size: 8-bit lockable: no power well: core bit description 7:0 master clear ? wo. no specific pattern. enabled with a wr ite to the port. this has the same effect as the hardware reset. the command, status, request, and byte pointer flip/flop registers are cleared and the mask register is set. bit description 7:0 clear mask register ? wo. no specific pattern. command enabled with a write to the port. bit description 7:4 reserved. must be 0. 3:0 channel mask bits ? r/w. this register permits all four channels to be simultaneously enabled/ disabled instead of enabling/disabl ing each channel indi vidually, as is the case with the mask register ? write single mask bit. in addition, this register has a read path to allow the status of the channel mask bits to be read. a channel's mask bit is automatically set to 1 when the current byte/ word count register reaches terminal count ( unless the channel is in auto-initialization mode). setting the bit(s) to a 1 disables the corresponding dreq(s). setting the bit(s) to a 0 enables the corresponding dreq(s). bits [3:0] are set to 1 upon part reset or master clear. when read, bits [3:0] indicate the dma channel [3:0] ([7:4]) mask status. bit 0 = channel 0 (4) 1 = masked, 0 = not masked bit 1 = channel 1 (5) 1 = masked, 0 = not masked bit 2 = channel 2 (6) 1 = masked, 0 = not masked bit 3 = channel 3 (7) 1 = masked, 0 = not masked note: disabling channel 4 also di sables channels 0?3 due to the cascade of channel?s 0 ? 3 through channel 4.
368 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.3 timer i/o registers (lpc i/f?d31:f0) port aliases register name default value type 40h 50h counter 0 interval time status byte format 0xxxxxxxb ro counter 0 counter access port undefined r/w 41h 51h counter 1 interval time status byte format 0xxxxxxxb ro counter 1 counter access port undefined r/w 42h 52h counter 2 interval time status byte format 0xxxxxxxb ro counter 2 counter access port undefined r/w 43h 53h timer control word undefined wo timer control word register xxxxxxx0b wo counter latch command x0h wo
intel ? i/o controller hub 6 (ich6) family datasheet 369 lpc interface bridge registers (d31:f0) 10.3.1 tcw?timer control word register (lpc i/f?d31:f0) i/o address: 43h attribute: wo default value: all bits undefined size: 8 bits this register is prog rammed prior to any counter being accessed to specify counter modes. following part reset, the control words for each regi ster are undefined and each counter output is 0. each timer must be programmed to bring it into a known state. there are two special commands that can be issued to the counters through this register, the read back command and the counter latch command. wh en these commands are chosen, several bits within this register are redefined. th ese register formats are described below: bit description 7:6 counter select ? wo. the counter selection bits select the counter the control word acts upon as shown below. the read back command is selected when bits[7:6] are both 1. 00 = counter 0 select 01 = counter 1 select 10 = counter 2 select 11 = read back command 5:4 read/write select ? wo. these bits are the read/write control bits. the actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 counter mode selection ? wo. these bits select one of six possible modes of operation for the selected counter. 0 binary/bcd countdown select ? wo. 0 = binary countdown is used. the la rgest possible bina ry count is 2 16 1 = binary coded decimal (bcd) count is us ed. the largest possible bcd count is 10 4 bit value mode 000b mode 0 out signal on end of count (=0) 001b mode 1 hardware retriggerable one-shot x10b mode 2 rate generator (divide by n counter) x11b mode 3 square wave output 100b mode 4 software triggered strobe 101b mode 5 hardware triggered strobe
370 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) rdbk_cmd?read back command (lpc i/f?d31:f0) the read back command is used to determine the count value, programmed mode, and current states of the out pin and null count flag of the se lected counter or counters. status and/or count may be latched in any or all of the counters by selecting the counter during the register write. the count and status remain latched until read, and fu rther latch commands are ignored until the count is read. both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. if both are latched, the first read operation from that counter returns the latched status. the next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. subsequent reads return an unlatched count. ltch_cmd?counter latch command (lpc i/f?d31:f0) the counter latch command latches the current count value. this command is used to insure that the count read from the counter is accurate. the co unt value is then read from each counter's count register through the counter ports access ports regi ster (40h for counter 0, 41h for counter 1, and 42h for counter 2). the count must be read accordin g to the programmed format, i.e., if the counter is programmed for two byte counts, two bytes must be read. the two bytes do not have to be read one right after the other (read, write, or programm ing operations for other counters may be inserted between the reads). if a counter is latched once and then latched again before the count is read, the second counter latch command is ignored. bit description 7:6 read back command. must be 11 to select the read back command 5 latch count of selected counters. 0 = current count value of the se lected counters will be latched 1 = current count will not be latched 4 latch status of selected counters. 0 = status of the selected counters will be latched 1 = status will not be latched 3 counter 2 select. 1 = counter 2 count and/or status will be latched 2 counter 1 select. 1 = counter 1 count and/or status will be latched 1 counter 0 select. 1 = counter 0 count and/or status will be latched. 0 reserved. must be 0. bit description 7:6 counter selection. these bits select the counter for latchi ng. if ?11? is written, then the write is interpreted as a read back command. 00 = counter 0 01 = counter 1 10 = counter 2 5:4 counter latch command. 00 = selects the counter latch command. 3:0 reserved. must be 0.
intel ? i/o controller hub 6 (ich6) family datasheet 371 lpc interface bridge registers (d31:f0) 10.3.2 sbyte_fmt?interval time r status byte format register (lpc i/f?d31:f0) i/o address: counter 0 = 40h, counter 1 = 41h, attribute: ro counter 2 = 42h size: 8 bits per counter default value: bits[6:0 ] undefined, bit 7=0 each counter's status byte can be read following a read back comma nd. if latch status is chosen (bit 4=0, read back comm and) as a read back option for a given counter, the next read from the counter's counter access ports regi ster (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. the status byte returns the following: bit description 7 counter out pin state ? ro. 0 = out pin of the counter is also a 0 1 = out pin of the counter is also a 1 6 count register status ? ro. this bit indicates when the last count written to the count register (cr) has been loaded into the counting element (ce). the exact time this happens depends on the counter mode, but until the count is loaded into the counting element (ce), the count value will be incorrect. 0 = count has been transferred from cr to ce and is available for reading. 1 = null count. count has not been transferred from cr to ce and is not yet available for reading. 5:4 read/write selection status ? ro. these bits reflect the read/write selection made through bits[5:4] of the control register. the binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = counter latch command 01 = read/write least significant byte (lsb) 10 = read/write most significant byte (msb) 11 = read/write lsb then msb 3:1 mode selection status ? ro. these bits return the count er mode programming. the binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = mode 0 ? out signal on end of count (=0) 001 = mode 1 ? hardware retriggerable one-shot x10 = mode 2 ? rate generator (divide by n counter) x11 = mode 3 ? square wave output 100 = mode 4 ? software triggered strobe 101 = mode 5 ? hardware triggered strobe 0 countdown type status ? ro. this bit reflects the current countdown type. 0 = binary countdown 1 = binary coded decimal (bcd) countdown.
372 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.3.3 counter access ports register (lpc i/f?d31:f0) i/o address: counter 0 ? 40h, counter 1 ? 41h, attribute: r/w counter 2 ? 42h default value: all bits undefined size: 8 bit 10.4 8259 interrupt controller (pic) registers (lpc i/f?d31:f0) 10.4.1 interrupt controller i/o map (lpc i/f?d31:f0) the interrupt controller registers are located at 20h and 21h for the master controller (irq 0 ? 7), and at a0h and a1h for the slave controller (irq 8 ? 13). these registers have multiple functions, depending upon the data written to them. table 10-3 shows the different register possibilities for each address. note: refer to note addressing active-low interrupt sources in 8259 interrupt controllers section ( chapter 5.9 ). bit description 7:0 counter port ? r/w. each counter port address is used to program the 16-bit count register. the order of programming, either lsb only, msb only, or lsb then msb, is defined with the interval counter control register at port 43h. the counter port is also used to read the current count from the count register, and return the status of the counter programming following a read back command. table 10-3. pic regist ers (lpc i/f?d31:f0) port aliases register name default value type 20h 24h, 28h, 2ch, 30h, 34h, 38h, 3ch master pic icw1 init. cmd word 1 undefined wo master pic ocw2 op ctrl word 2 001xxxxxb wo master pic ocw3 op ctrl word 3 x01xxx10b wo 21h 25h, 29h, 2dh, 31h, 35h, 39h, 3dh master pic icw2 init. cmd word 2 undefined wo master pic icw3 init. cmd word 3 undefined wo master pic icw4 init. cmd word 4 01h wo master pic ocw1 op ctrl word 1 00h r/w a0h a4h, a8h, ach, b0h, b4h, b8h, bch slave pic icw1 init. cmd word 1 undefined wo slave pic ocw2 op ctrl word 2 001xxxxxb wo slave pic ocw3 op ctrl word 3 x01xxx10b wo a1h a5h, a9h, adh, b1h, b5h, b9h, bdh slave pic icw2 init. cmd word 2 undefined wo slave pic icw3 init. cmd word 3 undefined wo slave pic icw4 init. cmd word 4 01h wo slave pic ocw1 op ctrl word 1 00h r/w 4d0h ? master pic edge/level triggered 00h r/w 4d1h ? slave pic edge/level triggered 00h r/w
intel ? i/o controller hub 6 (ich6) family datasheet 373 lpc interface bridge registers (d31:f0) 10.4.2 icw1?initialization command word 1 register (lpc i/f?d31:f0) offset address: master controller ? 20h attribute: wo slave controller ? a0h size: 8 bit /controller default value: all bits undefined a write to initialization command word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. the interrupt mask register is cleared. 2. irq7 input is assigned priority 7. 3. the slave mode address is set to 7. 4. special mask mode is cleared and status read is set to irr. once this write occurs, the controller expects writes to icw2, icw3, and icw4 to complete the initialization sequence. bit description 7:5 icw/ocw select ? wo. these bits are mcs-85 specific, and not needed. 000 = should be programmed to ?000? 4 icw/ocw select ? wo. 1 = this bit must be a 1 to select icw1 and enable the icw2, icw3, and icw4 sequence. 3 edge/level bank select (ltim) ? wo. disabled. replaced by the edge/level triggered control registers (elcr, d31:f0:4d0h, d31:f0:4d1h). 2 adi ? wo. 0 = ignored for the ich6. should be programmed to 0. 1 single or cascade (sngl) ? wo. 0 = must be programmed to a 0 to indicate two controllers operating in cascade mode. 0 icw4 write required (ic4) ? wo. 1 = this bit must be programmed to a 1 to indicate that icw4 needs to be programmed.
374 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.4.3 icw2?initialization command word 2 register (lpc i/f?d31:f0) offset address: master controller ? 21h attribute: wo slave controller ? a1h size: 8 bit /controller default value: all bits undefined icw2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. the value programmed for bits[7:3 ] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each irq on the controller. typical isa icw2 values are 08h fo r the master controller and 70h for the slave controller. 10.4.4 icw3?master controlle r initialization command word 3 register (lpc i/f?d31:f0) offset address: 21h attribute: wo default value: all bits undefined size: 8 bits bit description 7:3 interrupt vector base address ? wo. bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 interrupt request level ? wo. when writing icw2, these bits should all be 0. during an interrupt acknowledge cycle, these bits are pr ogrammed by the interrupt controller with the interrupt to be serviced. this is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second inta# cycle. the code is a three bit binary code: code master interrupt slave interrupt 000b irq0 irq8 001b irq1 irq9 010b irq2 irq10 011b irq3 irq11 100b irq4 irq12 101b irq5 irq13 110b irq6 irq14 111b irq7 irq15 bit description 7:3 0 = these bits must be programmed to 0. 2 cascaded interrupt controller irq connection ? wo. this bit indicates that the slave controller is cascaded on irq2. when irq8#?irq15 is asserted, it goes through the slave controller?s priority resolver. the slave controller?s intr output onto irq2. irq2 then goes through the master controller?s priority solver. if it wins, the intr si gnal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = this bit must always be programmed to a 1. 1:0 0 = these bits must be programmed to 0.
intel ? i/o controller hub 6 (ich6) family datasheet 375 lpc interface bridge registers (d31:f0) 10.4.5 icw3?slave controlle r initialization command word 3 register (lpc i/f?d31:f0) offset address: a1h attribute: wo default value: all bits undefined size: 8 bits 10.4.6 icw4?initialization command word 4 register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: wo slave controller ? 0a1h size: 8 bits default value: 01h bit description 7:3 0 = these bits must be programmed to 0. 2:0 slave identification code ? wo. these bits are compared agai nst the slave identification code broadcast by the master controller from the traili ng edge of the first internal inta# pulse to the trailing edge of the second internal inta# pulse. these bits must be programmed to 02h to match the code broadcast by the master controller. when 02h is broadcast by the ma ster controller during the inta# sequence, the slave controller assume s responsibility for br oadcasting the interrupt vector. bit description 7:5 0 = these bits must be programmed to 0. 4 special fully nested mode (sfnm) ? wo. 0 = should normally be disabled by writing a 0 to this bit. 1 = special fully nested mode is programmed. 3 buffered mode (buf) ? wo. 0 = must be programmed to 0 for the ich6. this is non-buffered mode. 2 master/slave in buffered mode ? wo. not used. 0 = should always be programmed to 0. 1 automatic end of interrupt (aeoi) ? wo. 0 = this bit should normally be programmed to 0. this is the normal end of interrupt. 1 = automatic end of interrupt (aeoi) mode is programmed. 0 microprocessor mode ? wo. 1 = must be programmed to 1 to indicate that the controller is operating in an intel architecture-based system.
376 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.4.7 ocw1?operational control word 1 (interrupt mask) register (lpc i/f?d31:f0) offset address: master controller ? 021h attribute: r/w slave controller ? 0a1h size: 8 bits default value: 00h 10.4.8 ocw2?operational control word 2 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[4:0]=undefined, bit[7:5]=001 following a part reset or icw initialization, th e controller enters the fully nested mode of operation. non-specific eoi without rotation is the default. both rotation mode and specific eoi mode are disabled following initialization. bit description 7:0 interrupt request mask ? r/w. when a 1 is written to any bi t in this register, the corresponding irq line is masked. when a 0 is writ ten to any bit in this register , the corresponding irq mask bit is cleared, and interrupt requests will again be accepted by the controller. mask ing irq2 on the master controller will also mask the interrupt requests from the slave controller. bit description 7:5 rotate and eoi codes (r, sl, eoi) ? wo. these three bits control the rotate and end of interrupt modes and combinations of the two. 000 = rotate in auto eoi mode (clear) 001 = non-specific eoi command 010 = no operation 011 = *specific eoi command 100 = rotate in auto eoi mode (set) 101 = rotate on non-specific eoi command 110 = *set priority command 111 = *rotate on specific eoi command *l0 ? l2 are used 4:3 ocw2 select ? wo. when selecting ocw2, bits 4:3 = ?00? 2:0 interrupt level select (l2, l1, l0) ? wo. l2, l1, and l0 determine the interrupt level acted upon when the sl bit is active. a simple binary code, outlined below, selects the channel for the command to act upon. when the sl bit is inactive, these bits do not have a defined function; programming l2, l1 and l0 to 0 is sufficient in this case. code interrupt level code interrupt level 000b irq0/8 000b irq4/12 001b irq1/9 001b irq5/13 010b irq2/10 010b irq6/14 011b irq3/11 011b irq7/15
intel ? i/o controller hub 6 (ich6) family datasheet 377 lpc interface bridge registers (d31:f0) 10.4.9 ocw3?operational control word 3 register (lpc i/f?d31:f0) offset address: master controller ? 020h attribute: wo slave controller ? 0a0h size: 8 bits default value: bit[6,0]= 0, bit[7,4: 2]=undefined, bit[5,1]=1 bit description 7 reserved. must be 0. 6 special mask mode (smm) ? wo. 1 = the special mask mode can be used by an interr upt service routine to dynamically alter the system priority structure while the routine is executing, through select ive enabling/disabling of the other channel's mask bits. bit 5, the esmm bi t, must be set for this bit to have any meaning. 5 enable special mask mode (esmm) ? wo. 0 = disable. the smm bit becomes a ?don't care?. 1 = enable the smm bit to set or reset the special mask mode. 4:3 ocw3 select ? wo. when selecting ocw3, bits 4:3 = 01 2 poll mode command ? wo. 0 = disable. poll command is not issued. 1 = enable. the next i/o read to the interrupt c ontroller is treated as an interrupt acknowledge cycle. an encoded byte is driven onto the dat a bus, representing the highest priority level requesting service. 1:0 register read command ? wo. these bits provide control for reading the in-service register (isr) and the interrupt request register (irr). when bit 1=0, bit 0 will not affect the register read selection. when bit 1=1, bit 0 selects the register status returned following an ocw3 read. if bit 0=0, the irr will be read. if bit 0=1, the isr will be read. following icw initialization, the default ocw3 port address read will be ?read irr?. to retain the cu rrent selection (read isr or read irr), always write a 0 to bit 1 when programming this regist er. the selected register can be read repeatedly without reprogramming ocw3. to select a new stat us register, ocw3 must be reprogrammed prior to attempting the read. 00 = no action 01 = no action 10 = read irq register 11 = read is register
378 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.4.10 elcr1?master controller edge/level triggered register (lpc i/f?d31:f0) offset address: 4d0h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high level. the cascade channel, irq2, the heart beat timer (irq0), and the keyboard controller (irq1), cannot be put into level mode. bit description 7 irq7 ecl ? r/w. 0 = edge. 1 = level. 6 irq6 ecl ? r/w. 0 = edge. 1 = level. 5 irq5 ecl ? r/w. 0 = edge. 1 = level. 4 irq4 ecl ? r/w. 0 = edge. 1 = level. 3 irq3 ecl ? r/w. 0 = edge. 1 = level. 2:0 reserved. must be 0.
intel ? i/o controller hub 6 (ich6) family datasheet 379 lpc interface bridge registers (d31:f0) 10.4.11 elcr2?slave controller edge/level triggered register (lpc i/f?d31:f0) offset address: 4d1h attribute: r/w default value: 00h size: 8 bits in edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. in level mode (bit[x] = 1), the interrupt is recognized by a high le vel. the real time clock, irq8#, and the floating point error interrupt, irq13, cannot be programmed for level mode. bit description 7 irq15 ecl ? r/w. 0 = edge 1 = level 6 irq14 ecl ? r/w. 0 = edge 1 = level 5 reserved. must be 0. 4 irq12 ecl ? r/w. 0 = edge 1 = level 3 irq11 ecl ? r/w. 0 = edge 1 = level 2 irq10 ecl ? r/w. 0 = edge 1 = level 1 irq9 ecl ? r/w. 0 = edge 1 = level 0 reserved. must be 0.
380 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.5 advanced programmable interrupt controller (apic)(d31:f0) 10.5.1 apic register map (lpc i/f?d31:f0) the apic is accessed via an indir ect addressing scheme. two registers are visible by software for manipulation of most of the apic registers. th ese registers are mapped into memory space. the registers are shown in table 10-4 . table 10-5 lists the registers which can be accessed with in the apic via the index register. when accessing these registers, accesses must be done one dword at a time. for example, software should never access byte 2 from the data register before accessing bytes 0 and 1. the hardware will not attempt to recover from a bad programming model in this case. 10.5.2 ind?index regi ster (lpc i/f?d31:f0) memory address fec0_0000h attribute: r/w default value: 00h size: 8 bits the index register will select which apic indirect register to be manipulated by software. the selector values for the indi rect registers are listed in table 10-5 . software will program this register to select the desired apic internal register . table 10-4. apic direct registers (lpc i/f?d31:f0) address mnemonic register name size type fec0_0000h ind index 8 bits r/w fec0_0010h dat data 32 bits r/w feco_0040h eoir eoi 32 bits wo table 10-5. apic indirect registers (lpc i/f?d31:f0) index mnemonic register name size type 00 id identification 32 bits r/w 01 ver version 32 bits ro 02?0f ? reserved ? ro 10?11 redir_tbl0 redirection table 0 64 bits r/w, ro 12?13 redir_tbl1 redirection table 1 64 bits r/w, ro ... ... ... ... ... 3e?3f redir_tbl23 redirection table 23 64 bits r/w, ro 40?ff ? reserved ? ro bit description 7:0 apic index ? r/w. this is an 8-bit pointer into the i/o apic register table.
intel ? i/o controller hub 6 (ich6) family datasheet 381 lpc interface bridge registers (d31:f0) 10.5.3 dat?data regis ter (lpc i/f?d31:f0) memory address fec0_0010h attribute: r/w default value: 00000000h size: 32 bits this is a 32-bit register specifying the data to be read or written to the register pointed to by the index register. this register can only be accessed in dword quantities. 10.5.4 eoir?eoi regist er (lpc i/f?d31:f0) memory address fec0_0040h attribute: wo default value: n/a size: 32 bits the eoi register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. when a write is issued to this register, the i/o apic will check the lower 8 bits written to this register, and compare it with the vector field for each entry in th e i/o redirection table. when a match is found, the remote_irr bit (index offset 10 h, bit 14) for that i/o redirection entry will be cleared. note: if multiple i/o redirection entries, for any reas on, assign the same vector for more than one interrupt input, each of those entries will have th e remote_irr bit reset to 0. the interrupt which was prematurely reset will not be lost because if its input remained active when the remote_irr bit is cleared, the interrupt will be reissued and serviced at a later time. note: only bits 7:0 are actually used. bits 31:8 are ignored by the ich6. note: to provide for future expansion, the processor should always write a value of 0 to bits 31:8. bit description 7:0 apic data ? r/w. this is a 32-bit register for the data to be read or written to the apic indirect register ( figure 10-5 ) pointed to by the index register (memory address fec0_0000h). bit description 31:8 reserved. to provide for future expansion, the processor should always write a value of 0 to bits 31:8. 7:0 redirection entry clear ? wo. when a write is issued to this register, the i/o apic will check this field, and compare it with the vector field for eac h entry in the i/o redirection table. when a match is found, the remote_irr bit for that i/o redirection entry will be cleared.
382 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.5.5 id?identification register (lpc i/f?d31:f0) index offset: 00h attribute: r/w default value: 00000000h size: 32 bits the apic id serves as a physical name of the apic. the apic bus arbitration id for the apic is derived from its i/o apic id. this regi ster is reset to 0 on power-up reset. 10.5.6 ver?version regi ster (lpc i/f?d31:f0) index offset: 01h attribute: ro default value: 00170020h size: 32 bits each i/o apic contains a hardwired version regist er that identifies differ ent implementation of apic and their versions. the maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this apic. bit description 31:28 reserved 27:24 apic id ? r/w. software must program this value before using the apic. 23:16 reserved 15 scratchpad bit. 14:0 reserved bit description 31:24 reserved 23:16 maximum redirection entries ? ro. this is the entry number (0 being the lowest entry) of the highest entry in the redirection table. it is equal to the number of interrupt input pins minus one and is in the range 0 through 239. in the ich6 this field is hardwired to 17h to indicate 24 interrupts. 15 prq ? ro. this bit indicate that the ioxapic does not implement the pin assertion register. 14:8 reserved 7:0 version ? ro. this is a version number that i dentifies the implementation version.
intel ? i/o controller hub 6 (ich6) family datasheet 383 lpc interface bridge registers (d31:f0) 10.5.7 redir_tbl?redirectio n table (lpc i/f?d31:f0) index offset: 10h ? 11h (vector 0) through attribute: r/w, ro 3e ? 3fh (vector 23) default value: bit 16 = 1,. size: 64 bits each, (accessed as all other bits undefined two 32 bit quantities) the redirection table has a dedicated entry for ea ch interrupt input pin. the information in the redirection table is used to translate the interrupt manifestation on the corresponding interrupt pin into an apic message. the apic will respond to an edge triggered interrup t as long as the interrupt is held until after the acknowledge cycle has begun. once the interrupt is de tected, a delivery status bit internally to the i/o apic is set. the state machine will step ah ead and wait for an acknowledgment from the apic unit that the interrupt message was sent. only then will the i/o apic be ab le to recognize a new edge on that interrupt pin. that new edge will only result in a new invocation of the handler if its acceptance by the destination apic causes the interrupt request regi ster bit to go from 0 to 1. (in other words, if the interrupt was not already pending at the destination.) bit description 63:56 destination ? r/w. if bit 11 of this entry is 0 (physical) , then bits 59:56 specifies an apic id. in this case, bits 63:59 should be programmed by software to 0. if bit 11 of this entry is 1 (logical), then bits 63: 56 specify the logical destination address of a set of processors. 55:48 extended destination id (edid) ? ro. these bits are sent to a local apic only when in processor system bus mode. they become bits 11:4 of the address. 47:17 reserved 16 mask ? r/w. 0 = not masked: an edge or level on this interrupt pi n results in the delivery of the interrupt to the destination. 1 = masked: interrupts are not delivered nor held pending. setting this bit after the interrupt is accepted by a local apic has no effect on that in terrupt. this behavior is identical to the device withdrawing the interrupt before it is posted to t he processor. it is softwa re's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local apic unit but before the interru pt is dispensed to the processor. 15 trigger mode ? r/w. this field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = edge triggered. 1 = level triggered. 14 remote irr ? r/w. this bit is used for level tri ggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = reset when an eoi message is received from a local apic. 1 = set when local apic/s accept the le vel interrupt sent by the i/o apic. 13 interrupt input pin polarity ? r/w. this bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = active high. 1 = active low. 12 delivery status ? ro. this field contains the current status of the delivery of this interrupt. writes to this bit have no effect. 0 = idle. no activity for this interrupt. 1 = pending. interrupt has been injected, but delivery is not complete.
384 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) note: delivery mode encoding: 000 = fixed. deliver the signal on the intr signal of all processor cores lis ted in the destination. trigger mode can be edge or level. 001 = lowest priority. deliver the signal on the intr signal of the processor core that is executing at the lowest priority among all the processors listed in the spec ified destination. trigger mode can be edge or level. 010 = smi (system management interrupt). requires the interrupt to be programmed as edge triggered. the vector information is ignored but must be programmed to all 0?s for future compatibility: not supported 011 = reserved 100 = nmi. deliver the signal on the nmi signal of all proces sor cores listed in the destination. vector information is ignored. nmi is treated as an edge triggered interrupt even if it is programmed as level triggered. for proper operation this redirection table entry must be programmed to edge triggered. the nmi delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will continue counting through the redire ction table addresses. once the count for the nmi pin is reached again, the interrupt will be sent again: not supported 101 = init. deliver the signal to all processor cores list ed in the destination by asserting the init signal. all addressed local apics will assume their init state. init is always treated as an edge triggered interrupt even if programmed as level triggered. for proper operation this redirect ion table entry must be programmed to edge triggered. the init delivery mode does not set the rirr bit. if the redirection table is incorrectly set to level, the loop count will conti nue counting through the redirection table addresses. once the count for the init pin is reached again, the interrupt will be sent again: not supported 110 = reserved 111 = extint. deliver the signal to the intr signal of al l processor cores listed in the destination as an interrupt that originated in an externally connected 8259a comp atible interrupt controller. the inta cycle that corresponds to this extint delivery will be routed to the external controll er that is expected to supply the vector. requires the interrupt to be programmed as edge triggered. 11 destination mode ? r/w. this field determines the in terpretation of the destination field. 0 = physical. destination apic id is identified by bits 59:56. 1 = logical. destinations are ident ified by matching bit 63:56 with the logical destination in the destination format register and logical de stination register in each local apic. 10:8 delivery mode ? r/w. this field specifies how the apic s listed in the destinat ion field should act upon reception of this signal. cert ain delivery modes will only operate as intended when used in conjunction with a specific trigger mode. these encodings are listed in the note below: 7:0 vector ? r/w. this field contains the interrupt ve ctor for this interrupt. values range between 10h and feh. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 385 lpc interface bridge registers (d31:f0) 10.6 real time clock registers (lpc i/f?d31:f0) 10.6.1 i/o register addr ess map (lpc i/f?d31:f0) the rtc internal registers and ram are organi zed as two banks of 128 bytes each, called the standard and extended banks. the first 14 bytes of the standard bank contain the rtc time and date information along with four registers, a ? d, that are used for conf iguration of the rtc. the extended bank contains a full 128 bytes of batt ery backed sram, and will be accessible even when the rtc module is disabled (via the rtc configuration register). registers a ? d do not physically exist in the ram. all data movement between the host processor and the real-time clock is done through registers mapped to the standard i/o space. the register map appears in table 10-6 . notes: 1. i/o locations 70h and 71h are the standard legacy location for the real-time clock. the map for this bank is shown in table 10-7 . locations 72h and 73h are for accessi ng the extended ram. the extended ram bank is also accessed using an index ed scheme. i/o address 72h is us ed as the address pointer and i/o address 73h is used as the data register. index addr esses above 127h are not valid. if the extended ram is not needed, it may be disabled. 2. software must preserve the value of bit 7 at i/o addresses 70h and 74h. when writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. note that port 70h is not directly readable. th e only way to read this register is through alt access mode. although rtc index bits 6:0 are readable from por t 74h, bit 7 will always return 0. if the nmi# enable is not changed during normal operation, software can al ternatively read this bit once and then retain the value for all subsequent writes to port 70h. table 10-6. rtc i/o registers (lpc i/f?d31:f0) i/o locations if u128e bit = 0 function 70h and 74h also alias to 72h and 76h real-t ime clock (standard ram) index register 71h and 75h also alias to 73h and 77h real-time clock (standard ram) target register 72h and 76h extended ram index register (if enabled) 73h and 77h extended ram target register (if enabled)
386 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.6.2 indexed registers (lpc i/f?d31:f0) the rtc contains two sets of indexed registers that are accessed using the two separate index and target registers (70/71h or 72/73h), as shown in table 10-7 . table 10-7. rtc (standard) ram bank (lpc i/f?d31:f0) index name 00h seconds 01h seconds alarm 02h minutes 03h minutes alarm 04h hours 05h hours alarm 06h day of week 07h day of month 08h month 09h year 0ah register a 0bh register b 0ch register c 0dh register d 0eh?7fh 114 bytes of user ram
intel ? i/o controller hub 6 (ich6) family datasheet 387 lpc interface bridge registers (d31:f0) 10.6.2.1 rtc_rega?register a (lpc i/f?d31:f0) rtc index: 0a attribute: r/w default value: undefined size: 8-bit lockable: no power well: rtc this register is used for general configuration of the rtc functions. none of the bits are affected by rsmrst# or any other ich6 reset signal. bit description 7 update in progress (uip) ? r/w. this bit may be monitored as a status flag. 0 = the update cycle will not start for at least 488 s. the time, calendar, and alarm information in ram is always availabl e when the uip bit is 0. 1 = the update is soon to occur or is in progress. 6:4 division chain select (dv[2:0]) ? r/w. these three bits control the di vider chain for the oscillator, and are not affected by rsmrst# or any ot her reset signal. dv2 corresponds to bit 6. 010 = normal operation 11x = divider reset 101 = bypass 15 stages (test mode only) 100 = bypass 10 stages (test mode only) 011 = bypass 5 stages (test mode only) 001 = invalid 000 = invalid 3:0 rate select (rs[3:0]) ? r/w. these bits selects one of 13 taps of the 15 stage divider chain. the selected tap can generate a periodic interrupt if the pie bit is set in register b. otherwise this tap will set the pf flag of register c. if the periodic interr upt is not to be used, thes e bits should all be set to 0. rs3 corresponds to bit 3. 0000 = interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 s 0100 = 244.141 s 0101 = 488.281 s 0110 = 976.5625 s 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms
388 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.6.2.2 rtc_regb?register b (general configuration) (lpc i/f?d31:f0) rtc index: 0bh attribute: r/w default value: u0u00uuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 update cycle inhibit (set) ? r/w. this bit enables/inhibits the update cycles. this bit is not affected by rsmrst# nor any other reset signal. 0 = update cycle occurs normally once each second. 1 = a current update cycle will abort and subs equent update cycles will no t occur until set is returned to 0. when set is one, the bios may initialize time and calendar bytes safely. note: this bit should be set then cleared early in bios post after each powerup directly after coin-cell battery insertion. 6 periodic interrupt enable (pie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur with a ti me base set with the rs bits of register a. 5 alarm interrupt enable (aie) ? r/w. this bit is cleared by rtcrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when th e af is set by an alarm match from the update cycle. an alarm can occur once a sec ond, one an hour, once a day, or one a month. 4 update-ended interrupt enable (uie) ? r/w. this bit is cleared by rsmrst#, but not on any other reset. 0 = disable. 1 = enable. allows an interrupt to occur when the update cycle ends. 3 square wave enable (sqwe) ? r/w. this bit serves no function in the ich6. it is left in this register bank to provide compatib ility with the motorola 146818b. t he ich6 has no sqw pin. this bit is cleared by rsmrst#, but not on any other reset. 2 data mode (dm) ? r/w. this bit specifies either binary or bc d data representation. this bit is not affected by rsmrst# nor any other reset signal. 0 = bcd 1 = binary 1 hour format (hourform) ? r/w. this bit indicates the hour byte format. this bit is not affected by rsmrst# nor any other reset signal. 0 = twelve-hour mode. in twelve-hour mode, the seventh bit represents am as 0 and pm as one. 1 = twenty-four hour mode. 0 daylight savings enable (dse) ? r/w. this bit triggers two specia l hour updates per year. the days for the hour adjustment are those specified in united states federal law as of 1987, which is different than previous years. this bit is not affected by rs mrst# nor any other reset signal. 0 = daylight savings time updates do not occur. 1 = a) update on the first sunday in april, where time increments from 1:59:59 am to 3:00:00 am. b) update on the last sunday in october when t he time first reaches 1:59:59 am, it is changed to 1:00:00 am. the time must increment norma lly for at least two update cycles (seconds) previous to these conditions for the time change to occur properly.
intel ? i/o controller hub 6 (ich6) family datasheet 389 lpc interface bridge registers (d31:f0) 10.6.2.3 rtc_regc?register c (flag register) (lpc i/f?d31:f0) rtc index: 0ch attribute: ro default value: 00u00000 (u: undefined) size: 8-bit lockable: no power well: rtc writes to register c have no effect. 10.6.2.4 rtc_regd?register d (flag register) (lpc i/f?d31:f0) rtc index: 0dh attribute: r/w default value: 10uuuuuu (u: undefined) size: 8-bit lockable: no power well: rtc bit description 7 interrupt request flag (irqf) ? ro. irqf = (pf * pie) + (af * ai e) + (uf *ufe). this bit also causes the rtc interrupt to be asserted. this bi t is cleared upon rsmrst# or a read of register c. 6 periodic interrupt flag (pf) ? ro. this bit is cleared upon rsmrst# or a read of register c. 0 = if no taps are specified via the rs bits in register a, this flag will not be set. 1 = periodic interrupt flag will be 1 when the tap specified by the rs bits of register a is 1. 5 alarm flag (af) ? ro. 0 = this bit is cleared upon rtcrst# or a read of register c. 1 = alarm flag will be set after all alarm values match the current time. 4 update-ended flag (uf) ? ro. 0 = the bit is cleared upon rsmrst# or a read of register c. 1 = set immediately following an update cycle for each second. 3:0 reserved. will always report 0. bit description 7 valid ram and time bit (vrt) ? r/w. 0 = this bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = this bit is hardwired to 1 in the rtc power well. 6 reserved. this bit always returns a 0 and should be set to 0 for write cycles. 5:0 date alarm ? r/w. these bits store the date of month alar m value. if set to 000000b, then a don?t care state is assumed. the host must configure th e date alarm for these bits to do anything, yet they can be written at any time. if the date alarm is not enabled, these bits will re turn 0?s to mimic the functionality of the motorola 146818b. these bi ts are not affected by any reset assertion.
390 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.7 processor interface registers (lpc i/f?d31:f0) table 10-8 is the register address map fo r the processor in terface registers. 10.7.1 nmi_sc?nmi status and control register (lpc i/f?d31:f0) i/o address: 61h attribute: r/w, ro default value: 00h size: 8-bit lockable: no power well: core table 10-8. processor interface pci register address map (lpc i/f?d31:f0) offset mnemonic register name default type 61h nmi_sc nmi status and control 00h r/w, ro 70h nmi_en nmi enable 80h r/w (special) 92h port92 fast a20 and init 00h r/w f0h coproc_err coprocessor error 00h wo cf9h rst_cnt reset control 00h r/w bit description 7 serr# nmi source status (serr#_nmi_sts) ? ro. 1 = bit is set if a pci agent detected a system error and pulses the pci serr# line and if bit 2 (pci_serr_en) is cleared. this interrupt source is enabled by setting bit 2 to 0. to reset the interrupt, set bit 2 to 1 and then set it to 0. when writing to port 61h, this bit must be 0. note: this bit is set by any of the ich6 internal sources of serr; this includes serr assertions forwarded from the secondary pci bus, errors on a pci express* port, or other internal functions that generate serr#. 6 iochk# nmi source status (iochk_nmi_sts) ? ro. 1 = bit is set if an lpc agent (via serirq) as serted iochk# and if bit 3 (iochk_nmi_en) is cleared. this interrupt source is enabled by setting bit 3 to 0. to reset the interrupt, set bit 3 to 1 and then set it to 0. when writing to port 61h, this bit must be a 0. 5 timer counter 2 out status (tmr2_out_sts) ? ro. this bit reflects the current state of the 8254 counter 2 output. counter 2 must be programmed following any pci reset for this bit to have a determinate value. when writing to port 61h, this bit must be a 0. 4 refresh cycle toggle (ref_toggle) ? ro. this signal toggles from ei ther 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles woul d occur. when writing to port 61h, this bit must be a 0. 3 iochk# nmi enable (iochk_nmi_en) ? r/w. 0 = enabled. 1 = disabled and cleared. 2 pci serr# enable (pci_serr_en) ? r/w. 0 = serr# nmis are enabled. 1 = serr# nmis are disabled and cleared. 1 speaker data enable ( spkr_dat_en) ? r/w. 0 = spkr output is a 0. 1 = spkr output is equivalent to the counter 2 out signal value. 0 timer counter 2 enable (tim_cnt2_en) ? r/w. 0 = disable 1 = enable
intel ? i/o controller hub 6 (ich6) family datasheet 391 lpc interface bridge registers (d31:f0) 10.7.2 nmi_en?nmi enable (and real time clock index) register (lpc i/f?d31:f0) i/o address: 70h attri bute: r/w (special) default value: 80h size: 8-bit lockable: no power well: core note: the rtc index field is write-only for normal operation. this fiel d can only be read in alt-access mode. note, however, that this register is aliase d to port 74h (documented in), and all bits are readable at that address. 10.7.3 port92?fast a20 and in it register (lpc i/f?d31:f0) i/o address: 92h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bits description 7 nmi enable (nmi_en) ? r/w (special). 0 = enable nmi sources. 1 = disable all nmi sources. 6:0 real time clock index address (rtc_indx) ? r/w (special). this data goes to the rtc to select which register or cm os ram address is being accessed. bit description 7:2 reserved 1 alternate a20 gate (alt_a20_gate) ? r/w. this bit is or?d with the a20gate input signal to generate a20m# to the processor. 0 = a20m# signal can potentially go active. 1 = this bit is set when init# goes active. 0 init_now ? r/w. when this bit transitions from a 0 to a 1, the ich6 will force init# active for 16 pci clocks.
392 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.7.4 coproc_err?coprocessor error register (lpc i/f?d31:f0) i/o address: f0h attribute: wo default value: 00h size: 8-bits lockable: no power well: core 10.7.5 rst_cnt?reset control register (lpc i/f?d31:f0) i/o address: cf9h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core bits description 7:0 coprocessor error (coproc_err) ? wo. any value written to this register will cause ignne# to go active, if ferr# had generated an internal irq13. for ferr# to generate an internal irq13, the coproc_err_en bit (device 31:functi on 0, offset d0, bit 13) must be 1. bit description 7:4 reserved 3 full reset (full_rst) ? r/w. this bit is used to determine the states of slp_s3#, slp_s4#, and slp_s5# after a cf9 hard reset (sys_rst =1 and rst_cpu is set to 1), after pwrok going low (with rsmrst# high), or after two tco timeouts. 0 = ich6 will keep slp_s3#, slp_s4# and slp_s5# high. 1 = ich6 will drive slp_s3#, slp_s4# and slp_s5# low for 3 ? 5 seconds. note: when this bit is set, it also causes the full power cycle (slp_s3/4/5# assertion) in response to sysreset#, pwrok#, and watchdog timer reset sources. 2 reset cpu (rst_cpu) ? r/w. when this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the sys_rst bit (bit 1 of this register). 1 system reset (sys_rst) ? r/w. this bit is used to determine a hard or soft reset to the processor. 0 = when rst_cpu bit goes from 0 to 1, the ich6 performs a soft reset by activating init# for 16 pci clocks. 1 = when rst_cpu bit goes from 0 to 1, the ich6 performs a hard reset by activating pltrst# and sus_stat# active for about 5-6 millis econds, however the slp_s3#, slps4# and slp_s5# will not go active. the ich6 main power we ll is reset when this bit is 1. it also resets the resume well bits (except for those noted throughout the datasheet). 0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 393 lpc interface bridge registers (d31:f0) 10.8 power management registers (pm?d31:f0) the power management registers are distributed within the pci device 31 : function 0 space, as well as a separate i/o range. each register is desc ribed below. unless otherwise indicate, bits are in the main (core) power well. bits not explicitly defined in each register are assumed to be rese rved. when writing to a reserved bit, the value should always be 0. software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. 10.8.1 power management pc i configuration registers (pm?d31:f0) table 10-9 shows a small part of the c onfiguration space for pci device 31: function 0. it includes only those registers dedicated for power management. some of the registers are only used for legacy power management schemes. table 10-9. power management pci register address map (pm?d31:f0) offset mnemonic register name default type a0h gen_pmcon_1 general power management configuration 1 0000h r/w, ro, r/wo a2h gen_pmcon_2 general power management configuration 2 00h r/w, r/wc a4h gen_pmcon_3 general power management configuration 3 00h r/w, r/wc a9h cx-state_cnf cx state configuration (mobile only). 00h r/w aah c4-timing_cnt c4 timing control (mobile only). 00h r/w abh bm_break_en bm_break_en 00h r/w adh msc_fun miscellaneous functionality 00h r/w b8?bbh gpi_rout gpi route control 00000000h r/w
394 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.1.1 gen_pmcon_1?general pm configurati on 1 register (pm?d31:f0) offset address: a0h att ribute: r/w, ro, r/wo default value: 0000h size: 16-bit lockable: no usage: acpi, legacy power well: core bit description 15:11 reserved 10 bios_pci_exp_en ? r/w. this bit acts as a global e nable for the sci associated with the pci express* ports. 0 = the various pci express ports and (g)mch cannot cause the pci_exp_sts bit to go active. 1 = the various pci express ports and (g)mch c an cause the pci_exp_sts bit to go active. 9 pwrbtn_lvl ? ro. this bit indicates the current state of the pwrbtn# signal. 0 = low. 1 = high. 8reserved 7 (desktop only) reserved 7 (mobile only) enter c4 when c3 invoked (c4onc3_en) ? r/w. if this bit is set, then when software does a lvl3 read, the ich6 transitions to the c4 state. 6 i64_en . software sets this bit to indicate that the processor is an ia_64 processor, not an ia_32 processor. this may be used in various state machines where there are behavioral differences. 5 cpu slp# enable (cpuslp_en) ? r/w. 0 = disable. 1 = enables the cpuslp# signal to go active in the s1 state. this reduces the processor power. note: cpuslp# will go active during intel speedstep ? technology transitions and on entry to c3 and c4 states even if this bit is not set. 4 smi_lock ? r/wo. when this bit is set, writes to the glb_smi_en bit (pmbase + 30h, bit 0) will have no effect. once the smi_lock bit is set, writes of 0 to smi_lock bit will have no effect (i.e., once set, this bit can only be cleared by pltrst#). 3:2 (desktop only) reserved 3 (mobile only) intel speedstep enable (ss_en) ? r/w. 0 = intel speedstep technology logic is disabl ed and the ss_cnt register will not be visible (reads to ss_cnt will return 00h and writes will have no effect). 1 = intel speedstep technology logic is enabled. 2 (mobile only) pci clkrun# enable (clkrun_en) ? r/w. 0 = disable. ich6 drives the clkrun# signal low. 1 = enable clkrun# logic to control the system pci clock via the clkrun# and stp_pci# signals. note: when the slp_en# bit is set, the ich6 drives the clkrun# signal low regardless of the state of the clkrun_en bit. this ensur es that the pci and lpc clocks continue running during a transition to a sleep state. 1:0 periodic smi# rate select (per_smi_sel) ? r/w. set by software to control the rate at which periodic smi# is generated. 00 = 1 minute 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds
intel ? i/o controller hub 6 (ich6) family datasheet 395 lpc interface bridge registers (d31:f0) 10.8.1.2 gen_pmcon_2?general pm configuration 2 register (pm?d31:f0) offset address: a2h attribute: r/w, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: resume bit description 7 dram initialization bit ? r/w. this bit does not effect hardware functionality in any way. bios is expected to set this bit prior to starting the dram initialization sequence and to clear this bit after completing the dram initialization sequence. bios can detect that a dram initialization sequence was interrupted by a reset by readi ng this bit during the boot sequence. ? if the bit is 1, then the dram initialization was interrupted. ? this bit is reset by the assertion of the rsmrst# pin. 6:5 cpu pll lock time (cplt) ? r/w. this field indicates the amount of time that the processor needs to lock its plls. this is used wherever timing t270 ( chapter 22 ) applies. 00 = min 30.7 s (default) 01 = min 61.4 s 10 = min 122.8 s 11 = min 245.6 s it is the responsibility of the bios to program the corr ect value in this field prio r to the first transition to c3 or c4 states (or performing intel speedstep ? technology transitions). note: the new dpslp-to-slp bits (d31:f0:aah, bits 1:0) act as an override to these bits. note: these bits are not cleared by any type of reset except rsmrst# or a cf9 write 4 system reset status (srs) ? r/wc. software clears this bit by writing a 1 to it. 0 = sys_reset# button not pressed. 1 = ich6 sets this bit when the sys_reset# button is pressed. bios is expected to read this bit and clear it, if it is set. note: this bit is also reset by rsmrst# and cf9h resets. 3 cpu thermal trip status (cts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when pltrst# is inactive and th rmtrip# goes active whil e the system is in an s0 or s1 state. notes: 1. this bit is also reset by rs mrst#, and cf9h resets. it is not reset by the shutdown and reboot associated with the cputhrmtrip# event. 2. the cf9h reset in the description refers to cf9h type core well reset which includes sys_rst#, pwrok/vrmpwrgd low, smbus hard reset, tco ti meout. this type of reset will clear cts bit.
396 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) note: vrmpwrok is sampled using the rtc clock. theref ore, low times that are less than one rtc clock period may not be detected by the ich6. 2 minimum slp_s4# assertion width violation status ? r/wc. 0 = software clears this bi t by writing a 1 to it. 1 = hardware sets this bit when the slp_s4# assertion width is less than the time programmed in the slp_s4# minimum assertion width field (d31:f0 :offset a4h:bits 5:4). the ich6 begins the timer when slp_s4# is asserted during s4/s5 entry, or when the rsmrst# input is de- asserted during g3 exit. note that this bit is functional regardless of the value in the slp_s4# assertion stretch enable (d31:f0:offset a4h:bit 3). note: this bit is reset by the assertion of the rs mrst# pin, but can be set in some cases before the default value is readable. 1 cpu power failure (cpupwr_flr) ? r/wc. 0 = software (typically bios) clears this bit by writing a 0 to it. 1 = indicates that the vrmpwrgd signal from the processor?s vrm went low while the system was in an s0 or s1 state. 0 pwrok failure (pwrok_flr) ? r/wc. 0 = software clears this bit by writing a 1 to it, or when the system goes into a g3 state. 1 = this bit will be set any time pwrok goes low, w hen the system was in s0, or s1 state. the bit will be cleared only by software by writing a 1 to this bit or when the system goes to a g3 state. note: see chapter 5.14.11.3 for more details about the pwrok pin functionality. note: in the case of true pwrok failure, pwrok will go low first before the vrmpwrgd. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 397 lpc interface bridge registers (d31:f0) 10.8.1.3 gen_pmcon_3?general pm configuration 3 register (pm?d31:f0) offset address: a4h attribute: r/w, r/wc default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: rtc note: rsmrst# is sampled using the rt c clock. therefore, low times that are less than one rtc clock period may not be detected by the ich6. bit description 7:6 swsmi_rate_sel ? r/w. this field indicates w hen the swsmi timer will time out. valid values are: 00 = 1.5 ms 0.6 ms 01 = 16 ms 4 ms 10 = 32 ms 4 ms 11 = 64 ms 4 ms these bits are not cleared by any type of reset except rtcrst#. 5:4 slp_s4# minimum assertion width ? r/w. this field indicates the mi nimum assertion width of the slp_s4# signal to guarantee that th e drams have been safely power-cycled. valid values are: 11 = 1 to 2 seconds 10 = 2 to 3 seconds 01 = 3 to 4 seconds 00 = 4 to 5 seconds this value is used in two ways: 1. if the slp_s4# assertion width is ever shorter than this time, a status bit is set for bios to read when s0 is entered. 2. if enabled by bit 3 in this register, the har dware will prevent the slp_s4# signal from de- asserting within this minimu m time period after asserting. rtcrst# forces this field to th e conservative default state (00b) 3 slp_s4# assertion stretch enable ? r/w. 0 = the slp_s4# minimum assertion time is 1 to 2 rtcclk. 1 = the slp_s4# signal minimally assert for the ti me specified in bits 5:4 of this register. this bit is cleared by rtcrst# 2 rtc power status (rtc_pwr_sts) ? r/w. this bit is set when rtcrst# indicates a weak or missing battery. the bit is not clear ed by any type of reset. the bit will remain set until the software clears it by writing a 0 back to this bit position. 1 power failure (pwr_flr) ? r/wc. this bit is in the rtc well, and is not cleared by any type of reset except rtcrst#. 0 = indicates that the trickle current has not failed since the last time the bit was cleared. software clears this bit by writing a 1 to it. 1 = indicates that the trickle current (from the main battery or trickle suppl y) was removed or failed. note: clearing cmos in an ich-based platform ca n be done by using a jumper on rtcrst# or gpi, or using safemode strap. implementati ons should not attempt to clear cmos by using a jumper to pull vccrtc low. 0 afterg3_en ? r/w. this bit determines what state to go to when power is re-applied after a power failure (g3 state). this bit is in the rtc we ll and is not cleared by any type of reset except writes to cf9h or rtcrst#. 0 = system will return to s0 state (boot) after power is re-applied. 1 = system will return to the s5 state (except if it was in s4, in which case it will return to s4). in the s5 state, the only enabled wake event is the power button or any enabled wake event that was preserved through the power failure. note: bit will be set when thrmtrip#-based shutdown occurs.
398 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.1.4 cx-state_cnf?cx stat e configuration register (pm?d31:f0) (mobile only) offset address: a9h attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core this register is used to enable new c-state related modes. bit description 7 scratchpad (sp) ? r/w. 6:5 reserved 4 popdown mode enable (pdme) ? r/w. this bit is used in conjunction with the pume bit (d31:f0:a9h, bit 3). if pume is 0, then this bit must also be 0. 0 = the ich6 will not attempt to automatically return to a previous c3 or c4 state. 1 = when this bit is a 1 and intel ? ich6 observes that there are no bus master requests, it can return to a previous c3 or c4 state. note: this bit is separate from the pume bit to cover cases where latenc y issues permit popup but not popdown. 3 popup mode enable (pume) ? r/w. when this bit is a 0, the i ch6 behaves like ich5, in that bus master traffic is a break event, and it will retu rn from c3/c4 to c0 based on a break event. see chapter 5.14.5 for additional details on this mode. 0 = the ich6 will treat bus master traffic a break event, and will return from c3/c4 to c0 based on a break event. 1 = when this bit is a 1 and ich6 observes a bus mast er request, it will take the system from a c3 or c4 state to a c2 state and auto enable bus ma sters. this will let snoops and memory access occur. 2 report zero for bm_sts (bm_sts_zero_en) ? r/w. 0 = the ich6 sets bm_sts (pmbase + 00h, bit 4) if there is bus master activity from pci, pci express* and internal bus masters. 1 = when this bit is a 1, ich6 will not set the bm_s ts if there is bus master activity from pci, pci express and internal bus masters. notes: 1. if the bm_sts bit is already set when the bm_s ts_zero_en bit is set, the bm_sts bit will remain set. software will still need to clear the bm_sts bit. 2. it is expected that if the pume bit (this register, bit 3) is set, the bm_sts_zero_en bit should also be set. setting one without the other would mainly be for debug or errata workaround. 3. bm_sts will be set by lpc dma or lpc masters, even if bm_sts_zero_en is set. 1:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 399 lpc interface bridge registers (d31:f0) 10.8.1.5 c4-timing_cnt?c4 ti ming control register (pm?d31:f0) (mobile only) offset address: aah attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core this register is used to enable c-state related modes. bit description 7:4 reserved 3:2 dprslpvr to stpcpu ? r/w. this field selects the amount of time that the ich6 waits for from the de-assertion of dprslpvr to the de-asserti on of stp_cpu#. this provides a programmable time for the processor?s voltage to stabilize when ex iting from a c4 state. this thus changes the value for t266. 1:0 dpslp-to-slp ? r/w. this field selects the dpslp# de-assertion to cpu_slp# de-assertion time (t270). normally this value is deter mined by the cpu_pll_lock _time field in the gen_pmcon_2 register. when this field is non-zero , then the values in this register have higher priority. it is software?s responsibility to program these fields in a consistent manner. bits t266 min t266 max comment 00b 95 s 101 s default 01b 22 s 28 s value used for ?fast? vrms 10b reserved 11b reserved bits t270 00b use value is cpu_pll_lock_time field (default is 30 s) 01b 20 s 10b 15 s 11b 10 s
400 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.1.6 bm_break_en register (pm?d31:f0) (mobile only) offset address: abh attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi, legacy power well: core bit description 7 ide_break_en ? r/w. 0 = parallel ide or serial ata traf fic will not act as a break event. 1 = parallel ide or serial ata traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. parallel ide or serial at a master activity will cause bm_sts to be set and will cause a break from c3/c4. 6 pcie_break_en ? r/w. 0 = pci express* traffic will not act as a break event. 1 = pci express traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. pci express master acti vity will cause bm_sts to be se t and will cause a break from c3/c4. 5 pci_break_en ? r/w. 0 = pci traffic will not act as a break event. 1 = pci traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. pci master activity will cause bm_sts to be set and will cause a break from c3/c4. 4:3 reserved 2 ehci_break_en ? r/w. 0 = ehci traffic will not act as a break event. 1 = ehci traffic acts as a break event, even if the bm_sts-zero_en and popup_en bits are set. ehci master activity will cause bm_sts to be set and will cause a break from c3/c4. 1 uhci_break_en ? r/w. 0 = uhci traffic will not act as a break event. 1 = usb traffic from any of the internal uhcis acts as a break event, even if the bm_sts- zero_en and popup_en bits are set. uhci master activity will cause bm_sts to be set and will cause a break from c3/c4. 0 acaz_break_en ? r/w. 0 = ac ?97 or intel high definition audio traffic wi ll not act as a break event. 1 = ac ?97 or intel high definition audio traffic acts as a break event, even if the bm_sts- zero_en and popup_en bits are set. ac ?97 or intel high definition audio master acti vity will cause bm_sts to be set and will cause a break from c3/c4.
intel ? i/o controller hub 6 (ich6) family datasheet 401 lpc interface bridge registers (d31:f0) 10.8.1.7 msc_fun?miscellane ous functionality register (pm?d31:f0) offset address: adh attribute: r/w default value: 00h size: 8-bit power well: resume 10.8.1.8 gpi_rout?gpi rout ing control register (pm?d31:f0) offset address: b8h ? bbh attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: resume bit description 7:6 reserved 5 lpc generic range 2 bit 5 mask (lgr5m) ? r/w. 0 = the existing lpc generic i/o decode range 2 decodes bit 5 as defined in the d31:f0h:88h register description. 1 = the lpc generic i/o decode range 2 forces an address match on bit 5. note: if this bit is set, lgr4m (bit 4 of this register) must also be set. 4 lpc generic range 2 bit 4 mask (lgr4m) ? r/w. 0 = the existing lpc generic i/o decode range 2 decodes bit 4 as defined in the d31:f0h:88h register description. 1 = the lpc generic i/o decode range 2 forces an address match on bit 4. 3reserved 2 top swap status (tss) ? ro. this bit provides a r ead-only path to view the state of the top swap bit that is in the chipset confi guration registers:offset 3414h:bit 0. 1:0 usb transient disconnect detect (tdd) ? r/w: this field prevents a short single-ended zero (se0) condition on the usb ports from being inte rpreted by the uhci host controller as a disconnect. bios should set to 11b. bit description 31:30 gpi15 route ? r/w. see bits 1:0 for description. same pattern for gpi14 through gpi3 5:4 gpi2 route ? r/w. see bits 1:0 for description. 3:2 gpi1 route ? r/w. see bits 1:0 for description. 1:0 gpi0 route ? r/w. gpi[15:0] can be routed to cause an smi or sci when the gpi[n]_sts bit is set. if the gpio is not set to an input, this field has no effect. if the system is in an s1?s5 state and if the gpe0 _en bit is also set, then the gpi can cause a wake event, even if the gpi is not routed to cause an smi# or sci. 00 = no effect. 01 = smi# (if corresponding alt_ gpi_smi_en bit is also set) 10 = sci (if corresponding gpe0_en bit is also set) 11 = reserved software must set this bit field to generate th e appropriate type of system interrupt, depending on how the sci_en bit is set. for example, if the sc i_en bit is set, then this field must be programmed to 00b or 10b. if the sci_en bit is cleared, then this field must be programmed to 00b or 01b. software must also update this field if the sci_en bit is changed.
402 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) note: gpios that are not implemented will not have the corresponding bits implemented in this register. 10.8.2 apm i/o decode table 10-10 shows the i/o registers associ ated with apm support. this register space is enabled in the pci device 31: function 0 space (apmdec_en), and cannot be moved (fixed i/o location). 10.8.2.1 apm_cnt?advanced power management control port register i/o address: b2h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core 10.8.2.2 apm_sts?advanced powe r management status port register i/o address: b3h attribute: r/w default value: 00h size: 8-bit lockable: no usage: legacy only power well: core table 10-10. apm register map address mnemonic register name default type b2h apm_cnt advanced power management control port 00h r/w b3h apm_sts advanced power management status port 00h r/w bit description 7:0 this field is used to pass an apm command between the os and the smi handler. writes to this port not only store data in the apmc register, but also generates an smi# when the apmc_en bit is set. bit description 7:0 this field is used to pass data between the os a nd the smi handler. basically, this is a scratchpad register and is not affected by any other r egister or function (other than a pci reset).
intel ? i/o controller hub 6 (ich6) family datasheet 403 lpc interface bridge registers (d31:f0) 10.8.3 power management i/o registers table 10-11 shows the registers associat ed with acpi and legacy power management support. these registers are enabled in the pci devi ce 31: function 0 space (pm_io_en), and can be moved to any i/o location (128-byte aligned). the registers are defined to be compliant with the acpi 2.0 specification, and use the same bit names. note: all reserved bits and registers will always return 0 when read, and will have no effect when written. table 10-11. acpi and legacy i/o register map pmbase + offset mnemonic register name acpi pointer default type 00?01h pm1_sts pm1 status pm1a_evt_blk 0000h r/wc 02?03h pm1_en pm1 enable pm1a_evt_blk+2 0000h r/w 04?07h pm1_cnt pm1 control pm1a_cnt_blk 00000000h r/w, wo 08?0bh pm1_tmr pm1 timer pmtmr_blk xx000000h ro 0c?0fh ? reserved ? ? ? 10h?13h proc_cnt processor control p_blk 00000000h r/w, ro, wo 14h lv2 level 2 p_blk+4 00h ro 15h?16h ? reserved (desktop only) ? ? ? 15h lv3 level 3 (mobile only) p_blk+5 00h ro 16h lv4 level 4 (mobile only) p_blk+6 00h ro 17?1fh ? reserved ? ? ? 20h ? reserved (desktop only) ? ? ? 20h pm2_cnt pm2 control (mobile only) pm2a_cnt_blk 00h r/w 28?2bh gpe0_sts general purpose event 0 status gpe0_blk 00000000h r/w, r/wc 2c?2fh gpe0_en general purpose event 0 enables gpe0_blk+4 00000000h r/w 30?33h smi_en smi# control and enable 00000000h r/w, wo, r/w (special) 34?37h smi_sts smi status 00000000h r/wc, ro 38?39h alt_gp_smi_en alternate gpi smi enable 0000h r/w 3a?3bh alt_gp_smi_sts alternate gpi smi status 0000h r/wc 3c?43h ? reserved ? ? ? 44?45h devact_sts device activity status 0000h r/wc 46h?4fh ? reserved 50h ? reserved (desktop only) 50h ss_cnt intel speedstep ? technology control (mobile only) 01h r/w (special) 51h?5fh ? reserved ? ? ? 54h?57h c3_res (mobile only) c3-residency register ? 00000000h ro, r/w 60h?7fh ? reserved for tco ? ? ?
404 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.1 pm1_sts?power mana gement 1 status register i/o address: pmbase + 00h ( acpi pm1a_evt_blk ) attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 15: resume, except bit 11 in rtc if bit 10 or 8 in this register is set, and the corresponding _en bit is set in the pm1_en register, then the ich6 will generate a wake event. once back in an s0 state (or if already in an s0 state when the event occurs), the ich6 wi ll also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit is not set. note: bit 5 does not cause an smi# or a wake event. bi t 0 does not cause a wake event but can cause an smi# or sci. bit description 15 wake status (wak_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the system is in one of the sleep states (via the slp_en bit) and an enabled wake event occurs. upon setting this bit, t he ich6 will transition the system to the on state. if the afterg3_en bit is not set and a power fail ure (such as removed batteries) occurs without the slp_en bit set, the system will return to an s0 state when power returns, and the wak_sts bit will not be set. if the afterg3_en bit is set and a power failure occurs without the slp_en bit having been set, the system will go into an s5 state when power returns, and a subsequent wake event will cause the wak_sts bit to be set. note that any s ubsequent wake event would have to be caused by either a power button press, or an enabled wake event that was preserved through the power failure (enable bit in the rtc well). 14 reserved 13:12 reserved 11 power button override status (prbtnor_sts) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a power button overri de occurs (i.e., the power button is pressed for at least 4 consecutive seconds), or due to the corresponding bit in the smbus slave message. the power button override causes an unc onditional transition to the s5 state, as well as sets the afterg# bit. the bios or sc i handler clears this bit by writing a 1 to it. this bit is not affected by hard resets via cf 9h writes, and is not reset by rsmrst#. thus, this bit is preserved through power failures. no te that if this bit is still asserted when the global sci_en is set then an sci will be generated. 10 rtc status (rtc_sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write, but is reset by rsmrst#. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the rtc generates an alarm (assertion of the irq8# signal). additionally if the rtc_en bit (pmbase + 02h, bi t 10) is set, the setting of the rtc_sts bit will generate a wake event. 9reserved
intel ? i/o controller hub 6 (ich6) family datasheet 405 lpc interface bridge registers (d31:f0) 8 power button status ( pwrbtn__sts) ? r/wc. this bit is not affected by hard resets caused by a cf9 write. 0 = if the pwrbtn# signal is held low for more than 4 seconds, the hardware clears the pwrbtn_sts bit, sets the pwrbtnor_sts bit, and the system transitions to the s5 state with only pwrbtn# enabled as a wake event. this bit can be cleared by software by writing a one to the bit position. 1 = this bit is set by hardware when the pw rbtn# signal is assert ed low, independent of any other enable bit. in the s0 state, while pwrbtn_en and pwrbtn_sts are both set, an sci (or smi# if sci_en is not set) will be generated. in any sleeping state s1?s5, while pwrbtn_en (pmbase + 02h, bit 8) and pwrbtn_sts are both set, a wake event is generated. note: if the pwrbtn_sts bit is cleared by soft ware while the pwrbtn# signal is sell asserted, this will not cause the pwrbn_ sts bit to be set. the pwrbtn# signal must go inactive and active again to set the pwrbtn_sts bit. 7:6 reserved 5 global status (gbl _sts) ? r/wc. 0 = the sci handler should then clear this bit by writing a 1 to the bit location. 1 = set when an sci is generated due to bios wanting the attention of the sci handler. bios has a corresponding bit, bios_rls, whic h will cause an sci and set this bit. 4 (desktop only) reserved 4 (mobile only) bus master status (bm_sts) ? r/wc. this bit will not c ause a wake event, sci or smi#. 0 = software clears this bit by writing a 1 to it. 1 = set by the ich6 when a bus master requests a ccess to main memory. bus master activity is detected by any of the pci requests being acti ve, any internal bus master request being active, the bmbusy# signal being active, or req-c2 message received while in c3 or c4 state. notes: 1. if the bm_sts_zero_en bit is set, then this bit will generally report as a 0. lpc dma and bus master activity will always set the bm_sts bit, even if the bm_sts_zero_en bit is set. 3:1 reserved 0 timer overflow status (tmrof_sts) ? r/wc. 0 = the sci or smi# handler clears this bit by writing a 1 to the bit location. 1 = this bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). this will occur every 2.3435 seconds. when the tmrof_en bit (pmbase + 02h, bit 0) is set, then the setting of the tmrof_sts bit will additionally generate an sci or smi# (depending on the sci_en). bit description
406 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.2 pm1_en?power management 1 enable register i/o address: pmbase + 02h ( acpi pm1a_evt_blk + 2 ) attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 9, 11 ? 15: resume, bit 10: rtc bit description 15 reserved 14 reserved 13:11 reserved 10 rtc event enable (rtc_en) ? r/w. this bit is in the rtc well to allow an rtc event to wake after a power failure. this bit is not cleared by any reset other than rtcrst# or a power button override event. 0 = no sci (or smi#) or wake event is generated then rtc_sts (pmbase + 00h, bit 10) goes active. 1 = an sci (or smi#) or wake event will occu r when this bit is set and the rtc_sts bit goes active. 9 reserved. 8 power button enab le (pwrbtn_en) ? r/w. this bit is used to enable the setting of the pwrbtn_sts bit to generate a power managem ent event (smi#, sci). pwrbtn_en has no effect on the pwrbtn_sts bit (pmbase + 00h, bit 8) being set by the assertion of the power button. the power button is always enabled as a wake event. 0 = disable. 1 = enable. 7:6 reserved. 5 global enable (gbl_en) ? r/w. when both the gbl_en and the gbl_sts bit (pmbase + 00h, bit 5) are set, an sci is raised. 0 = disable. 1 = enable sci on gbl_sts going active. 4:1 reserved. 0 timer overflow interrupt enable (tmrof_en) ? r/w. works in conjunction with the sci_en bit (pmbase + 04h, bit 0) as described below: tmrof_en sci_en effect when tmrof_sts is set 0 x no smi# or sci 10 smi# 11 sci
intel ? i/o controller hub 6 (ich6) family datasheet 407 lpc interface bridge registers (d31:f0) 10.8.3.3 pm1_cnt?power management 1 control i/o address: pmbase + 04h ( acpi pm1a_cnt_blk ) attribute: r/w, wo default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: bits 0 ? 7: core, bits 8 ? 12: rtc, bits 13 ? 15: resume bit description 31:14 reserved. 13 sleep enable ( slp_en) ? wo. setting this bit causes the system to sequence into the sleep state defined by the slp_typ field. 12:10 sleep type (slp_typ) ? r/w. this 3-bit field defines the ty pe of sleep the system should enter when the slp_en bit is set to 1. these bits are only reset by rtcrst#. 9:3 reserved. 2 global release (gbl_rls) ? wo. 0 = this bit always reads as 0. 1 = acpi software writes a 1 to this bit to ra ise an event to the bios. bios software has a corresponding enable and status bits to cont rol its ability to receive acpi events. 1 (desktop only) reserved 1 (mobile only) bus master reload (bm_rld) ? r/w. this bit is treated as a sc ratchpad bit. this bit is reset to 0 by pltrst# 0 = bus master requests will not cause a break from the c3 state. 1 = enable bus master requests (internal, external or bmbusy#) to cause a break from the c3 state. if software fails to set this bit before going to c3 st ate, ich6 will still return to a snoopable state from c3 or c4 states due to bus master activity. 0 sci enable ( sci_en) ? r/w. selects the sci interrupt or the smi# interrupt for various events including the bits in the pm1_sts register (bit 10, 8, 0), and bits in gpe0_sts. 0 = these events will generate an smi#. 1 = these events will generate an sci. code master interrupt 000b on: typically maps to s0 state. 001b asserts stpclk#. puts processor in stop-grant state. optional to assert cpuslp# to put processor in sleep state: typically maps to s1 state. 010b reserved 011b reserved 100b reserved 101b suspend-to-ram. assert slp_s3#: typically maps to s3 state. 110b suspend-to-disk. assert slp_s3#, and sl p_s4#: typically maps to s4 state. 111b soft off. assert slp_s3#, slp_s4#, and slp_s5#: typically maps to s5 state.
408 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.4 pm1_tmr?power management 1 timer register i/o address: pmbase + 08h ( acpi pmtmr_blk ) attribute: ro default value: xx000000h size: 32-bit lockable: no usage: acpi power well: core 10.8.3.5 proc_cnt?processor control register i/o address: pmbase + 10h ( acpi p_blk ) attribute: r/w, ro, wo default value: 00000000h size: 32-bit lockable: no (bits 7:5 are write once) usage: acpi or legacy power well: core bit description 31:24 reserved 23:0 timer value (tmr_val) ? ro. returns the running count of the pm timer. this counter runs off a 3.579545 mhz clock (14.31818 mhz divided by 4). it is reset to 0 during a pci reset, and then continues counting as long as the system is in the s0 state. after an s1 state, the counter will not be reset (it will continue counting from the last value in s0 state. anytime bit 22 of the timer goes high to low (b its referenced from 0 to 23), the tmrof_sts bit (pmbase + 00h, bit 0) is set. the high-to-low tr ansition will occur every 2.3435 seconds. if the tmrof_en bit (pmbase + 02h, bit 0) is set, an sci interrupt is also generated. bit description 31:18 reserved 17 throttle status (thtl_sts) ? ro. 0 = no clock throttling is occurrin g (maximum processor performance). 1 = indicates that the clock state machine is th rottling the processor performance. this could be due to the tht_en bit or the force_thtl bit being set. 16:9 reserved 8 force thermal throttling (force_thtl) ? r/w. software can set this bit to force the thermal throttling function. 0 = no forced throttling. 1 = throttling at the duty cycle specified in th rm_dty starts immediately, and no smi# is generated.
intel ? i/o controller hub 6 (ich6) family datasheet 409 lpc interface bridge registers (d31:f0) 7:5 thrm_dty ? wo. this write-once fiel d determines the duty cycle of the throttling when the force_thtl bit is set. the duty cycle indicates the approximate percentage of time the stpclk# signal is asserted while in the throttle mode. t he stpclk# throttle period is 1024 pciclks. note that the throttling only occurs if the system is in the c0 state. if in the c2, c3, or c4 state, no throttling occurs. once the thrm_dty field is written, any subseque nt writes will have no effect until pltrst# goes active. 4 thtl_en ? r/w. when set and the system is in a c0 state, it enables a processor-controlled stpclk# throttling. the duty cycle is selected in the thtl_dty field. 0 = disable 1 = enable 3:1 thtl_dty ? r/w. this field determines the duty cycl e of the throttling when the thtl_en bit is set. the duty cycle indicates the approximate perc entage of time the stpc lk# signal is asserted (low) while in the throttle mode. the stpclk# throttle period is 1024 pciclks. 0 reserved bit description thrm_dty throttle mode pci clocks 000b 50% (default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128 thtl_dty throttle mode pci clocks 000b 50% (default) 512 001b 87.5% 896 010b 75.0% 768 011b 62.5% 640 100b 50% 512 101b 37.5% 384 110b 25% 256 111b 12.5% 128
410 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.6 lv2 ? level 2 register i/o address: pmbase + 14h ( acpi p_blk+4 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by intel ia64 processo rs or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the c2 state when the read to this register occurs 10.8.3.7 lv3?level 3 register (mobile only) i/o address: pmbase + 15h ( acpi p_blk + 5 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: if the c4onc3_en bit is set, reads this register will initiate a lvl4 transition rather than a lvl3 transition. in the event that software attemp ts to simultaneously read the lvl2 and lvl3 registers (which is illegal), the ich6 will ignore t he lvl3 read, and only perform a c2 transition. note: this register should not be used by ia64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the c3 state when the read to this register occurs. 10.8.3.8 lv4?level 4 register (mobile only) i/o address: pmbase + 16h ( acpi p_blk + 6 ) attribute: ro default value: 00h size: 8-bit lockable: no usage: acpi or legacy power well: core note: this register should not be used by ia64 processors or systems with more than 1 logical processor, unless appropriate semaphoring software has been put in place to ensure that all threads/processors are ready for the c4 state when the read to this register occurs. bit description 7:0 reads to this register return all 0s, writes to th is register have no effect. reads to this register generate a ?enter a level 2 power state? (c2) to the clock control logic. this will cause the stpclk# signal to go active, and stay active until a break ev ent occurs. throttling (due either to thtl_en or force_thtl) will be ignored. bit description 7:0 reads to this register return all 0s, writes to th is register have no effect. reads to this register generate a ?enter a c3 power state? to the clock c ontrol logic. the c3 stat e persists until a break event occurs. bit description 7:0 reads to this register return all 0s, writes to th is register have no effect. reads to this register generate a ?enter a c4 power state? to the clock c ontrol logic. the c4 stat e persists until a break event occurs.
intel ? i/o controller hub 6 (ich6) family datasheet 411 lpc interface bridge registers (d31:f0) 10.8.3.9 pm2_cnt?power manageme nt 2 control (mobile only) i/o address: pmbase + 20h ( acpi pm2_blk ) attribute: r/w default value: 00h size: 8-bit lockable: no usage: acpi power well: core 10.8.3.10 gpe0_sts?general pur pose event 0 st atus register i/o address: pmbase + 28h ( acpi gpe0_blk ) attribute: r/w, r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi power well: resume this register is symmetrical to the general pu rpose event 0 enable regi ster. unless indicated otherwise below, if the corresponding _en bit is set, then when the _sts bit get set, the ich6 will generate a wake event. once back in an s0 stat e (or if already in an s0 state when the event occurs), the ich6 will also generate an sci if the sci_en bit is set, or an smi# if the sci_en bit (pmbase + 04h, bit 0) is not set. bits 31:16 are re set by a cf9h write; bits 15:0 are not. all are reset by rsmrst#. bit description 7:1 reserved 0 arbiter disable (arb_dis) ? r/w. this bit is essentially just a scratchpad bit for legacy software compatibility. software typically sets this bit to 1 prior to entering a c3 or c4 state. when a transition to a c3 or c4 state occurs, ich6 will automatical ly prevent any internal or external non-isoch bus masters from initiating any cycles up to the (g)mch. this blocking starts immediately upon the ich6 sending the go-c3 message to the (g)mch. the blocking stops when the ack-c2 message is received. note that this is not really blocking, in that messages (such as from pci express*) are just queued and held pending. bit description 31:16 gpin_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = these bits are set any time the corres ponding gpio is set up as an input and the corresponding gpio signal is high (or low if the corresponding gp_inv bit is set). if the corresponding enable bit is set in the gpe0_e n register, then when the gpi[n]_sts bit is set: ? if the system is in an s1?s5 state, the event will also wake the system. ? if the system is in an s0 state (or upon waki ng back to an s0 state), a sci will be caused depending on the gpi_rout bits (d31:f0:b8h, bits 31:30) for the corresponding gpi. note: mapping is as follows: bit 31 corresponds to gpi[15] ... and bit 16 corresponds to gpi:[0]. 15 reserved 14 usb4_sts ? r/w. 0 = disable. 1 = set by hardware and can be reset by writing a one to this bit position or a resume well reset. this bit is set when usb uhci controller #4 needs to cause a wake. additionally if the usb4_en bit is set, the setting of the u sb4_sts bit will generate a wake event.
412 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 13 pme_b0_sts ? r/w. this bit will be set to 1 by t he ich6 when any internal device with pci power management capabilities on bus 0 asserts the equivalent of the pme# signal. additionally, if the pme_b0_en bit is set, and the system is in an s0 state, then the setting of the pme_b0_sts bit will generate an sci (or smi# if sc i_en is not set). if the pme_b0_sts bit is set, and the system is in an s1?s4 state (or s5 state due to slp_typ and slp_en), then the setting of the pme_b0_sts bit will generate a wake event, and an sci (or smi# if sci_en is not set) will be generated. if the system is in an s5 state due to power button override, then the pme_b0_sts bit will not cause a wake event or sci. the default for this bit is 0. writing a 1 to this bit position clears this bit. 12 usb3_sts ? r/w. 0 = disable. 1 = set by hardware and can be reset by writing a one to this bit position or a resume well reset. this bit is set when usb uhci controller #3 needs to cause a wake. additionally if the usb3_en bit is set, the setting of the u sb3_sts bit will generate a wake event. 11 pme_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the pme# signal goes ac tive. additionally, if the pme_en bit is set, and the system is in an s0 state, then the setting of the pme_sts bit will generate an sci or smi# (if sci_en is not set). if the pme_en bit is set, and the system is in an s1?s4 state (or s5 state due to setting slp_typ and slp_en), then the setting of the pme_sts bit will generate a wake event, and an sci will be generated. if the system is in an s5 state due to power button override or a power failure, then pme_sts will not cause a wake event or sci. 10 (desktop only) reserved 10 (mobile only) batlow_sts ? r/wc. (mobile only) software clears this bit by writing a 1 to it. 0 = batlow# not asserted 1 = set by hardware when the batlow# signal is asserted. 9 pci_exp_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware to indicate that: ? the pme event message was received on one or more of the pci express* ports ? an assert pmegpe message received from the (g)mch via dmi notes: 1. the pci wake# pin has no impact on this bit. 2. if the pci_exp_sts bit went active due to an assert pmegpe message, then a de-assert pmegpe message must be received prior to the software write in order for the bit to be cleared. 3. if the bit is not cleared and the corresponding pci_exp_en bit is set, the level-triggered sci will remain active. 4. a race condition exists where the pci ex press device sends another pme message because the pci express device was not serviced within the time w hen it must resend the message. this may result in a spurious interrup t, and this is comprehended and approved by the pci express* specification, revision 1.0a . the window for this race condition is approximately 95- 105 milliseconds. 8 ri_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the ri# input signal goes active. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 413 lpc interface bridge registers (d31:f0) 7 smbus wake status (smb_wak_sts) ? r/wc. the smbus controller can independently cause an smi# or sci, so this bit does not need to do so (unlike the other bi ts in this register). software clears this bit by writing a 1 to it. 0 = wake event not caused by the ich6?s smbus logic. 1 = set by hardware to indicate that the wake ev ent was caused by the ic h6?s smbus logic.this bit will be set by the wake/smi# command type, even if the system is already awake. the smi handler should then clear this bit. notes: 1. this bit is set by the smbus slave command 01h (wake/smi#) even when the system is in the s0 state. therefore, to avoid an instant wa ke on subsequent transitions to sleep states, software must clear this bit after each reception of the wake/smi# command or just prior to entering the sleep state. 2. if smb_wak_sts is set due to smbus slave re ceiving a message, it will be cleared by internal logic when a thrmtrip# event happens or a power button override event. however, thrmtrip# or power button override event will not clear smb_wak_sts if it is set due to smbalert# signal going active. 3. the smbalert_sts bit (d31:f3:i/o offset 00h: bit 5) should be cleared by software before the smb_wak_sts bit is cleared. 6 tcosci_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = toc logic did not cause sci. 1 = set by hardware when the tco logic causes an sci. 5 ac97_sts ? r/wc. this bit will be set to 1 when the codecs are attempting to wake the system and the pme events for the codecs are armed for wakeup. a pme is armed by programming the appropriate pmee bit in the power management control and status register at bit 8 of offset 54h in each ac ?97 function. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when the codecs are attemp ting to wake the system. the ac97_sts bit gets set only from the following two cases: 1.the pmee bit for the function is set, and o the ac-link bit clock has been shut and the routed acz_sdin line is high (for audio, if routing is disabled, no wake events are allowed. 2.for modem, if audio routing is disabled, then the wake event is an or of all acz_sdin lines. if routing is enabled, then the wake ev ent for modem is the remaining non-routed acz_sdin line), or o gpi status change interrupt bit (nabmbar + 30h, bit 0) is 1. note: this bit is not affected by a hard reset caused by a cf9h write. note: this bit is also used for intel high definition audio when ich6 is configured to use the intel high definition audio host controller rather than the ac97 host controller. 4 usb2_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 2 does not need to cause a wake. 1 = set by hardware when usb uhci controller 2 needs to cause a wake. wake event will be generated if the corresponding usb2_en bit is set. 3 usb1_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = usb uhci controller 1 does not need to cause a wake. 1 = set by hardware when usb uhci controller 1 needs to cause a wake. wake event will be generated if the corresponding usb1_en bit is set. 2 reserved 1 hot_plug_sts ? r/wc. 0 = this bit is cleared by writ ing a 1 to this bit position. 1 = when a pci express* hot-plug event occurs. th is will cause an sc i if the hot_plug_en bit is set in the gep0_en register. 0 thermal interrupt status (thrm_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = thrm# signal not driven active as defined by the thrm_pol bit 1 = set by hardware anytime the thrm# signal is driven active as defined by the thrm_pol bit. additionally, if the thrm_en bit is set, t hen the setting of the thrm_sts bit will also generate a power management event (sci or smi#). bit description
414 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.11 gpe0_en?general purp ose event 0 enables register i/o address: pmbase + 2ch ( acpi gpe0_blk + 4 ) attribute: r/w default value: 00000000h size: 32-bit lockable: no usage: acpi power well: bits 0?7, 9, 12, 14?31 resume, bits 8, 10?11, 13 rtc this register is symmetrical to the general purpos e event 0 status register. all the bits in this register should be cleared to 0 based on a power button override or proce ssor thermal trip event. the resume well bits are all cleared by rsmr st#. the rtc sell bits are cleared by rtcrst#. bit description 31:16 gpin_en ? r/w. these bits enable the corresponding gpi[n]_sts bits being set to cause a sci, and/or wake event. these bits are cleared by rsmrst#. note: mapping is as follows: bit 31 corresponds to gpi[15] ... and bit 16 corresponds to gpi[0]. 15 reserved 14 usb4_en ? r/w. 0 = disable. 1 = enable the setting of the usb4_sts bit to generate a wake event. the usb4_sts bit is set anytime usb uhci controller #4 signals a wake event. break events are handled via the usb interrupt. 13 pme_b0_en ? r/w. 0 = disable 1 = enables the setting of the pme_b0_sts bit to generate a wake event and/or an sci or smi#. pme_b0_sts can be a wake event from the s1?s4 states, or from s5 (if entered via slp_typ and slp_en) or power failure, but not power button override. this bit defaults to 0. note: it is only cleared by software or rtcrst#. it is not cleared by cf9h writes. 12 usb3_en ? r/w. 0 = disable. 1 = enable the setting of the usb3_sts bit to generate a wake event. the usb3_sts bit is set anytime usb uhci controller #3 signals a wake event. break events are handled via the usb interrupt. 11 pme_en ? r/w. 0 = disable. 1 = enables the setting of the pme_sts to generate a wake event and/or an sci. pme# can be a wake event from the s1 ? s4 state or from s5 (if entered via slp_en, but not power button override). 10 (desktop only) reserved 10 (mobile only) batlow_en ? r/w. (mobile only) 0 = disable. 1 = enables the batlow# signal to cause an sm i# or sci (depending on the sci_en bit) when it goes low. this bit does not prevent the ba tlow# signal from inhi biting the wake event. 9 pci_exp_en ? r/w. 0 = disable sci generation upon pci_exp_sts bit being set. 1 = enables ich6 to cause an sci when pci_exp_sts bit is set. this is used to allow the pci express* ports, including the link to the (g)m ch, to cause an sci due to wake/pme events.
intel ? i/o controller hub 6 (ich6) family datasheet 415 lpc interface bridge registers (d31:f0) 8 ri_en ? r/w. the value of this bit will be maintained through a g3 state and is not affected by a hard reset caused by a cf9h write. 0 = disable. 1 = enables the setting of the ri_sts to generate a wake event. 7 reserved 6 tcosci_en ? r/w. 0 = disable. 1 = enables the setting of the tcosci_sts to generate an sci. 5 ac97_en ? r/w. 0 = disable. 1 = enables the setting of the ac97_sts to generate a wake event. note: this bit is also used for intel high definition audio when the intel high definition audio host controller is enabled rather than the ac97 host controller. 4 usb2_en ? r/w. 0 = disable. 1 = enables the setting of the usb2_sts to generate a wake event. 3 usb1_en ? r/w. 0 = disable. 1 = enables the setting of the usb1_sts to generate a wake event. 2 thrm#_pol ? r/w. this bit controls the polarity of the thrm# pin needed to set the thrm_sts bit. 0 = low value on the thrm# signal will set the thrm_sts bit. 1 = high value on the thrm# signal will set the thrm_sts bit. 1 hot_plug_en ? r/w. 0 = disables sci generation upon the hot_plug_sts bit being set. 1 = enables the ich6 to cause an sci when the hot_ plug_sts bit is set. this is used to allow the pci express ports to cause an sci due to hot-plug events. 0 thrm_en ? r/w. 0 = disable. 1 = active assertion of the thrm# signal (as defined by the thrm_pol bit) will set the thrm_sts bit and generate a power management event (sci or smi). bit description
416 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.12 smi_en?smi cont rol and enable register i/o address: pmbase + 30h attribute: r/w, r/w (special), wo default value: 00000000h size: 32 bit lockable: no usage: acpi or legacy power well: core note: this register is symmetrical to the smi status register. bit description 31:19 reserved 18 intel_usb2_en ? r/w. 0 = disable 1 = enables intel-specific u sb2 smi logic to cause smi#. 17 legacy_usb2_en ? r/w. 0 = disable 1 = enables legacy usb2 logic to cause smi#. 16:15 reserved 14 periodic_en ? r/w. 0 = disable. 1 = enables the ich6 to generate an smi# when the periodic_sts bit (pmbase + 34h, bit 14) is set in the smi_sts register (pmbase + 34h). 13 tco_en ? r/w. 0 = disables tco logic generating an smi#. note that if the nmi2smi_en bit is set, smis that are caused by re-routed nmis will not be gated by the tco_en bit. even if the tco_en bit is 0, nmis will still be ro uted to cause smis. 1 = enables the tco logic to generate smi#. note: this bit cannot be written once the tco_lock bit is set. 12 reserved 11 mcsmi_enmicrocontroller smi enable (mcsmi_en) ? r/w. 0 = disable. 1 = enables ich6 to trap accesses to the mi crocontroller range (62h or 66h) and generate an smi#. note that ?trapped? cycles will be claim ed by the ich6 on pci, but not forwarded to lpc. 10:8 reserved 7 bios release (bios_rls) ? wo. 0 = this bit will always return 0 on reads . writes of 0 to this bit have no effect. 1 = enables the generation of an sci interrupt for acpi software when a one is written to this bit position by bios software. note: gbl_sts being set will cause an sci, even if the sci_en bit is not set. software must take great care not to set the bios_rls bit (which causes gbl_sts to be set) if the sci handler is not in place. 6 software smi# timer enable (swsmi_tmr_en) ? r/w. 0 = disable. clearing the swsmi_tmr_en bit before the timer expires will reset the timer and the smi# will not be generated. 1 = starts software smi# timer. when the sw smi timer expires (the timeout period depends upon the swsmi_rate_sel bit setting), swsmi_tmr_sts is set and an smi# is generated. swsmi_tmr_en stays set until cleared by software. 5 apmc_en ? r/w. 0 = disable. writes to the apm_cnt register will not cause an smi#. 1 = enables writes to the apm_cnt register to cause an smi#.
intel ? i/o controller hub 6 (ich6) family datasheet 417 lpc interface bridge registers (d31:f0) 4 slp_smi_en ? r/w. 0 = disables the generation of smi# on slp_en. note that this bit must be 0 before the software attempts to transition the system into a sl eep state by writing a 1 to the slp_en bit. 1 = a write of 1 to the slp_en bit (bit 13 in pm1_cnt register) will generate an smi#, and the system will not transition to the sleep st ate based on that write to the slp_en bit. 3 legacy_usb_en ? r/w. 0 = disable. 1 = enables legacy usb ci rcuit to cause smi#. 2 bios_en ? r/w. 0 = disable. 1 = enables the generation of smi# when acpi software writes a 1 to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). note that if t he bios_sts bit (d31:f0:pmbase + 34h:bit 2), which gets set when software writes 1 to gbl_rls bit, is already a 1 at the time that bios_en becomes 1, an smi# will be generated when bios_en gets set. 1 end of smi (eos) ? r/w (special). this bit controls the arbitration of the smi signal to the processor. this bit must be set for the ich6 to assert smi# low to the processor after smi# has been asserted previously. 0 = once the ich6 asserts smi# low, the eos bit is au tomatically cleared. 1 = when this bit is set to 1, smi# signal will be de-asserted for 4 pci clocks before its assertion. in the smi handler, the processor should clear al l pending smis (by servicing them and then clearing their respective status bits), set the eos bit, and ex it smm. this will allow the smi arbiter to re-assert smi upon detection of an smi event and the setting of a smi status bit. note: ich6 is able to generate 1st smi after rese t even though eos bit is not set. subsequent smi require eos bit is set. 0 gbl_smi_en ? r/w. 0 = no smi# will be generated by ich6. this bit is reset by a pci reset event. 1 = enables the generation of smi# in the system upon any enabled smi event. note: when the smi_lock bit is set, this bit cannot be changed. bit description
418 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.13 smi_sts?sm i status register i/o address: pmbase + 34h attribute: ro, r/wc default value: 00000000h size: 32-bit lockable: no usage: acpi or legacy power well: core note: if the corresponding _en bit is se t when the _sts bit is set, the ich6 will cause an smi# (except bits 8 ? 10 and 12, which do not need enable bits since they are logic ors of other registers that have enable bits). the ich6 uses the same gpe0_en register (i/o address: pmbase+2ch) to enable/disable both smi and acpi sci general purpose input events. acpi os assumes that it owns the entire gpe0_en register per acpi sp ec. problems arise when some of the general- purpose inputs are enabled as smi by bios, and some of the general purpose inputs are enabled for sci. in this case acpi os turns off the enabled bi t for any gpix input signals that are not indicated as sci general-purpose events at boot, and exit from sleeping states. bios should define a dummy control method which prevents the ac pi os from clearing the smi gpe0_en bits. bit description 31:20 reserved 21 monitor_sts ? ro. this bit will be set if the trap/smi l ogic has caused the smi. this will occur when the processor or a bus master accesses an assigned register (or a sequence of accesses). see section 7.1.32 thru section 7.1.35 for details on the specific cause of the smi. 20 pci_exp_smi_sts ? ro. pci express* smi event occurred. th is could be due to a pci express pme event or hot-plug event. 19 reserved 18 intel_usb2_sts ? ro. this non-sticky read-only bit is a l ogical or of each of the smi status bits in the intel-specific usb2 smi status regi ster anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 17 legacy_usb2_sts ? ro. this non-sticky read-only bit is a l ogical or of each of the smi status bits in the usb2 legacy support register anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. writes to this bit will have no effect. 16 smbus smi status (smbus_smi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = this bit is set from the 64 khz clock domain us ed by the smbus. software must wait at least 15.63 us after the initial assertion of this bit before clearing it. 1 = indicates that the smi# was caused by: 1. the smbus slave receiving a mess age that an smi# should be caused, or 2. the smbalert# signal goes active and the smb_smi_en bit is set and the smbalert_dis bit is cleared, or 3. the smbus slave receiving a host noti fy message and the host_notify_intren and the smb_smi_en bits are set, or 4. the ich6 detecting the smlink_slave_smi command while in the s0 state. 15 serirq_smi_sts ? ro. 0 = smi# was not caused by the serirq decoder. 1 = indicates that the smi# was caused by the serirq decoder. note: this is not a sticky bit 14 periodic_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set at the rate determined by the per_smi_sel bits. if the periodic_en bit (pmbase + 30h, bit 14) is also set, the ich6 generates an smi#. 13 tco_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = smi# not caused by tco logic. 1 = indicates the smi# was caused by the tco logic. note that this is not a wake event.
intel ? i/o controller hub 6 (ich6) family datasheet 419 lpc interface bridge registers (d31:f0) 12 device monitor status (devmon_sts) ? ro. 0 = smi# not caused by device monitor. 1 = set if bit 0 of the devact_sts register (pm base + 44h) is set. the bit is not sticky, so writes to this bit will have no effect. 11 microcontroller smi# status ( mcsmi_sts) ? r/wc. software clears this bit by writing a 1 to it. 0 = indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = set if there has been an access to the power management microcontroller range (62h or 66h) and the microcontroller decode enable #1 bit in the lpc bridge i/o e nables configuration register is 1 (d31:f0:offset 82h:bit 11). note that this implementation assumes that the microcontroller is on lpc. if this bit is set, and the mcsmi_en bit is also set, the ich6 will generate an smi#. 10 gpe0_sts ? ro. this bit is a logical or of the bits in the alt_gp_smi_sts register that are also set up to cause an smi# (as indicated by the gp i_rout registers) and have the corresponding bit set in the alt_gp_smi_en register. bits that are not routed to cause an smi# will have no effect on this bit. 0 = smi# was not generated by a gpi assertion. 1 = smi# was generated by a gpi assertion. 9 gpe0_sts ? ro. this bit is a logical or of the bits 14: 10, 8:2, and 0 in the gpe0_sts register (pmbase + 28h) that also have the corresponding bit set in the gpe0_en register (pmbase + 2ch). 0 = smi# was not generated by a gpe0 event. 1 = smi# was generated by a gpe0 event. 8 pm1_sts_reg ? ro. this is an ors of the bits in the acpi pm1 status register (offset pmbase+00h) that can cause an smi#. 0 = smi# was not generated by a pm1_sts event. 1 = smi# was generated by a pm1_sts event. 7 reserved 6 swsmi_tmr_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = software smi# timer has not expired. 1 = set by the hardware when the software smi# timer expires. 5 apm_sts ? r/wc. software clears this bit by writing a 1 to it. 0 = no smi# generated by write access to apm control register with apmch_en bit set. 1 = smi# was generated by a write access to the apm control register with the apmc_en bit set. 4 slp_smi_sts ? r/wc. software clears this bit by writing a 1 to the bit location. 0 = no smi# caused by write of 1 to slp_ en bit when slp_smi_en bit is also set. 1 = indicates an smi# was caused by a write of 1 to slp_en bit when slp_smi_en bit is also set. 3 legacy_usb_sts ? ro. this bit is a logical or of eac h of the smi status bits in the usb legacy keyboard/mouse control registers anded with the corresponding enable bits. this bit will not be active if the enable bits are not set. 0 = smi# was not generated by usb legacy event. 1 = smi# was generated by usb legacy event. 2 bios_sts ? r/wc. 0 = no smi# generated due to acpi software requesting attention. 1 = this bit gets set by hardware when a 1 is written by software to the gbl_rls bit (d31:f0:pmbase + 04h:bit 2). when both the bios_en bit (d31:f0:pmbase + 30h:bit 2) and the bios_sts bit are set, an smi# will be generated. the bios_sts bit is cleared when software writes a 1 to its bit position. 1:0 reserved bit description
420 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.14 alt_gp_smi_en?altern ate gpi smi enable register i/o address: pmbase +38h attribute: r/w default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume 10.8.3.15 alt_gp_smi_sts?alterna te gpi smi status register i/o address: pmbase +3ah attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: acpi or legacy power well: resume bit description 15:0 alternate gpi smi enable ? r/w. these bits are used to enable the corresponding gpio to cause an smi#. for these bits to have any effect, the following must be true. ? the corresponding bit in the alt_gp_smi_en register is set. ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. note: mapping is as follows: bit 15 corresponds to gpi[15] ... bit 0 corresponds to gpi[0]. bit description 15:0 alternate gpi smi status ? r/wc. these bits report the status of the corresponding gpis. 0 = inactive. software clears this bit by writing a 1 to it. 1 = active these bits are sticky. if the following conditi ons are true, then an smi# will be generated and the gpe0_sts bit set: ? the corresponding bit in the alt_gpi_smi_en register (pmbase + 38h) is set ? the corresponding gpi must be routed in the gpi_rout register to cause an smi. ? the corresponding gpio must be implemented. all bits are in the resume well. default for t hese bits is dependent on the state of the gpi pins.
intel ? i/o controller hub 6 (ich6) family datasheet 421 lpc interface bridge registers (d31:f0) 10.8.3.16 devact_sts ? device activity status register i/o address: pmbase +44h attribute: r/wc default value: 0000h size: 16-bit lockable: no usage: legacy only power well: core each bit indicates if an access has occurred to the corresponding devi ce?s trap range, or for bits 6:9 if the corresponding pci interrupt is active. this register is used in conjunction with the periodic smi# timer to detect any system activity for legacy power management. the periodic smi# timer indicates if it is the right time to read the devact_sts register (pmbase + 44h). note: software clears bits that are set in this register by writing a 1 to the bit position. bit description 15:13 reserved 12 kbc_act_sts ? r/wc. kbc (60/64h). 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. clear this bit by writing a 1 to the bit location. 11:10 reserved 9 pirqdh_act_sts ? r/wc. pirq[d or h]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pc i interrupts has been active. clear this bit by writing a 1 to the bit location. 8 pirqcg_act_sts ? r/wc. pirq[c or g]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pc i interrupts has been active. clear this bit by writing a 1 to the bit location. 7 pirqbf_act_sts ? r/wc. pirq[b or f]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pc i interrupts has been active. clear this bit by writing a 1 to the bit location. 6 pirqae_act_sts ? r/wc. pirq[a or e]. 0 = the corresponding pci interrupts have not been active. 1 = at least one of the corresponding pc i interrupts has been active. clear this bit by writing a 1 to the bit location. 5:1 reserved 0 ide_act_sts ? r/wc. ide primary drive 0 and drive 1. 0 = indicates that there has been no access to this device?s i/o range. 1 = this device?s i/o range has been accessed. the enable bit is in the atc register (d31:f1:offset c0h). clear this bit by writing a 1 to the bit location.
422 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.8.3.17 ss_cnt? intel speedstep ? technology control register (mobile only) i/o address: pmbase +50h attribute: r/w (special) default value 01h size: 8-bit lockable: no usage: acpi/legacy power well: core note: writes to this register will initiate an intel speedstep technology transition that involves a temporary transition to a c3-lik e state in which the stpclk# si gnal will go active. an intel speedstep technology transition always occur on writes to the ss_cnt register, even if the value written to ss_state is the same as the previous value (after this ?transition? the system would still be in the same intel speedstep technology state). if the ss_en bi t is 0, then writes to this register will have no effe ct and reads will return 0. 10.8.3.18 c3_res? c3 residen cy register (mobile only) i/o address: pmbase +5 4h attribute: rw/ro default value 00000000h size: 32-bit lockable: no usage: acpi/legacy power well: core software may only write this register during system initialization to set the state of the c3_residency_mode bit. it must not be written while the timer is in use. bit description 7:1 reserved 0 ss_state (intel speedstep ? technology state) ? r/w (special). when this bit is read, it returns the last value written to this register. by conv ention, this will be the current intel speedstep technology state. writes to this register caus es a change to the intel speedstep technology state indicated by the value written to this bit. if the new value for ss_state is the same as the previous value, then transition will still occur. 0 = high power state. 1 = low power state note: this is only a convention because the transition is the same regardless of the value written to this bit. bit description 31 c3_resedency_mode ? rw. when this bit is 0, the c3_resi dency counter field will automati cally clear upon entry into the c3 or c4 state. when this bit is 1, the c3_reside ncy counter will not autom atically clear upon entry into the c3 or c4 state. 30:24 reserved 23:0 c3_residency ? ro. the value in this field increments at the same rate as the power management timer. if the c3_resedency_mode bit is clear, this field automatically resets to 0 at the point when the lvl3 or lvl4 read occurs. if the c3_residency_mode bit is set, the register does not reset when the lvl3 or lvl4 read occurs. in either mode, it increments while stp_cpu# is active (i.e. the processor is in a c3 or c4 state). th is field will roll over in the same way as the pm timer, however the most signi ficant bit is not sticky. software is responsible for reading this field befor e performing the lvl3/4 transition. software must also check for rollover if the maxi mum time in c3/c4 could be exceeded.
intel ? i/o controller hub 6 (ich6) family datasheet 423 lpc interface bridge registers (d31:f0) 10.9 system management tco registers (d31:f0) the tco logic is accessed via registers ma pped to the pci configuration space (device 31:function 0) and the system i/o space. for tc o pci configuration regi sters, see lpc device 31:function 0 pci configuration registers. tco register i/o map the tco i/o registers reside in a 32-byte ra nge pointed to by a tcobase value, which is, pmbase + 60h in the pci config uration space. the following ta ble shows the mapping of the registers within that 32-byte range. each regi ster is described in the following sections. 10.9.1 tco_rld?tco timer reload and current value register i/o address: tcobase +00h attribute: r/w default value: 0000h size: 16-bit lockable: no power well: core table 10-12. tco i/o register address map tcobase + offset mnemonic register name default type 00h?01h tco_rld tco timer reload and current value 0000h r/w 02h tco_dat_in tco data in 00h r/w 03h tco_dat_out tco data out 00h r/w 04h?05h tco1_sts tco1 status 0000h r/wc, ro 06h?07h tco2_sts tco2 status 0000h r/w, r/wc 08h?09h tco1_cnt tco1 control 0000h r/w, r/w (special), r/wc 0ah?0bh tco2_cnt tco2 control 0008h r/w 0ch?0dh tco_message1, tco_message2 tco message 1 and 2 00h r/w 0eh tco_wdcnt watchdog control 00h r/w 0fh ? reserved ? ? 10h sw_irq_gen software irq generation 11h r/w 11h ? reserved ? ? 12h?13h tco_tmr tco timer initial value 0004h r/w 14h?1fh ? reserved ? ? bit description 15:10 reserved 9:0 tco timer value ? r/w. reading this register will return the current count of the tco timer. writing any value to this register will reload the timer to prevent the timeout.
424 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.9.2 tco_dat_in?tco data in register i/o address: tcobase +02h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 10.9.3 tco_dat_out?tco data out register i/o address: tcobase +03h attribute: r/w default value: 00h size: 8-bit lockable: no power well: core 10.9.4 tco1_sts?tco1 status register i/o address: tcobase + 04h attribute: r/wc, ro default value: 0000h size: 16-bit lockable: no power well: core (except bit 7, in rtc) bit description 7:0 tco data in value ? r/w. this data register field is used for passing commands from the os to the smi handler. writes to this register will cause an smi and set the sw_tco_smi bit in the tco1_sts register (d31:f0:04h). bit description 7:0 tco data out value ? r/w. this data register field is used for passing commands from the smi handler to the os. writes to this register will set the tco_int_sts bit in the tco_sts register. it will also cause an interrupt, as selected by the tco_int_sel bits. bit description 15:13 reserved 12 dmiserr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich6 received a dmi special cycle message vi a dmi indicating that it wants to cause an serr#. the software must read the (g)mch to determine the reason for the serr#. 11 reserved 10 dmismi_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich6 received a dmi special cycle message via dmi indicating that it wants to cause an smi. the software must read the (g)mch to determine the reason for the smi. 9 dmisci_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich6 received a dmi special cycle message via dm i indicating that it wants to cause an sci. the software must read the (g)mch to determine the reason for the sci.
intel ? i/o controller hub 6 (ich6) family datasheet 425 lpc interface bridge registers (d31:f0) 8 bioswr_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = ich6 sets this bit and generates and smi# to indicate an illegal attempt to write to the bios. this occurs when either: a) the bioswp bit is changed from 0 to 1 and the bld bit is also set, or b) any write is attempted to the bios and the bioswp bit is also set. note: on write cycles attempted to the 4 mb lowe r alias to the bios space, the bioswr_sts will not be set. 7 newcentury_sts ? r/wc. this bit is in the rtc well. 0 = cleared by writing a 1 to the bit position or by rtcrst# going active. 1 = this bit is set when the year byte (rtc i/o sp ace, index offset 09h) rolls over from 99 to 00. setting this bit will cause an smi# (but not a wake event). note: the newcentury_sts bit is not valid when t he rtc battery is first installed (or when rtc power has not been maintained). software can determine if rtc power has not been maintained by checking the rtc_pwr_sts bit (d31:f0:a4h, bit 2), or by other means (such as a checksum on rtc ram). if rt c power is determined to have not been maintained, bios should set the time to a legal value and then clear the newcentury_sts bit. the newcentury_sts bit may take up to 3 rtc clocks for the bit to be cleared after a 1 is written to the bit to clear it. after writing a 1 to this bit, software should not exit the smi handler until verifying that the bit has actually been cleared. th is will ensure that the smi is not re-entered. 6:4 reserved 3 timeout ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by ich6 to indicate that the smi was caused by the tco timer reaching 0. 2 tco_int_sts ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = smi handler caused the interrupt by writi ng to the tco_dat_out register (tcobase + 03h). 1 sw_tco_smi ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = software caused an smi# by writing to the tco_dat_in register (tcobase + 02h). 0 nmi2smi_sts ? ro. 0 = cleared by clearing the associated nmi status bit. 1 = set by the ich6 when an smi# occurs becaus e an event occurred that would otherwise have caused an nmi (because nmi2smi_en is set). bit description
426 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.9.5 tco2_sts?tco2 status register i/o address: tcobase +06h attribute: r/w, r/wc default value: 0000h size: 16-bit lockable: no power well: resume (except bit 0, in rtc) bit description 15:5 reserved 4 smlink slave smi status (smlink_slv_smi_sts) ? r/wc. allow the software to go directly into pre-determined sleep state. this avoids race c onditions. software clears this bit by writing a 1 to it. 0 = the bit is reset by rsmrst#, but not due to the pci reset associated with exit from s3?s5 states. 1 = ich6 sets this bit to 1 when it receives t he smi message on the smlink's slave interface. 3reserved 2 boot_sts ? r/wc. 0 = cleared by ich6 based on rsmrst# or by software writing a 1 to this bit. note that software should first clear the second_to_sts bit befor e writing a 1 to clear the boot_sts bit. 1 = set to 1 when the second_to_sts bit goes from 0 to 1 and the processor has not fetched the first instruction. if rebooting due to a second tco timer timeout, and if the boot_sts bit is set, the ich6 will reboot using the ?safe? multiplier (1111). this allows the system to recover from a processor fr equency multiplier that is too high, and allows the bios to check the boot_sts bit at boot. if the bit is set and the frequency multiplier is 1111, then the bios knows that the processor has been programmed to an illegal multiplier. 1 second_to_sts ? r/wc. 0 = software clears this bit by writing a 1 to it, or by a rsmrst#. 1 = ich6 sets this bit to 1 to indicate that the timeout bit had been (or is currently) set and a second timeout occurred before the tco_rld regist er was written. if this bit is set and the no_reboot configuration bit is 0, then the ich6 will reboot the system after the second timeout. the reboot is done by asserting pltrst#. 0 intruder detect (intrd_det) ? r/wc. 0 = software clears this bit by writing a 1 to it, or by rtcrst# assertion. 1 = set by ich6 to indicate that an intrusion was dete cted. this bit is set even if the system is in g3 state. notes: 1. this bit has a recovery time. after writing a 1 to this bit position (to clear it), the bit may be read back as a 1 for up 65 microseconds before it is r ead as a 0. software must be aware of this recovery time when reading this bit after clearing it. 2. if the intruder# signal is active when the soft ware attempts to clear the intrd_det bit, the bit will remain as a 1, and the smi# will be generated again immediately. the smi handler can clear the intrd_sel bits (tcobase + 0ah, bits 2:1), to avoid further smis. however, if the intruder# signals goes inactive and then active again, there will not be further smi?s (because the intrd_sel bits would select that no smi# be generated). 3. if the intruder# signal goes inactive some poi nt after the intrd_det bit is written as a 1, then the intrd_det signal will go to a 0 when intruder# input signal goes inactive. note that this is slightly different than a classic sticky bit, since most st icky bits would remain active indefinitely when the signal goes active and would immediately go i nactive when a 1 is written to the bit
intel ? i/o controller hub 6 (ich6) family datasheet 427 lpc interface bridge registers (d31:f0) 10.9.6 tco1_cnt?tco 1 control register i/o address: tcobase +08h attribut e: r/w, r/w (special), r/wc default value: 0000h size: 16-bit lockable: no power well: core bit description 15:13 reserved 12 tco_lock ? r/w (special). when set to 1, this bit prevents writes from changing the tco_en bit (in offset 30h of power management i/o space). once this bit is set to 1, it can not be cleared by software writing a 0 to this bit location. a core-well reset is required to change this bit from 1 to 0. this bit defaults to 0. 11 tco timer halt (tco_tmr_hlt) ? r/w. 0 = the tco timer is enabled to count. 1 = the tco timer will halt. it will not count, and thus cannot reach a value that will cause an smi# or set the second_to_sts bit. when set, this bi t will prevent rebooting and prevent alert on lan event messages from being transmitted on t he smlink (but not alert on lan* heartbeat messages). 10 send_now ? r/w (special). 0 = the ich6 will clear this bit when it has comp leted sending the message. software must not set this bit to 1 again until the ich6 has set it back to 0. 1 = writing a 1 to this bit will cause the ich6 to send an alert on lan event message over the smlink interface, with t he software event bit set. setting the send_now bit causes the ich6 integr ated lan controller to reset, which can have unpredictable side-effects. unless software protects against these side effects, software should not attempt to set this bit. 9 nmi2smi_en ? r/w. 0 = normal nmi functionality. 1 = forces all nmis to instead cause smis. th e functionality of this bit is dependent upon the settings of the nmi_en bit and the gbl_smi_ en bit as detailed in the following table: 8 nmi_now ? r/wc. 0 = software clears this bit by writing a 1 to it. t he nmi handler is expected to clear this bit. another nmi will not be generated until the bit is cleared. 1 = writing a 1 to this bit causes an nmi. this allows the bios or smi handler to force an entry to the nmi handler. 7:0 reserved nmi_en gbl_smi_en description 0b 0b no smi# at all because gbl_smi_en = 0 0b 1b smi# will be caused due to nmi events 1b 0b no smi# at all because gbl_smi_en = 0 1b 1b no smi# due to nmi because nmi_en = 1
428 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.9.7 tco2_cnt?tco2 control register i/o address: tcobase +0ah attribute: r/w default value: 0008h size: 16-bit lockable: no power well: resume 10.9.8 tco_message1 and tco_message2 registers i/o address: tcobase +0ch (message 1) attribute: r/w tcobase +0dh (message 2) default value: 00h size: 8-bit lockable: no power well: resume bit description 15:6 reserved 5:4 os_policy ? r/w. os-based software writes to these bits to select the policy that the bios will use after the platform resets due the wdt. the following convention is recommended for the bios and os: 00 = boot normally 01 = shut down 10 = don?t load os. hold in pre-boot state and use lan to determine next step 11 = reserved note: these are just scratchpad bits. they should not be reset when the tco logic resets the platform due to watchdog timer. 3 gpi11_alert_disable ? r/w. at reset (via rsmrst# asserted) this bit is set and gpi[11] alerts are disabled. 0 = enable. 1 = disable gpi[11]/smbalert# as an alert s ource for the heartbeats and the smbus slave. 2:1 intrd_sel ? r/w. this field selects the action to take if the intruder# signal goes active. 00 = no interrupt or smi# 01 = interrupt (as selected by tco_int_sel). 10 = smi 11 = reserved 0reserved bit description 7:0 tco_message[ n ] ? r/w. the value written into this regi ster will be sent out via the smlink interface in the message field of the alert on la n message. bios can write to this register to indicate its boot progress which can be monitored externally
intel ? i/o controller hub 6 (ich6) family datasheet 429 lpc interface bridge registers (d31:f0) 10.9.9 tco_wdcnt?tco watchdog control register offset address: tcobase + 0eh attribute: r/w default value: 00h size: 8 bits power well: resume 10.9.10 sw_irq_gen?software irq generation register offset address: tcobase + 10h attribute: r/w default value: 11h size: 8 bits power well: core 10.9.11 tco_tmr?tco timer initial value register i/o address: tcobase +12h attribute: r/w default value: 0004h size: 16-bit lockable: no power well: core bit description 7:0 watchdog status (wdstatus) ? r/w. the value written to this regist er will be sent in the alert on lan message on the smlink interface. it can be used by the bios or system management software to indicate more details on the boot progress. this register will be reset to the default of 00h based on rsmrst# (but not pci reset). bit description 7:2 reserved 1 irq12_cause ? r/w. the state of this bit is logically anded with the irq12 signal as received by the ich6?s serirq logic. this bit must be a 1 ( default) if the ich6 is expected to receive irq12 assertions from a serirq device. 0 irq1_cause ? r/w. the state of this bit is logically anded with the irq1 signal as received by the ich6?s serirq logic. this bit must be a 1 ( default) if the ich6 is expected to receive irq1 assertions from a serirq device. bit description 15:10 reserved 9:0 tco timer initial value ? r/w. value that is loaded into the timer each time the tco_rld register is written. values of 0000h or 0001h will be i gnored and should not be attempted. the timer is clocked at approximately 0.6 seconds, and thus allows timeouts ranging from 1.2 second to 613.8 seconds. note: the timer has an error of 1 tick (0.6s). the tco timer will only count down in the s0 state.
430 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.10 general purpose i/o registers (d31:f0) the control for the general purpose i/o signals is handled through a separate 64-byte i/o space. the base offset for this space is se lected by the gpiobase register. 10.10.1 gpio register i/o address map table 10-13. registers to control gpio address map gpiobase + offset mnemonic register name default access general registers 00?03h gpio_use_sel gpio use select 1ba83180h r/w 04?07h gp_io_sel gpio input/output select e400 ffffh r/w 08?0bh ? reserved ? ? 0c?0fh gp_lvl gpio level for input or output ff3f0000h r/w 10?13h ? reserved ? ? output control registers 14?17h ? reserved ? ? 18?1bh gpo_blink gpio blink enable 00040000h r/w 1c?1fh ? reserved ? ? input control registers 20?2bh ? reserved ? ? 2c?2fh gpi_inv gpio signal invert 00000000h r/w 30?33h gpio_use_sel2 gpio use select 2 [63:32] 00000006h r/w 34?37h gp_io_sel2 gpio input/output select 2 [63:32] 00000300h r/w 38?3bh gp_lvl2 gpio level for input or output 2 [63:32] 00030207h r/w
intel ? i/o controller hub 6 (ich6) family datasheet 431 lpc interface bridge registers (d31:f0) 10.10.2 gpio_use_sel?gpio use select register offset address: gpiobase + 00h attribute: r/w default value: 1ba83180h size: 32-bit lockable: no power well: core for 0:7, 12, 16:21, 23, 26, 29:31 resume for 8:11, 13:15, 25, 27, 28 10.10.3 gp_io_sel?gpio input/output select register offset address: gpio base +04h attribute: r/w default value: e400ffffh size: 32-bit lockable: no power well: resume bit description 31:29 26, 15:14, 11:9, 5:0 gpio_use_sel[31:29, 26, 15:14, 11:9, 5:0] ? r/w. each bit in this register enables the corresponding gpio (if it exists) to be used as a gpio, rather than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. notes: 1. the following bit is not implemented because there is no corresponding gpio: 22. 2. the following bits are always 1 because they are unmultiplexed: 7, 8, 12:13, 19, 21, 23:25, 27:28 3. the following bits are not implemented bec ause they are determined by the desktop/mobile configuration: 6, 18, 20 4. bit 16 is not implemented because gpo selectio n will be controlled by bit 0 (req/gnt pair) 5. bit 17 is not implemented because gpo selectio n will be controlled by bit 1 (req/gnt pair) 6. if gpio[n] does not exist, then the bit in this regi ster will always read as 0 and writes will have no effect. 7. after a full reset (rsmrst#) all multiplexed si gnals in the resume and core wells are configured as their native function rather than as a gpio. af ter just a pltrst#, the gpio in the core well are configured as their native function. 8. when configured to gpio mode, the multiplexing logic should present the inactive state to native logic that uses the pin as an input. bit description 31:29 always 1. these gpis are fixed as inputs. 28:27 gp_io_sel[28:27] ? r/w. when set to a 1, the corr esponding gpio signal (if enabled in the gpio_use_sel register) is programmed as an input. when set to 0, the gpio signal is programmed as an output. 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input. 26 always 1. this gpi is fixed as an input. 25:24 gp_io_sel[25:24] ? r/w. when set to a 1, the corr esponding gpio signal (if enabled in the gpio_use_sel register) is programmed as an input. when set to 0, the gpio signal is programmed as an output. 0 = output. the corresponding gpio signal is an output. 1 = input. the corresponding gpio signal is an input. 21:16 always 0. the gpos are fixed as outputs. 15:0 always 1. these gpis are fixed as inputs.
432 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.10.4 gp_lvl?gpio level for input or output register offset address: gpiob ase +0ch attribute: r/w default value: ff3f0000h size: 32-bit lockable: no power well: see bit descriptions bit description 31:29 gp_lvl[31:29] ? r/w. these bits correspond to input-onl y gpi in the core well. the corresponding gp_lvl bit reflects the state of the i nput signal (1 = high, 0 = low). writes to these bits will have no effect. since these bits correspond to gpi that are in t he core well, these bits will be reset by pltrst#. 0 = low 1 = high 28:27 gp_lvl[28:27] ? r/w. if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the correspondi ng gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. if gpio[n] is programmed as an input, then the co rresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low.). writes will have no effect. since these bits correspond to gpio that are in the resume well, these bits will be reset by rsmrst# and also by a write to the cf9h register. 0 = low 1 = high 26 gp_lvl[26] ? r/w. this bit corresponds to an input- only gpi in the core well. the corresponding gp_lvl bit reflects the state of the inpu t signal (1 = high, 0 = lo w). writes to this bit will have no effect. since this bit correspond to a gpi that is in th e core well, this bit will be reset by pltrst#. 0 = low 1 = high 25:24 gp_lvl[25:24] ? r/w. if gpio[n] is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the correspondi ng gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. 1 = high, 0 = low. if gpio[n] is programmed as an input, then the co rresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low.). writes will have no effect. since these bits correspond to gpio that are in the resume well, these bits will be reset by rsmrst# and also by a write to the cf9h register. 0 = low 1 = high 23:16 gp_lvl[23:16] ? r/w. these bits can be updated by software to drive a high or low value on the output pin. these bits correspond to gpio that ar e in the core well, and will be reset to their default values by pltrst#. 0 = low 1 = high 15:0 reserved. (these bits are not needed, as the level of general purpose inputs can be read through the registers in the acpi i/o space).
intel ? i/o controller hub 6 (ich6) family datasheet 433 lpc interface bridge registers (d31:f0) 10.10.5 gpo_blink?gpo blink enable register offset address: gpio base +18h attribute: r/w default value: 0004 0000h size: 32-bit lockable: no power well: see bit description note: (desktop only) gpio18 will blink by default immediately after reset. this signal could be connected to an led to indicate a failed boot (by programming bi os to clear gp_blink18 after successful post). bit description 28:27, 25 gp_blink[28:27, 25] ? r/w. the setting of this bit has no ef fect if the corresponding gpio signal is programmed as an input. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times have approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. the value of the corresponding gp_lvl bit remains unchanged during the blink process, and does not effect the blink in any way. the gp_lvl bit is not altered when programmed to blink. it will remain at its previous value. these bits correspond to gpio in the resume well . these bits revert to the default value based on rsmrst# or a write to the cf9h register (but not just on pltrst#). 19:18 (desktop only) gp_blink[n] ? r/w. the setting of these bits will have no effect if the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the core well, and will be reset to their default values by pltrst#. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times are approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set. 19 (mobile only) gp_blink[n] ? r/w. the setting of these bits will have no effect if the corresponding gpio is programmed as an input. these bits correspond to gpio that are in the core well, and will be reset to their default values by pltrst#. 0 = the corresponding gpio will function normally. 1 = if the corresponding gpio is programmed as an output, the output signal will blink at a rate of approximately once per second. the high and low times are approximately 0.5 seconds each. the gp_lvl bit is not altered when this bit is set.
434 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.10.6 gpi_inv?gpio signal invert register offset address: gpiob ase +2ch attribute: r/w default value: 00000000h size: 32-bit lockable: no power well: see bit description bit description 31:16 reserved 15:13 gp_inv[n] ? r/w. these bits are used to allow both acti ve-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, t he input signal must be active for at least two pci clocks to ensure detection by the ich6. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits has no effect if the corresponding gpio is programmed as an output. these bits corr espond to gpi that are in the resume well, and will be reset to their default values by rsmr st# or by a write to the cf9h register. 0 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be low. 12 gp_inv[n] ? r/w. these bits are used to allow both acti ve-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, t he input signal must be active for at least two pci clocks to ensure detection by the ic h6. these bits correspond to gpi that are in the core well, and will be reset to their default values by pltrst#. 0 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be low. 11:8 gp_inv[n] ? r/w. these bits are used to allow both acti ve-low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, t he input signal must be active for at least two pci clocks to ensure detection by the ich6. in the s3, s4 or s5 states the input signal must be active for at least 2 rtc clocks to ensure detection. the setting of these bits has no effect if the corresponding gpio is programmed as an output. these bits corr espond to gpi that are in the resume well, and will be reset to their default values by rsmr st# or by a write to the cf9h register. 0 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be low. 7:0 gp_inv[n] ? r/w. these bits are used to allow both active -low and active-high inputs to cause smi# or sci. note that in the s0 or s1 state, the input signal must be active for at least two pci clocks to ensure detection by the ich6. the setti ng of these bits will have no effect if the corresponding gpio is programmed as an output. these bits correspond to gpi that are in the core well, and will be reset to their default values by pltrst#. 0 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be high. 1 = the corresponding gpi_sts bit is set when the i ch6 detects the state of the input pin to be low.
intel ? i/o controller hub 6 (ich6) family datasheet 435 lpc interface bridge registers (d31:f0) 10.10.7 gpio_use_sel2?gpio use select 2 register[63:32] offset address: gpio base +30h attribute: r/w default value: 00000006h size: 32-bit lockable: no power well: processor i/o for 17, core for 16:0 10.10.8 gp_io_sel2?gpio input/ output select 2 register[63:32] offset address: gpio base +34h attribute: r/w default value: 00000300h size: 32-bit lockable: no power well: core bit description 17, 9:8 gpio_use_sel2[49, 41:40] ? r/w. each bit in this register enables the corresponding gpio (if it exists) to be used as a gpio, ra ther than for the native function. 0 = signal used as native function. 1 = signal used as a gpio. after a full reset (rsmrst#) all multiplexed signals in the resume and core wells are configured as a gpio rather than as their native function. after just a pltrst#, the gpio in the core well are configured as gpio. notes: 1. the following bits are not implemented becaus e there is no corresponding gpio: 3:7, 10:15, 18:31. 2. the following bits are always 1 because they are unmultiplexed: 1:2 3. bit 16 is not implemented because the gpio select ion will be controlled by bit 8 (req/gnt pair) 4. if gpio[n] does not exist, then the bit in this regi ster will always read as 0 and writes will have no effect. 5. the following bits are not implemented bec ause they are determined by the desktop/mobile configuration: 0 bit description 31:18 always 0. no corresponding gpio. 17:16 always 0. outputs. 15:10 always 0. no corresponding gpio. 9:8 always 0. inputs. 7:3 always 0. no corresponding gpio. 2:0 gp_io_sel2[34:32] ? r/w. 0 = gpio signal is programmed as an output. 1 = corresponding gpio signal (if enabled in the gp io_use_sel2 register) is programmed as an input.
436 intel ? i/o controller hub 6 (i ch6) family datasheet lpc interface bridge registers (d31:f0) 10.10.9 gp_lvl2?gpio level for in put or output 2 register[63:32] offset address: gpiob ase +38h attribute: r/w default value: 00030207h size: 32-bit lockable: no power well: see below bit description 31:18 reserved. read-only 0 17:16 gp_lvl[49:48] ? r/w. the corresponding gp_lvl[n] bit can be updated by software to drive a high or low value on the output pin. since these bi ts correspond to gpio that are in the processor i/ o and core well, respectively, thes e bits will be reset by pltrst#. 0 = low 1 = high 15:10 reserved. read-only 0 9:8 gp_lvl[41:40] ? r/w. the corresponding gp_lvl[n] bit re flects the state of the input signal. writes will have no effect. since t hese bits correspond to gpio that are in the core well, these bits will be reset by pltrst#. 0 = low 1 = high 7:3 reserved. read-only 0 2:0 gp_lvl[34:32] ? r/w. if gpion is programmed to be an output (via the corresponding bit in the gp_io_sel register), then the corresponding gp_lvl [n] bit can be updated by software to drive a high or low value on the output pin. if gpion is programmed as an input, then the corresponding gp_lvl bit reflects the state of the input signal (1 = high, 0 = low). writes will have no effect. 0 = low 1 = high since these bits correspond to gpio that are in th e core well, these bits will be reset by pltrst#.
intel ? i/o controller hub 6 (ich6) family datasheet 437 ide controller registers (d31:f1) 11 ide controller registers (d31:f1) 11.1 pci configuration registers (ide?d31:f1) note: address locations that are not shown should be treated as reserved (see section 6.2 for details). all of the ide registers are in the core we ll. none of the registers can be locked. note: the ich6 ide controller is not arbitrated as a pci device; therefore, it does not need a master latency table 11-1. ide controller pci register address map (ide-d31:f1) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 266fh ro 04?05h pcicmd pci command 00h r/w, ro 06?07h pcists pci status 0280h r/w, ro 08h rid revision identification see register description. ro 09h pi programming interface 8ah r/w, ro 0ah scc sub class code 01h ro 0bh bcc base class code 01h ro 0ch cls cache line size 00h ro 0dh pmlt primary master latency timer 00h ro 10?13h pcmd_bar primary command block base address 00000001h r/w, ro 14?17h pcnl_bar primary control block base address 00000001h r/w, ro 18?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1c?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20?23h bm_base bus master base address 00000001h r/w, ro 2c?2dh ide_svid subsystem vendor id 00h r/wo 2e?2fh ide_sid subsystem id 0000h r/wo 3c intr_ln interrupt line see register description. r/w 3d intr_pn interrupt pin 01h ro 40?41h ide_timp primary ide timing 0000h r/w 42?43h ide_tims secondary ide timing 0000h r/w 44h slv_idetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4a?4bh sdma_tim synchronous dma timing 0000h r/w 54h ide_config ide i/o configuration 00000000h r/w c0h atc apm trapping control 00h r/w c4h ats apm trapping status 00h r/wc
438 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) timer. 11.1.1 vid?vendor identification register (ide?d31:f1) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16-bit lockable: no power well: core 11.1.2 did?device identifi cation register (ide?d31:f1) offset address: 02 ? 03h attribute: ro default value: 266fh size: 16-bit lockable: no power well: core bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the ich6 ide controller.
intel ? i/o controller hub 6 (ich6) family datasheet 439 ide controller registers (d31:f1) 11.1.3 pcicmd?pci command register (ide?d31:f1) address offset: 04h ? 05h attribute: ro, r/w default value: 00h size: 16 bits bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0 = enables the ide controller to assert in ta# (native mode) or irq14/15 (legacy mode). 1 = disable. the interrupt will be de-asserted. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? ro. reserved as 0. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle enable (s ce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. controls the ich6?s ability to act as a pci master for ide bus master transfers. 1 memory space enable (mse) ? r/w. 0 = disables access. 1 = enables access to the ide expansion memory range. the exbar register (offset 24h) must be programmed before this bit is set. note: bios should set this bit to a 1. 0 i/o space enable (iose) ? r/w. this bit controls acce ss to the i/o space registers. 0 = disables access to the legacy or native ide por ts (both primary and secondary) as well as the bus master i/o registers. 1 = enable. note that the base address regi ster for the bus master registers should be programmed before this bit is set. notes: 1. separate bits are provided (ide decode enabl e, in the ide timing register) to independently disable the primary or secondary i/o spaces. 2. when this bit is 0 and the ide controller is in native mode, the interrupt pin register (see section 11.1.19 ) will be masked (the interrupt will not be asserted). if an interrupt occurs while the masking is in pl ace and the interrupt is still active when the masking ends, the interrupt w ill be allowed to be asserted.
440 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.1.4 pcists ? pci stat us register (ide?d31:f1) address offset: 06 ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. reserved as 0. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated by bus master ide interface function. 1 = bus master ide interface function, as a master, generated a master abort. 12 reserved as 0 ? ro. 11 reserved as 0 ? ro. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; however, the ich6 does not have a real devsel# signal as sociated with the ide unit, so these bits have no effect. 8 data parity error detected (dped) ? ro. reserved as 0. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66mhz capable (66mhz_cap) ? ro. reserved as 0. 4 reserved 3 interrupt status (ints) ? ro . this bit is independent of the state of the interrupt disable bit in the command register. 0 = interrupt is cleared. 1 = interrupt/msi is asserted. note: this bit will read ?1? after power on reset w hen no parallel ata drive is attached. this is the intended behavior. 2:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 441 ide controller registers (d31:f1) 11.1.5 rid?revision identifi cation register (ide?d31:f1) offset address: 08h attribute: ro default value: see bit description size: 8 bits 11.1.6 pi?programming inter face register (ide?d31:f1) address offset: 09h attribute: ro, r/w default value: 8ah size: 8 bits 11.1.7 scc?sub class code register (ide?d31:f1) address offset: 0ah attribute: ro default value: 01h size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 7 this read-only bit is a 1 to indicate that the ich6 supports bus master operation 6:4 reserved. hardwired to 000b. 3 sop_mode_cap ? ro. this read-only bit is a 1 to indica te that the secondary controller supports both legacy and native modes. 2 sop_mode_sel ? r/w. this read/write bit determines the mode that the secondary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode 1 pop_mode_cap ? ro. this read-only bit is a 1 to indica te that the primary controller supports both legacy and native modes. 0 pop_mode_sel ? r/w. this read/write bits determines the mode that the primary ide channel is operating in. 0 = legacy-pci mode (default) 1 = native-pci mode bit description 7:0 sub class code (scc) ? ro. 01h = ide device, in the context of a mass storage device.
442 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.1.8 bcc?base class code register (ide?d31:f1) address offset: 0bh attribute: ro default value: 01h size: 8 bits 11.1.9 cls?cache line size register (ide?d31:f1) address offset: 0ch attribute: ro default value: 00h size: 8 bits 11.1.10 pmlt?primary master latency timer register (ide?d31:f1) address offset: 0dh attribute: ro default value: 00h size: 8 bits 11.1.11 pcmd_bar?primary command block base address register (ide?d31:f1) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native m ode for the primary controller?s command block. bit description 7:0 base class code (bcc) ? ro. 01 = mass storage device bit description 7:0 cache line size (cls) ? ro. 00h = hardwired. the ide controller is implement ed internally so this register has no meaning. bit description 7:0 master latency timer count (mltc) ? ro. 00h = hardwired. the ide controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o sp ace (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space.
intel ? i/o controller hub 6 (ich6) family datasheet 443 ide controller registers (d31:f1) 11.1.12 pcnl_bar?primary co ntrol block base address register (ide?d31:f1) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native m ode for the primary controller?s command block. 11.1.13 scmd_bar?secondary command block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native m ode for the secondary controller?s command block. 11.1.14 scnl_bar?secondary control block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native m ode for the secondary controller?s command block. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o sp ace (4 consecutiv e i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indica ting a request for i/o space. bit description 31:16 reserved 15:3 base address ? r/w. base address of the i/o sp ace (8 consecutiv e i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indica ting a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. base address of the i/o sp ace (4 consecutiv e i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indica ting a request for i/o space.
444 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.1.15 bm_base ? bus master base address register (ide?d31:f1) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface functi on uses base address register 5 to request a 16-byte i/o space to provide a software interface to the bus ma ster functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. 11.1.16 ide_svid ? subsystem vendor identification (ide?d31:f1) address offset: 2ch ? 2dh attribute: r/wo default value: 00h size: 16 bits lockable: no power well: core 11.1.17 ide_sid ? subsystem identification register (ide?d31:f1) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base addre ss of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 15:0 subsystem vendor id (svid) ? r/wo. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to distinguish subsystems from each other. software (bios) sets the value in this regist er. after that, the value can be read, but subsequent writes to this register have no ef fect. the value written to this r egister will also be readable via the corresponding svid registers for th e usb#1, usb#2, and smbus functions. bit description 15:0 subsystem id (sid) ? r/wo. the sid register, in combinati on with the svid register, enables the operating system (os) to distinguis h subsystems from each other. software (bios) sets the value in this register. after that, the value can be read, but subsequent writes to this register have no effect. the value written to this register will also be re adable via the corresponding sid registers for the usb#1, usb#2, and smbus functions.
intel ? i/o controller hub 6 (ich6) family datasheet 445 ide controller registers (d31:f1) 11.1.18 intr_ln?interrupt li ne register (ide?d31:f1) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 11.1.19 intr_pn?interrupt pin register (ide?d31:f1) address offset: 3dh attribute: ro default value: see register description size: 8 bits 11.1.20 ide_timp ? ide primary timing registe r (ide?d31:f1) address offset: 40 ? 41h attribute: r/w default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. bit description 7:0 interrupt line (int_ln) ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this field reflects the value of d31ip.pip (chipset configuration registers:offset 3100h:bits 7:4). bit description 15 ide decode enable (ide) ? r/w. the ide i/o space enable bit (d31:f1:04h, bit 0) in the command register must be set in order for this bit to have any effect. 0 = disable. 1 = enables the ich6 to decode the comm and (1f0?1f7h) and control (3f6h) blocks. this bit also effects the memory decode range for ide expansion. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and use the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits det ermine the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits det ermines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock
446 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable. 1 = enable the fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive. 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = when this bit = 1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time . when this bit = 1 and bit 14 = 1, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will use compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description
intel ? i/o controller hub 6 (ich6) family datasheet 447 ide controller registers (d31:f1) 11.1.21 ide_tims ? ide secondary timing register (ide?d31:f1) address offset: 42 ? 43h attribute: r/w default value: 0000h size: 16 bits 11.1.22 slv_idetim?slave (dri ve 1) ide timing register (ide?d31:f1) address offset: 44h attribute: r/w default value: 00h size: 8 bits bit description 15 ide decode enable (ide) ? r/w. this bit enables/disables the secondary decode. the ide i/o space enable bit (d31:f1:04h, bit 0) in the command register must be set in order for this bit to have any effect. additionally, separ ate configuration bits are provid ed (in the ide i/o configuration register) to individually disable the secondary id e interface signals, even if the ide decode enable bit is set. 0 = disable. 1 = enables the ich6 to decode the associ ated command blocks (170?177h) and control block (376h). accesses to these ranges return 00h, as the secondary channel is not implemented. 14:12 no operation (nop) ? r/w. these bits are read/write for l egacy software compatibility, but have no functionality in the ich6 sinc e a secondary channel does not exist. 11 reserved 10:0 no operation (nop) ? r/w. these bits are read/write for l egacy software compatibility, but have no functionality in the ich6 sinc e a secondary channel does not exist. bit description 7:4 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# assertion and the first io rdy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks
448 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.1.23 sdma_cnt?synchronous dma control register (ide?d31:f1) address offset: 48h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved 3:2 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1. 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0.
intel ? i/o controller hub 6 (ich6) family datasheet 449 ide controller registers (d31:f1) 11.1.24 sdma_tim?synchronous dma timing register (ide?d31:f1) address offset: 4a ? 4bh attribute: r/w default value: 0000h size: 16 bits note: for fast_pcb1 = 1 (133 mhz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to section 5.16.4 for details. bit description 15:14 reserved 13:12 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 11:10 reserved 9:8 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved
450 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.1.25 ide_config?ide i/o configuration register (ide?d31:f1) address offset: 54h attribute: r/w default value: 00000000h size: 32 bits bit description 31:24 reserved 23:20 miscellaneous scratchpad (ms) ? r/w. previously defined as a sc ratchpad bit to indicate to a driver that ata-100 is supported. this is not used by software as all they needed to know was located in bits 7:4. see the definition of those bits. 19:18 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 17:16 sig_mode ? r/w. these bits are used to control mode of the ide signal pins for swap bay support. if the prs bit (chipset configuration registers:offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15:14 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits to enable/disable ultra ata/ 100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary sl ave drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits to enable/disable ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary mast er drive (overrides bit 0 in this register). 11:8 reserved 7 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 6 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 5 primary slave channel cable reporting ? r/w. bios should program this bit to tell the ide driver which cable is plugged into the channel. 0 = 40 conductor cable is present. 1 = 80 conductor cable is present. 4 primary master channel cable reporting ? r/w. same description as bit 5 3:2 no operation (nop) ? r/w. these bits are read/write for legacy software compatibility, but have no functionality in the ich6. 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock fo r ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock fo r ultra ata timings. 1 = 66 mhz base clock for ultra ata timings
intel ? i/o controller hub 6 (ich6) family datasheet 451 ide controller registers (d31:f1) 11.1.26 atc?apm trapping co ntrol register (ide?d31:f1) address offset: c0h attribute: r/w default value: 00h size: 8 bits 11.1.27 ats?apm trapping status register (ide?d31:f1) address offset: c4h attribute: r/wc default value: 00h size: 8 bits 11.2 bus master ide i/o registers (ide?d31:f1) the bus master ide function uses 16 bytes of i/o space, allocated via the bmiba register, located in device 31:function 1 configuration space, offs et 20h. all bus master ide i/o space registers can be accessed as byte, word, or dword quantities. reading reserved bits returns an indeterminate, inconsistent value, and writes to re served bits have no affect (but should not be attempted). the description of the i/o registers is shown in table 11-2 . bit description 7:2 reserved 1 slave trap (pst) ? r/w. this bit enables trapping and sm i# assertion on legac y i/o accesses to 1f0h?1f7h and 3f6h. the active device must be the sl ave device for the trap and/or smi# to occur. 0 master trap (pmt) ? r/w. this bit enables trapping and smi# assertion on legacy i/o accesses to 1f0h?1f7h and 3f6h. the active device must be ma ster device for the trap and/or smi# to occur. bit description 7:2 reserved 1 slave trap status (psts) ? r/wc. this bit indicates that a trap occurred to the slave device 0 master trap status (pmts) ? r/wc. this bit indicates that a trap occurred to the master device table 11-2. bus master ide i/o registers bmibase + offset mnemonic register name default type 00 bmicp bus master ide command primary 00h r/w 01 ? reserved 00h ro 02 bmisp bus master ide status primary 00h r/wc 03 ? reserved 00h ro 04?07 bmidp bus master ide descriptor table pointer primary xxxxxxxxh r/w
452 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1) 11.2.1 bmicp?bus master ide command register (ide?d31:f1) address offset: bmibase + 00h attribute: r/w default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (rwc) ? r/w. this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus ma ster operation is stil l active (i.e., the bus master ide active bit (bmibase + 02h, bit 0) of t he bus master ide status register for that ide channel is set) and the drive has not yet finis hed its data transfer (the interrupt bit (bmibase + 02h, bit 2) in the bus master ide status register for that ide channel is not set), the bus master command is said to be aborted and data transferr ed from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controll er. bus master operation does not actually start unless the bus master enable bit (d31:f1:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detec ted changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically.
intel ? i/o controller hub 6 (ich6) family datasheet 453 ide controller registers (d31:f1) 11.2.2 bmisp?bus master ide status register (ide?d31:f1) address offset: bmib ase + 02h attribute: r/wc default value: 00h size: 8 bits 11.2.3 bmidp?bus master ide desc riptor table pointer register (ide?d31:f1) address offset: bmibase + 04h attribute: r/w default value: all bits undefined size: 32 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = when this bit is cleared by so ftware, the interrupt is cleared. 1 = set when the host controller completes execution of a prd that has its interrupt bit (bit 2 of this register) set. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or devic e driver) to indicate that drive 1 for this channel is capable of dma transfers, and that t he controller has been initialized for optimum performance. the ich6 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (bios or devic e driver) to indicate that drive 0 for this channel is capable of dma transfers, and that t he controller has been initialized for optimum performance. the ich6 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. software can use this bit to determine if an ide device has asserted its interrupt line (ideirq). 0 = software clears this bit by writi ng a 1 to it. if this bit is cleared while the interrupt is still active, this bit will remain clear until another asse rtion edge is detected on the interrupt line. 1 = set by the rising edge of the ide interrupt line, regardless of whether or not the interrupt is masked in the 8259 or the internal i/o apic. when th is bit is read as 1, all data transferred from the drive is visible in system memory. 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich6 when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the ich6 when the start bit is cleared in the command register. when this bit is read as 0, all data transferred from the drive during the previous bus master command is visi ble in system memory, unless the bus master command was aborted. 1 = set by the ich6 when the start bit is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. this field corresponds to a[31:2]. the descriptor table must be dword-aligned. the descriptor table must not cross a 64-k boundary in memory. 1:0 reserved
454 intel ? i/o controller hub 6 (i ch6) family datasheet ide controller registers (d31:f1)
intel ? i/o controller hub 6 (ich6) family datasheet 455 sata controller registers (d31:f2) 12 sata controller registers (d31:f2) 12.1 pci configuration registers (sata?d31:f2) note: address locations that are not shown should be treated as reserved. all of the sata registers are in the core well. none of the registers can be locked. table 12-1. sata controller pci register address map (sata?d31:f2) (sheet 1 of 2) offset mnemonic register name default type 00?01h vid vendor identification 8086h ro 02?03h did device identification 2651h ich6 2652h ich6r 2653h ich6-m ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 02b0h r/wc, ro 08h rid revision identification see register description. ro 09h pi programming interface see register description. see register description 0ah scc sub class code see register description see register description 0bh bcc base class code 01h ro 0dh pmlt primary master latency timer 00h ro 10?13h pcmd_bar primary command block base address 00000001h r/w, ro 14?17h pcnl_bar primary control block base address 00000001h r/w, ro 18?1bh scmd_bar secondary command block base address 00000001h r/w, ro 1c?1fh scnl_bar secondary control block base address 00000001h r/w, ro 20?23h bar legacy bus master base address 00000001h r/w, ro 24?27h abar ahci base address 00000000h see register description 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap capabilities pointer 70h ro 3c int_ln interrupt line 00h r/w 3d int_pn interrupt pin see register description. ro 40?41h ide_timp primary ide timing 0000h r/w 42?43h ide_tims secondary ide timing 0000h r/w
456 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) note: the ich6 sata controller is not arbitrated as a pc i device, therefore it does not need a master latency timer. 12.1.1 vid?vendor identificati on register (sata?d31:f2) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bit lockable: no power well: core 44h sidetim slave ide timing 00h r/w 48h sdma_cnt synchronous dma control 00h r/w 4a?4bh sdma_tim synchronous dma timing 0000h r/w 54?57h ide_config ide i/o configuration 00000000h r/w 70?71h pid pci power management capability id 0001h ro 72?73h pc pci power management capabilities 4002h ro 74?75h pmcs pci power management control and status 0000h r/w, ro, r/wc 90h map address map 00h r/w 92?93h pcs port control and status 0000h r/w, ro, r/wc 94-97h sir sata initialization register 00000000h r/w a0h siri sata indexed registers index 00h r/w a4h strd sata indexed register data xxxxxxxxh r/w c0h atc apm trapping control 00h r/w c4 ats atm trapping status 00h r/wc d0?d3h sp scratch pad 00000000h r/w e0h? e3h bfcs bist fis control/status 00000000h r/w, r/wc e4h? e7h bftd1 bist fis transmit data, dw1 00000000h r/w e8h? ebh bftd2 bist fis transmit data, dw2 00000000h r/w table 12-1. sata controller pci register address map (sata?d31:f2) (sheet 2 of 2) offset mnemonic register name default type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h
intel ? i/o controller hub 6 (ich6) family datasheet 457 sata controller registers (d31:f2) 12.1.2 did?device identific ation register (sata?d31:f2) offset address: 02 ? 03h attribute: ro default value: ich6: 2651h size: 16 bit ich6r: 2652h ich6-m: 2653h lockable: no power well: core 12.1.3 pcicmd?pci command register (sata?d31:f2) address offset: 04h ? 05h attribute: ro, r/w default value: 0000h size: 16 bits bit description 15:0 device id ? ro. this is a 16-bit valu e assigned to the ich6 sata controller. bit description 15:11 reserved 10 interrupt disable ? r/w. this bit disables pin-based intx# interrupts. this bit has no effect on msi operation. 0 = internal intx# messages are generated if there is an interrupt and msi is not enabled. 1 = internal intx# messages will not be generated. 9 fast back to back enable (fbe) ? ro. reserved as 0. 8 serr# enable (serr_en) ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. reserved as 0. 6 parity error response (per) ? r/w. 0 = disabled. sata controller will not generat e perr# when a data parity error is detected. 1 = enabled. sata controller will generate per r# when a data parity error is detected. 5 vga palette snoop (vps) ? ro. reserved as 0. 4 postable memory write enable (pmwe) ? ro. reserved as 0. 3 special cycle enable (sce) ? ro. reserved as 0. 2 bus master enable (bme) ? r/w. this bit controls the ich6?s ability to act as a pci master for ide bus master transfers. this bit does not impact the generation of completions for split transaction commands. 1 memory space enable (mse) ? r/w / ro. this bit controls access to the sata controller?s target memory space (for ahci). (ich6-m/ich6r only) note: when map.mv (offset 90:bits 1:0) is not 00h, th is register is read only (ro). software is responsible for clearing this bi t before entering combined mode. for ich6, this bit is ro ?0?, unless t he scrae bit (offset 94h:bit 9) is set. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disables access to the legacy or native ide ports (both primary and secondary) as well as the bus master i/o registers. 1 = enable. note that the base address register for the bus master registers should be programmed before this bit is set.
458 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.4 pcists ? pci status register (sata?d31:f2) address offset: 06 ? 07h attribute: r/wc, ro default value: 02b0h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. 12.1.5 rid?revision identifi cation register (sata?d31:f2) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected by sata controller. 1 = sata controller detects a parity error on its interface. 14 signaled system error (sse) ? ro. reserved as 0. 13 received master abort (rma) ? r/wc. 0 = master abort not generated. 1 = sata controller, as a master, generated a master abort. 12 reserved as 0 ? ro. 11 signaled target abort (sta) ? ro. reserved as 0. 10:9 devsel# timing status (dev_sts) ? ro. 01 = hardwired; controls the device select time for the sata controller?s pci interface. 8 data parity error detected (dped) ? ro. for ich6, this bit can only be set on read completions received from sibus where there is a parity error. 1 = sata controller, as a master, either detects a pa rity error or sees the pa rity error line asserted, and the parity error response bit (bit 6 of the command register) is set. 7 fast back to back capable (fb2bc) ? ro. reserved as 1. 6 user definable features (udf) ? ro. reserved as 0. 5 66mhz capable (66mhz_cap) ? ro. reserved as 1. 4 capabilities list (cap_list) ? ro. this bit indicates the presence of a capabilities list. the minimum requirement for the capabilities lis t must be pci power management for the sata controller. 3 interrupt status (ints) ? ro. reflects the state of intx# messages. 0 = interrupt is cleared (independent of the state of interrupt disable bit in the command register [offset 04h]). 1 = interrupt is to be asserted 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register
intel ? i/o controller hub 6 (ich6) family datasheet 459 sata controller registers (d31:f2) 12.1.6 pi?programming inter face register (sata?d31:f2) 12.1.6.1 when sub class code register (d31:f2 :offset 0ah) = 01h address offset: 09h attribute: r/w, ro default value: see bit description size: 8 bits 12.1.6.2 when sub class code register (d31:f2 :offset 0ah) = 04h address offset: 09h attribute: ro default value: 00h size: 8 bits bit description 7 this read-only bit is a 1 to indicate that the ich6 supports bus master operation 6:4 reserved. will always return 0. 3 secondary mode native capable (snc) ? ro. 0 = secondary controller only supports legacy mode. 1 = secondary controller supports both legacy and native modes. when map.mv (d31:f2:offset 90:bits 1:0) is any va lue other than 00b, this bit reports as a 0. when map.mv is 00b, this bit reports as a 1. 2 secondary mode native enable (sne) ? r/w / ro. this bit determines the mode that the secondary channel is operating in. 0 = secondary controller operating in legacy (compatibility) mode 1 = secondary controller operating in native pci mode. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit is read-only (ro). software is responsible for clearing this bit before entering combined mode. when map.mv is 00b, this bit is read/write (r/w). if this bit is set by software, then the pne bit (bit 0 of this register) must also be set by software. while in theory these bits can be programmed sepa rately, such a configuration is not supported by hardware. 1 primary mode native capable (pnc) ? ro. 0 = primary controller only supports legacy mode. 1 = primary controller suppor ts both legacy and native modes. when map.mv (d31:f2:offset 90:bits 1:0) is any va lue other than 00b, this bit reports as a 0. when map.mv is 00b, this bit reports as a 1 0 primary mode native enable (pne) ? r/w / ro. this bit determines the mode that the primary channel is operating in. 0 = primary controller operating in legacy (compatibility) mode. 1 = primary controller operating in native pci mode. when map.mv (d31:f2:offset 90:bits 1:0) is any value other than 00b, this bit is read-only (ro). software is responsible for clearing this bit before entering combined mode. when map.mv is 00b, this bit is read/write (r/w). if this bit is set by software, then the sne bit (bit 2 of this register) must also be set by software. while in theory these bits can be programmed sepa rately, such a configuration is not supported by hardware. bit description 7:0 interface (if) ? ro. when configured as raid, this register becomes read only 0.
460 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.6.3 when sub class code regist er (d31:f2:offset 0ah) = 06h address offset: 09h attribute: ro default value: 01h size: 8 bits 12.1.7 scc?sub class code register (sata?d31:f2) address offset: 0ah attribute: see bit description default value: see bit description size: 8 bits 12.1.8 bcc?base class code register (sata?d31:f2sata?d31:f2) address offset: 0bh attribute: ro default value: 01h size: 8 bits bit description 7:0 interface (if) ? ro. this field indicates the sata controller supports ahci, rev 1.0. bit description 7:0 sub class code (scc). this field specifies the sub-class code of the controller, per the table below: intel ? ich6 only: ich6-m only: ich6r only: scc register attribute scc register value ro 01h (ide controller) map.uscc (d31:f2:offset 90h:bit 7) scc register attribute scc register value 0b ro 01h (ide controller) 1b ro 06h (sata controller) map.uscc (d31:f2:offset 90h:bit 7) scc register attribute scc default register value x r/wo 04h (raid controller) bit description 7:0 base class code (bcc) ? ro. 01h = mass storage device
intel ? i/o controller hub 6 (ich6) family datasheet 461 sata controller registers (d31:f2) 12.1.9 pmlt?primary master latency timer register (sata?d31:f2) address offset: 0dh attribute: ro default value: 00h size: 8 bits 12.1.10 pcmd_bar?primary co mmand block base address register (sata?d31:f2) address offset: 10h ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 8-byte i/o space is used in native m ode for the primary controller?s command block. 12.1.11 pcnl_bar?primary contro l block base address register (sata?d31:f2) address offset: 14h ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits . note: this 4-byte i/o space is used in native m ode for the primary controller?s command block. bit description 7:0 master latency timer count (mltc) ? ro. the sata controller is implemented internally, and is not arbitrated as a pci device, so it does not need a master latency timer. 00h = hardwired. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base address of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indi cate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base address of the i/o space (4 consecutive i/o locations). 1 reserved 0 resource type indicator (rte) ? ro. hardwire d to 1 to indicate a request for i/o space.
462 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.12 scmd_bar?secondary command block base address register (ide d31:f1) address offset: 18h ? 1bh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 12.1.13 scnl_bar?secondary control block base address register (ide d31:f1) address offset: 1ch ? 1fh attribute: r/w, ro default value: 00000001h size: 32 bits note: this 4-byte i/o space is used in native mode for the secondary controller?s command block. 12.1.14 bar ? legacy bus mast er base address register (sata?d31:f2) address offset: 20h ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits the bus master ide interface functi on uses base address register 5 to request a 16-byte i/o space to provide a software interface to the bus ma ster functions. only 12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). only bits [15:4] are used to decode the address. bit description 31:16 reserved 15:3 base address ? r/w. this field provides the base addre ss of the i/o space (8 consecutive i/o locations). 2:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:2 base address ? r/w. this field provides the base addre ss of the i/o space (4 consecutive i/o locations). 1reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space. bit description 31:16 reserved 15:4 base address ? r/w. this field provides the base addre ss of the i/o space (16 consecutive i/o locations). 3:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate a request for i/o space.
intel ? i/o controller hub 6 (ich6) family datasheet 463 sata controller registers (d31:f2) 12.1.15 abar ? ahci base address register (sata?d31:f2) 12.1.15.1 intel ? ich6 only address offset: 24h?27h attribute: ro default value: 00000000h size: 32 bits note: for ich6, this register is reserved and read only, unless the scrae bit (offset 94h:bit 9) is set, in which case the register follows the definition given in section 12.1.15.2 . 12.1.15.2 intel ? ich6r / ich6-m only address offset: 24h ? 27h attribute: r/w, ro default value: 00000000h size: 32 bits this register allocates space for the memory registers defined in section 12.3 . notes: 1. when the map.mv register is programmed for comb ined mode (00b), this register is ro. software is responsible for clearing this bit before entering combined mode. 2. the abar register must be set to a value of 0001_0000h or greater. 12.1.16 svid?subsystem vendor identification register (sata?d31:f2) address offset: 2ch ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core bit description 31:0 reserved bit description 31:10 base address (ba) ? r/w. base address of register memory space (aligned to 1 kb) 9:4 reserved 3 prefetchable (pf) ? ro. this bit indica tes that this range is not pre-fetchable 2:1 type (tp) ? ro. this bit indicates that this range can be mapped anywhere in 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for register memory space. bit description 15:0 subsystem vendor id (svid) ? r/wo. value is written by bios . no hardware action taken on this value.
464 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.17 sid?subsystem identifi cation register (sata?d31:f2) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 12.1.18 cap?capabilities poin ter register (sata?d31:f2) address offset: 34h attribute: ro default value: 70h size: 8 bits 12.1.19 int_ln?interrupt line register (sata?d31:f2) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 12.1.20 int_pn?interrupt pi n register (sata?d31:f2) address offset: 3dh attribute: ro default value: see register description size: 8 bits bit description 15:0 subsystem id (sid) ? r/wo. value is written by bios. no hardware action taken on this value. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this field indi cates that the first capability pointer offset is 70h, the pci power management capability. bit description 7:0 interrupt line ? r/w. this field is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d31ip.sip (c hipset configuration registers:offset 3100h:bits 11:8).
intel ? i/o controller hub 6 (ich6) family datasheet 465 sata controller registers (d31:f2) 12.1.21 ide_tim ? ide timing register (sata?d31:f2) address offset: primary: 40 ? 41h attribute: r/w secondary: 42 ? 43h default value: 0000h size: 16 bits this register controls the timings driven on the ide cable for pio and 8237 style dma transfers. it also controls operation of the buffer for pio transfers. note: this register is r/w to maintain software compat ibility and enable parallel ata functionality when the pci functions are combined. these bits ha ve no effect on sata operation unless otherwise noted. bit description 15 ide decode enable (ide) ? r/w. individually enable/disabl e the primary or secondary decode. 0 = disable. 1 = enables the intel ? ich6 to decode the associated command blocks (1f0?1f7h for primary, 170?177h for secondary) and control block (3f6h for primary and 376h for secondary). this bit effects the ide decode ranges for both legacy and native-mode decoding. note: this bit affects sata operation in both combined and non-combined ata modes. see section 5.17 for more on ata modes of operation. 14 drive 1 timing register enable (sitre) ? r/w. 0 = use bits 13:12, 9:8 for both drive 0 and drive 1. 1 = use bits 13:12, 9:8 for drive 0, and us e the slave ide timing register for drive 1 13:12 iordy sample point (isp) ? r/w. the setting of these bits determines the number of pci clocks between ide ior#/iow# assertion and the first iordy sample point. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 11:10 reserved 9:8 recovery time (rct) ? r/w. the setting of these bits determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clock 7 drive 1 dma timing enable (dte1) ? r/w. 0 = disable. 1 = enable the fast timing mode for dma transfers onl y for this drive. pio transfers to the ide data port will run in compatible timing. 6 drive 1 prefetch/posting enable (ppe1) ? r/w. 0 = disable. 1 = enable prefetch and posting to the ide data port for this drive. 5 drive 1 iordy sample point enable (ie1) ? r/w. 0 = disable iordy sampling for this drive. 1 = enable iordy sampling for this drive.
466 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 4 drive 1 fast timing bank (time1) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = when this bit =1 and bit 14 = 0, accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time. when this bit = 1 and bit 14 = 1, accesses to the data port will use the iordy sample point and recover time specified in the slave ide timing register. 3 drive 0 dma timing enable (dte0) ? r/w. 0 = disable 1 = enable fast timing mode for dma transfers only for this drive. pio transfers to the ide data port will run in compatible timing. 2 drive 0 prefetch/posting enable (ppe0) ? r/w. 0 = disable prefetch and posting to the ide data port for this drive. 1 = enable prefetch and posting to the ide data port for this drive. 1 drive 0 iordy sample point enable (ie0) ? r/w. 0 = disable iordy sampling is disabled for this drive. 1 = enable iordy sampling for this drive. 0 drive 0 fast timing bank (time0) ? r/w. 0 = accesses to the data port will us e compatible timings for this drive. 1 = accesses to the data port will use bits 13:12 for the iordy sample point, and bits 9:8 for the recovery time bit description
intel ? i/o controller hub 6 (ich6) family datasheet 467 sata controller registers (d31:f2) 12.1.22 sidetim?slave ide ti ming register (sata?d31:f2) address offset: 44h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compat ibility and enable parallel ata functionality when the pci functions are combined. these bits ha ve no effect on sata operation unless otherwise noted. bit description 7:6 secondary drive 1 iordy sample point (sisp1) ? r/w. this field determines the number of pci clocks between ide ior#/iow# assert ion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 5:4 secondary drive 1 recovery time (srct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for secondary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks 3:2 primary drive 1 iordy sample point (pisp1) ? r/w. this field determines the number of pci clocks between ior#/iow# assertion and the first iordy sample point, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 5 clocks 01 = 4 clocks 10 = 3 clocks 11 = reserved 1:0 primary drive 1 recovery time (prct1) ? r/w. this field determines the minimum number of pci clocks between the last iordy sample point and the ior#/iow# strobe of the next cycle, if the access is to drive 1 data port and bit 14 of the ide timing register for primary is set. 00 = 4 clocks 01 = 3 clocks 10 = 2 clocks 11 = 1 clocks
468 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.23 sdma_cnt?synchronous dma control register (sata?d31:f2) address offset: 48h attribute: r/w default value: 00h size: 8 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation unless otherwise noted. bit description 7:4 reserved 3 secondary drive 1 synchronous dma mode enable (ssde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary channel drive 1 2 secondary drive 0 synchronous dma mode enable (ssde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for secondary drive 0. 1 primary drive 1 synchronous dma mode enable (psde1) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 1 0 primary drive 0 synchronous dma mode enable (psde0) ? r/w. 0 = disable (default) 1 = enable synchronous dma mode for primary channel drive 0
intel ? i/o controller hub 6 (ich6) family datasheet 469 sata controller registers (d31:f2) 12.1.24 sdma_tim?synchronous dma timing register (sata?d31:f2) address offset: 4a ? 4bh attribute: r/w default value: 0000h size: 16 bits note: this register is r/w to maintain software compat ibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation, unless otherwise noted. bit description 15:14 reserved 13:12 secondary drive 1 cycle time (sct1) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 11:10 reserved 9:8 secondary drive 0 cycle time (sct0) ? r/w. for ultra ata mode. the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 7:6 reserved 5:4 primary drive 1 cycle time (pct1) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. 3:2 reserved 1:0 primary drive 0 cycle time (pct0) ? r/w. for ultra ata mode, the setting of these bits determines the minimum write str obe cycle time (ct). the dmardy#-to-stop (rp) time is also determined by the setting of these bits. scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved scb1 = 0 (33 mhz clk) scb1 = 1 (66 mhz clk) fast_scb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved pcb1 = 0 (33 mhz clk) pcb1 = 1 (66 mhz clk) fast_pcb1 = 1 (133 mhz clk) 00 = ct 4 clocks, rp 6 clocks 00 = reserved 00 = reserved 01 = ct 3 clocks, rp 5 clocks 01 = ct 3 clocks , rp 8 clocks 01 = ct 3 clocks, rp 16 clocks 10 = ct 2 clocks, rp 4 clocks 10 = ct 2 clocks, rp 8 clocks 10 = reserved 11 = reserved 11 = reserved 11 = reserved
470 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.25 ide_config?ide i/o configuration register (sata?d31:f2) address offset: 54h ? 57h attribute: r/w default value: 00000000h size: 32 bits note: this register is r/w to maintain software compatibility and enable parallel ata functionality when the pci functions are combined. these bits have no effect on sata operation, unless otherwise noted. bit description 31:24 reserved 23:20 scratchpad (sp2). intel ? ich6 does not perform any actions on these bits. 19:18 sec_sig_mode ? r/w. these bits are used to control mode of the secondary ide signal pins for swap bay support. if the srs bit (chipset configurati on registers:offset 3414h:bit 1) is 1, the reset states of bits 19:18 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 17:16 prim_sig_mode ? r/w. these bits are used to control m ode of the primary ide signal pins for mobile swap bay support. if the prs bit (chipset configurati on registers:offset 3414h:bit 1) is 1, the reset states of bits 17:16 will be 01 (tri-state) instead of 00 (normal). 00 = normal (enabled) 01 = tri-state (disabled) 10 = drive low (disabled) 11 = reserved 15 fast secondary drive 1 base clock (fast_scb1) ? r/w. this bit is used in conjunction with the sct1 bits (d31:f2:4ah, bits 13:12) to enable/di sable ultra ata/100 timings for the secondary slave drive. 0 = disable ultra ata/100 timing for the secondary slave drive. 1 = enable ultra ata/100 timing for t he secondary slave drive (overri des bit 3 in this register). 14 fast secondary drive 0 base clock (fast_scb0) ? r/w. this bit is used in conjunction with the sct0 bits (d31:f2:4ah, bits 9:8) to enable/dis able ultra ata/100 timings for the secondary master drive. 0 = disable ultra ata/100 timing for the secondary master drive. 1 = enable ultra ata/100 timing for t he secondary master drive (overri des bit 2 in this register). 13 fast primary drive 1 base clock (fast_pcb1) ? r/w. this bit is used in conjunction with the pct1 bits (d31:f2:4ah, bits 5:4) to enable/dis able ultra ata/100 timings for the primary slave drive. 0 = disable ultra ata/100 timing for the primary slave drive. 1 = enable ultra ata/100 timing for the primary slav e drive (overrides bit 1 in this register). 12 fast primary drive 0 base clock (fast_pcb0) ? r/w. this bit is used in conjunction with the pct0 bits (d31:f2:4ah, bits 1:0) to enable/dis able ultra ata/100 timings for the primary master drive. 0 = disable ultra ata/100 timing for the primary master drive. 1 = enable ultra ata/100 timing for the primary mast er drive (overrides bit 0 in this register). 11:8 reserved 7:4 scratchpad (sp1). ich6 does not perform any action on these bits.
intel ? i/o controller hub 6 (ich6) family datasheet 471 sata controller registers (d31:f2) 12.1.26 pid?pci power manageme nt capability identification register (sata?d31:f2) address offset: 70 ? 71h attribute: ro default value: 0001h size: 16 bits 12.1.27 pc?pci power manageme nt capabilities register (sata?d31:f2) address offset: 72 ? 73h attribute: ro default value: 4002h size: 16 bits f 3 secondary drive 1 base clock (scb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 2 secondary drive 0 base clock (scbo) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 1 primary drive 1 base clock (pcb1) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings 0 primary drive 0 base clock (pcb0) ? r/w. 0 = 33 mhz base clock for ultra ata timings. 1 = 66 mhz base clock for ultra ata timings bit description bits description 15:8 next capability (next) ? ro . indicates that this is the last item in the list. 7:0 capability id (cid) ? ro. indicates that this pointer is a pci power management. bits description 15:11 pme support (pme_sup) ? ro. this field i ndicates pme# can be generated from the d3 hot state in the sata host controller. 10 d2 support (d2_sup) ? ro. hardwired to 0. the d2 state is not supported 9 d1 support (d1_sup) ? ro. hardwired to 0. the d1 state is not supported 8:6 auxiliary current (aux_cur) ? ro. pme# from d3 cold state is not supported, therefore this field is 000b. 5 device specific initialization (dsi) ? ro. hard wired to 0 to indicate that no device-specific initialization is required. 4 reserved 3 pme clock (pme_clk) ? ro. hardwired to 0 to indi cate that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. hardwired to 010 to indica tes support for revision 1.1 of the pci power management specification.
472 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.28 pmcs?pci power mana gement control and status register (sata?d31:f2) address offset: 74 ? 75h attribute: ro , r/w, r/wc default value: 0000h size: 16 bits 12.1.29 map?address map register (sata?d31:f2) address offset: 90h attribute: r/w default value: 00h size: 8 bits bits description 15 pme status (pmes) ? r/wc. bit is set when a pme event is to be requested, and if this bit and pmee is set, a pme# will be gener ated from the sata controller 14:9 reserved 8 pme enable (pmee) ? r/w. when set, the sata controller generates pme# form d3 hot on a wake event. 7:2 reserved 1:0 power state (ps) ? r/w. these bits are used both to determine the current power state of the sata controller and to set a new power state. 00 = d0 state 11 = d3 hot state when in the d3 hot state, the controller?s configuration sp ace is available, but the i/o and memory spaces are not. additionally, interrupts are blocked. bits description 7 use sata class code (uscc) ? r/w. ich6 / ich6r only: reserved. software must not set this bit. ich6-m only: 0 =subclass code reported in scc (d31:f2:offset 0ah) is 01h (ide controller). 1 =subclass code reported in scc is 06h (sata controller). 6:2 reserved. 1:0 map value ? r/w. map value (mv): the value in the bits below indicate the address range the sata ports responds to, and whether or not the pata and sata functions are combined. when in combined mode, the ahci memory space is not available and ahci may not be used. 00 = non-combined. p0 is primary master, p2 is the primary slave. p1 is secondary master, p3 is the secondary slave (desktop only). p0 is primary ma ster, p2 is the primary slave (mobile only). 01 = combined. ide is primary. p1 is secondary master, p3 is th e secondary slave. (desktop only) 10 = combined. p0 is primary master. p2 is primary slave. ide is secondary 11 = reserved
intel ? i/o controller hub 6 (ich6) family datasheet 473 sata controller registers (d31:f2) 12.1.30 pcs?port control and st atus register (sata?d31:f2) address offset: 92h ? 93h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits this register is only used in systems that do not support ahci. in ahci enabled systems, bits[3:0] must always be set (ich6r only) / bits[2,0] must always be set (ich6-m only), and the status of the port is controlled through ahci memory space. bits description 15:8 reserved. 7 (desktop only) port 3 present (p3p) ? ro. the status of this bit may change at any time. this bit is cleared when the port is disabled via p3e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 3 has been detected. 7 (mobile only) reserved 6 port 2 present (p2p) ? ro. the status of this bit may change at any time. this bit is cleared when the port is disabled via p2e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 2 has been detected. 5 (desktop only) port 1 present (p1p) ? ro. the status of this bit may change at any time. this bit is cleared when the port is disabled via p1e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 1 has been detected. 5 (mobile only) reserved 4 port 0 present (p0p) ? ro. the status of this bit may change at any time. this bit is cleared when the port is disabled via p0e. this bit is not cleared upon surprise removal of a device. 0 = no device detected. 1 = the presence of a device on port 0 has been detected. 3 (desktop only) port 3 enabled (p3e) ? r/w. 0 = disabled. the port is in the ?off ? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p3cmd.sud (offset abar+298h:bit 1) 3 (mobile only) reserved 2 port 2 enabled (p2e) ? r/w. 0 = disabled. the port is in the ?off ? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p2cmd.sud (offset abar+218h:bit 1) 1 (desktop only) port 1 enabled (p1e) ? r/w. 0 = disabled. the port is in the ?off ? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p1cmd.sud (offset abar+198h:bit 1)
474 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.31 sir - sata initialization register address offset: 94h attribute: r/w default value: 00000000h size: 32 bits . 1 (mobile only) reserved 0 port 0 enabled (p0e) ? r/w. 0 = disabled. the port is in the ?off? state and cannot detect any devices. 1 = enabled. the port can transition between the on, partial, and slumber states and can detect devices. note: this bit takes precedence over p0cmd.sud (offset abar+118h:bit 1) bits description bit description 31:28 reserved 27:24 (desktop only) reserved 27:24 (mobile only) sata initialization field 3 (sif3) ? r/w. bios shall always program this field to the value 0ah. all other values are reserved. 23 sata initialization field 2 (sif2) ? r/w. bios shall always program this register to the value 1b. all other values are reserved. 22:10 reserved 9 scr access enable (scrae) ? r/w. in non-ahci mode, this bi t allows access to the sata scr registers (sstatus, scontrol, and serror registers). 0 = the abar (dev31:f2:offset 24h) register and mse bit field (dev31:f2:offset 04h:bit 1) remain as defined. 1 = the abar (dev31:f2:offset 24h) register and mse bit field (dev31:f2:offset 04h:bit 1) are forced to be read/write. notes: 1. using this mode only allows access to ahci registers pxsst s, pxscrtl, pxserr. all other ahci space is reserved when this bit is set. 2. proper use of this bit requires: ? abar must be programmed to a valid bar; mse must be set before software can access ahci space. ? the port implemented bit (d31:f2, offset abar+0 ch) for the corresponding port has to be set to allow access to the ahci port specif ic pxssts, pxscrtl, and pxserr registers. 8:0 sata initialization field 1 (sif1) ? r/w. bios shall always program this register to the value 182h. all other values are reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 475 sata controller registers (d31:f2) 12.1.32 siri?sata indexed registers index address offset: a0h attribute: r/w default value: 00h size: 8 bits . 12.1.33 strd?sata indexed register data address offset: a4h attribute: r/w default value: xxxxxxxxh size: 32 bits . bit description 7 reserved 6:2 index (idx) ? r/w. this field is a 5-bit index pointer into the sata i ndexed register space. data is written into and read from the sird register (d31:f2:a4h). 1:0 reserved table 12-1. sata indexed registers index name 00h?03h sata tx termination test register 1 (sttt1) 04h?17h reserved 18h?1bh sata initialization register 18 (sir18) 1ch?1fh sata test mode enable register (stme) 20h?27h reserved 28h?2bh sata initialization register 28 (sir28) 2bh?73h reserved 74h?77h sata tx termination test register 2 (sttt2) 78h?83h reserved 84h?87h sata initialization register 84 (sir84) 88h?ffh reserved bit description 31:0 data (dta) ? r/w. this field is a 32-bit data value that is written to the register pointed to by siri (d31:f2;a0h) or read from the register pointed to by siri.
476 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.34 sttt1?sata indexe d registers index 00h (sata tx termination test register 1) address offset: index 00h - 03h attribute: r/w default value: 00000000h size: 32 bits . bit description 31:2 reserved. 1 port 1 tx termination test enable ? r/w: 0 = port 1 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 1 tx termination. note: this bit only to be used for system board testing. 0 port 0 tx termination test enable ? r/w: 0 = port 0 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 0 tx termination. note: this bit only to be used for system board testing.
intel ? i/o controller hub 6 (ich6) family datasheet 477 sata controller registers (d31:f2) 12.1.35 sir18?sata indexed registers index 18h (sata initialization register 18h) address offset: index 18h - 01bh attribute: r/w default value: 0000025bh size: 32 bits . 12.1.36 stme?sata indexed registers index 1ch (sata test mode enable register) address offset: index 1ch - 1fh attribute: r/w default value: 00000000h size: 32 bits . 12.1.37 sir28?sata indexed registers index 28h (sata initialization register 28h) address offset: index 28h - 2bh attribute: r/w default value: 00cc2080h size: 32 bits . bit description 31:6 reserved. 5:0 bios programs this field to 101101b. bit description 31:19 reserved. 18 sata test mode enable bit ? r/w: 0 = entrance to intel ich6 sata test modes are disabled. 1 = this bit allows entrance to intel ich6 sata test modes when set. note: this bit only to be used for system board testing. 17:0 reserved. bit description 31:23 reserved. 22 bios leaves this bit at default. 21:19 reserved 18 bios leaves this bit at default. 17:0 reserved.
478 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.38 sttt2?sata indexe d registers index 74h (sata tx termination test register 2) address offset: index 74h - 77h attribute: r/w default value: 00000000h size: 32 bits . bit description 31:18 reserved. 17 port 3 tx termination test enable ? r/w: 0 = port 3 tx termination port testing is disabled. 1 = setting this bit will enable testing of port 3 tx termination. note: this bit only to be used for system board testing. 16 port 2 tx termination test enable ? r/w: 0 = port 2tx termination port testing is disabled. 1 = setting this bit will enable testing of port 2tx termination. note: this bit only to be used for system board testing. 15:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 479 sata controller registers (d31:f2) 12.1.39 sir84?sata indexed registers index 84h (sata initialization register 84h) address offset: index 84h - 87h attribute: r/w default value: 0000001bh size: 32 bits . 12.1.40 atc?apm trapping cont rol register (sata?d31:f2) address offset: c0h attribute: r/w default value: 00h size: 8 bits . bit description 31:6 reserved. 5:0 bios programs this field to 101101b. bit description 7:4 reserved 3 secondary slave trap (sst) ? r/w. this bit enables trapping and smi# assertion on legacy i/o accesses to 170h?177h and 376h. the active device on the secondary interface must be device 1 for the trap and/or smi# to occur. 2 secondary master trap (spt) ? r/w. this bit enables trapping and smi# assertion on legacy i/o accesses to 170h?177h and 376h. the active device on the secondary interface must be device 0 for the trap and/or smi# to occur. 1 primary slave trap (pst) ? r/w. this bit enables trapping and smi# assertion on legacy i/o accesses to 1f0h?1f7h and 3f6h. the active device on the primary interface must be device 1 for the trap and/or smi# to occur. 0 primary master trap (pmt) ? r/w. this bit enables trapping an d smi# assertion on legacy i/o accesses to 1f0h?1f7h and 3f6h. the active device on the primary interface must be device 0 for the trap and/or smi# to occur.
480 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.41 ats?apm trapping stat us register (sata?d31:f2) address offset: c4h attribute: r/wc default value: 00h size: 8 bits . 12.1.42 sp?scratch pad re gister (sata?d31:f2) address offset: d0h attribute: r/w default value: 00000000h size: 32 bits . 12.1.43 bfcs?bist fis control/status register (sata?d31:f2) address offset: e0h ? e3h attribute: r/w, r/wc default value: 00000000h size: 32 bits bit description 7:4 reserved 3 secondary slave trap (sst) ? r/wc. this bit indicates that a trap occurred to the secondary slave device. 2 secondary master trap (spt) ? r/wc. this bit indicates that a trap occurred to the secondary master device. 1 primary slave trap (pst) ? r/wc. this bit indicates that a trap occurred to the primary slave device. 0 primary master trap (pmt) ? r/wc. this bit indicates that a trap occurred to the primary master device. bit description 31:0 data (dt) ? r/w. this is a read/write register that is available for software to use. no hardware action is taken on this register. bits description 31:14 reserved 13 (desktop only) port 3 bist fis initiate (p3bfi) ? r/w. when a rising edge is detected on this bit field, the ich6 initiates a bist fis to the device on port 3, usi ng the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 3 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bi ts at offset 92h prior to attempting additional bist fises or to return the ich6 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then soft ware can clear then set the p3bfi bit to initiate another bist fis. this can be retried until t he bist fis eventually completes successfully. 13 (mobile only) reserved. 12 port 2 bist fis initiate (p2bfi) ? r/w. when a rising edge is detected on this bit field, the ich6 initiates a bist fis to the device on port 2, usi ng the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis will only be initiated if a device on port 2 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bi ts at offset 92h prior to attempting additional bist fises or to return the ich6 to a normal operational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then soft ware can clear then set the p2bfi bit to initiate another bist fis. this can be retried until t he bist fis eventually completes successfully.
intel ? i/o controller hub 6 (ich6) family datasheet 481 sata controller registers (d31:f2) 11 bist fis successful (bfs) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitt ed by ich6 receives an r_ok completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. 10 bist fis failed (bff) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set any time a bist fis transmitt ed by ich6 receives an r_err completion status from the device. note: this bit must be cleared by software prior to initiating a bist fis. 9 (desktop only) port 1 bist fis initiate (p1bfi) ? r/w. when a rising edge is detect ed on this bit field, the ich6 initiates a bist fis to the device on port 1, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis wi ll only be initiated if a device on port 1 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bi ts at offset 92h prior to attempting additional bist fises or to return the ich6 to a normal oper ational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then softwa re can clear then set the p1bfi bit to initiate another bist fis. this can be retried until t he bist fis eventually completes successfully. 9 (mobile only) reserved. 8 port 0 bist fis initiate (p0bfi) ? r/w. when a rising edge is detect ed on this bit field, the ich6 initiates a bist fis to the device on port 0, using the parameters specified in this register and the data specified in bftd1 and bftd2. the bist fis wi ll only be initiated if a device on port 0 is present and ready (not partial/slumber state). after a bist fis is successfully completed, software must disable and re-enable the port using the pxe bi ts at offset 92h prior to attempting additional bist fises or to return the ich6 to a normal oper ational mode. if the bist fis fails to complete, as indicated by the bff bit in the register, then softwa re can clear then set the p0bfi bit to initiate another bist fis. this can be retried until t he bist fis eventually completes successfully. 7:2 bist fis parameters . these 6 bits form the contents of the upper 6 bits of the bist fis pattern definition in any bist fis transmitted by the ich6. this field is not port specific ? its contents will be used for any bist fis initiated on port 0, port 1, port 2 or port 3. the specific bit definitions are: bit 7: t ? far end transmit mode bit 6: a ? align bypass mode bit 5: s ? bypass scrambling bit 4: l ? far end retimed loopback bit 3: f ? far end analog loopback bit 2: p ? primitive bit for use with transmit mode 1:0 reserved bits description
482 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.1.44 bftd1?bist fis transmit data1 register (sata?d31:f2) address offset: e4h ? e7h attribute: r/w default value: 00000000h size: 32 bits 12.1.45 bftd2?bist fis transmit data2 register (sata?d31:f2) address offset: e8h ? ebh attribute: r/w default value: 00000000h size: 32 bits bits description 31:0 bist fis transmit data 1 ? r/w. the data programmed into this register will form the contents of the second dword of any bist fis initiated by the ich6. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 2nd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h). bits description 31:0 bist fis transmit data 2 ? r/w. the data programmed into this register will form the contents of the third dword of any bist fis initiated by the ich6. this register is not port specific ? its contents will be used for bist fis initiated on any port. although the 2nd and 3rd dws of the bist fis are only meaningful when the ?t? bit of the bist fis is set to indicate ?far-end transmit mode?, this register?s contents will be transmitted as the bist fis 3rd dw regardless of whether or not the ?t? bit is indicated in the bfcs register (d31:f2:e0h).
intel ? i/o controller hub 6 (ich6) family datasheet 483 sata controller registers (d31:f2) 12.2 bus master ide i/o registers (d31:f2) the bus master ide functio n uses 16 bytes of i/o space, allocated via the bar register, located in device 31:function 2 conf iguration space, offset 20h. all bus master id e i/o space registers can be accessed as byte, word, or dword quantities. r eading reserved bits returns an indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be attempted). these registers are only used for legacy operation. soft ware must not use these registers when running ahci. the description of the i/o registers is shown in table 12-2 . table 12-2. bus master ide i/o register address map bar+ offset mnemonic register default type 00 bmicp command register primary 00h r/w 01 ? reserved ? ro 02 bmisp bus master ide status register primary 00h r/w, r/wc, ro 03 ? reserved ? ro 04?07 bmidp bus master ide descriptor table pointer pr imary xxxxxxxxh r/w 08 bmics command register secondary 00h r/w 09 ? reserved ? ro 0a bmiss bus master ide status register secondary 00h r/w, r/wc, ro 0b ? reserved ? ro 0c?0f bmids bus master ide descriptor table pointer secondary xxxxxxxxh r/w
484 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.2.1 bmic[p,s]?bus master ide command register (d31:f2) address offset: primary: bar + 00h attribute: r/w secondary: bar + 08h default value: 00h size: 8 bits bit description 7:4 reserved. returns 0. 3 read / write control (rwc) ? r/w. this bit sets the direction of the bus master transfer: this bit must not be changed when the bus master function is active. 0 = memory reads 1 = memory writes 2:1 reserved. returns 0. 0 start/stop bus master (start) ? r/w. 0 = all state information is lost when this bit is cleared. master mode operation cannot be stopped and then resumed. if this bit is reset while bus ma ster operation is stil l active (i.e., the bus master ide active bit (d31:f2:bar + 02h, bit 0) of the bus master ide status register for that ide channel is set) and the drive has not yet finished its data transfer (the interrupt bit in the bus master ide status register for that ide c hannel is not set), the bus master command is said to be aborted and data transferred from the drive may be discarded instead of being written to system memory. 1 = enables bus master operation of the controll er. bus master operation does not actually start unless the bus master enable bit (d31:f1:04h, bit 2) in pci configuration space is also set. bus master operation begins when this bit is detec ted changing from 0 to 1. the controller will transfer data between the ide device and memory only when this bit is set. master operation can be halted by writing a 0 to this bit. note: this bit is intended to be cleared by software after the data transfer is completed, as indicated by either the bus master ide active bit being cleared or the interrupt bit of the bus master ide status register for that ide channel being set, or both. hardware does not clear this bit automatically. if this bit is cleared to 0 prior to the dma data transfer being initiated by the drive in a device to memory data trans fer, then the ich6 will not send dmat to terminate the data transfer. sw intervention (e.g. sending srst) is required to reset the interface in this condition.
intel ? i/o controller hub 6 (ich6) family datasheet 485 sata controller registers (d31:f2) 12.2.2 bmis[p,s]?bus maste r ide status register (d31:f2) address offset: primary: bar + 02h attribute: r/w, r/wc, ro secondary: bar + 0ah default value: 00h size: 8 bits 12.2.3 bmid[p,s]?bus master ide descriptor table pointer register (d31:f2) address offset: primary: bar + 04h?07h attribute: r/w secondary: bar + 0ch ? 0fh default value: all bits undefined size: 32 bits bit description 7 prd interrupt status (prdis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the host controller exec ution of a prd that has its prd_int bit set. 6 drive 1 dma capable ? r/w. 0 = not capable. 1 = capable. set by device dependent code (bios or devic e driver) to indicate that drive 1 for this channel is capable of dma transfers, and that t he controller has been initialized for optimum performance. the intel ? ich6 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 5 drive 0 dma capable ? r/w. 0 = not capable 1 = capable. set by device dependent code (bios or devic e driver) to indicate that drive 0 for this channel is capable of dma transfers, and that t he controller has been initialized for optimum performance. the ich6 does not use this bit. it is intended for systems that do not attach bmide to the pci bus. 4:3 reserved. returns 0. 2 interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set when a device fis is received with the ?i ? bit set, provided that software has not disabled interrupts via the nien bit of the device control register (see chapter 5 of the serial ata specification , revision 1.0a). 1 error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the controller encounters a target abort or master abort when transferring data on pci. 0 bus master ide active (act) ? ro. 0 = this bit is cleared by the ich6 when the last transfer for a region is performed, where eot for that region is set in the region descriptor. it is also cleared by the ich6 when the start bus master bit (d31:f2:bar+ 00h, bit 0) is cleared in the command register. when this bit is read as a 0, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 1 = set by the ich6 when the start bit is written to the command register. bit description 31:2 address of descriptor table (addr) ? r/w. the bits in this field correspond to a[31:2]. the descriptor table must be dword-aligned. the descr iptor table must not cross a 64-k boundary in memory. 1:0 reserved
486 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3 ahci registers (d31:f2) note: these registers are ahci-specific and available only on ich6r and ich6-m when properly configured. the serial ata status, control, and error registers are special exceptions and may be accessed on all ich6 components if properly configured; see section 12.1.31 for details. the memory mapped registers within the sata controller exist in non-cacheable memory space. additionally, locked accesses are not supported. if software attempts to perform locked transactions to the registers, indeterminate re sults may occur. register accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte alignment boundary. the registers are broken into two sections ? generi c host control and port control. the port control registers are the same for all ports, and there are as many registers banks as there are ports. 12.3.1 ahci generic host co ntrol registers (d31:f2) table 12-3. ahci register address map abar + offset mnemonic register 00h?1fh ghc generic host control 20h?ffh ? reserved 100h?17fh p0pcr port 0 port control registers 180h?1ffh p1pcr port 1 port control registers (desktop only) registers are not available and software mu st not read or write registers. (mobile only) 200h?27fh p2pcr port 2 port control registers 280h?2ffh p3pcr port 3 port control registers (desktop only) registers are not available and software mu st not read or write registers. (mobile only) 300h?3ffh ? reserved table 12-4. generic host controller register address map abar + offset mnemonic register default type 00h?03h cap host capabilities c6027f03h r/wo, ro 04h?07h ghc global ich6 control 00000000h r/w 08h?0bh is interrupt status 00000000h r/wc, ro 0ch?0fh pi ports implemented 00000000h r/wo, ro 10h?13h vs ahci version 00010000h ro
intel ? i/o controller hub 6 (ich6) family datasheet 487 sata controller registers (d31:f2) 12.3.1.1 cap?host capabili ties register (d31:f2) address offset: abar + 00h?03h attribute: r/wo, ro default value: c6027f03h size: 32 bits all bits in this register that are r/wo are reset only by pltrst#. bit description 31 supports 64-bit addressing (s64a) ? ro. this bit indicates that the sata controller can access 64-bit data structures. the 32-bit upper bits of the port dma descriptor, the prd base, and each prd entry are read/write. 30 supports command queue acceleration (scqa) ? ro. hardwired to 1 to indicate that the sata controller supports sata command queuing via the dma setup fis. the intel ? ich6 handles dma setup fises natively, and can handle auto- activate optimization through that fis. 29 supports cold presence detect (scd) ? ro. cold presence detect not supported. 28 supports interlock switch (sis) ? r/wo. this bit indicates whet her the sata controller supports interlock switches on its ports for use in hot-plug operations. this value is loaded by platform bios prior to os initialization. if this bit is set, bios must also map the satagp pins to the sata controller through gpio space. 27 supports staggered spin-up (sss) ? r/wo. this bit indicates whether the sata controller supports staggered spin-up on its ports, for use in balancing power spikes. th is value is loaded by platform bios prior to os initialization. 0 = staggered spin-up not supported. 1 = staggered spin-up supported. 26 supports aggressive link power management (salp) ? r/w. 0 = indicates that the sata controller does not s upport auto-generating link requests to the partial or slumber states when there are no commands to process. 1 = indicates that the sata controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. note: for only b-1 step devices, bios must clear this bit. 25 supports activity led (sal) ? ro. this field indicates that t he sata controller supports a single output pin (sataled#) wh ich indicates activity. 24 supports raw fis mode (srm) ? ro. the sata controller does not support raw fis mode. 23:20 interface speed support (iss) ? ro. this field indicates the maximum speed the sata controller can support on its ports. 0h =1.5 gb/s. 19 supports non-zero dma offsets (snzo) ? ro . reserved, as per the ahci revision 1.0 specification 18 supports port selector acceleration ? ro. port selectors not supported. 17 supports port multiplier (pms) ? r/wo. ich6 does not support port multiplier. bios/sw shall write this bit to ?0? during ahci initalization. 16 supports port multiplier fis based switching (p mfs) ? ro. reserved, as per the ahci revision 1.0 specification. 15 reserved. returns 0. 14 slumber state capable (ssc) ? ro. the sata controller supports the slumber state. 13 partial state capable (psc) ? ro. the sa ta controller supports the partial state. 12:8 number of command slots (ncs) ? ro. hardwired to 1fh to indicate support for 32 slots. 7:5 reserved. returns 0. 4:0 number of ports (nps) ? ro. hardwired to 3h to i ndicate support for 4 ports. note that the number of ports indicated in this fiel d may be more than the number of ports indicated in the pi (abar + 0ch) register.
488 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.1.2 ghc?global ich6 c ontrol register (d31:f2) address offset: abar + 04h?07h attribute: r/w default value: 00000000h size: 32 bits bit description 31 ahci enable (ae) ? r/w. when set, this bit indicates that an ahci driver is loaded and the controller will be talked to via ahci mechanisms . this can be used by an ich6 that supports both legacy mechanisms (such as sff-8038i) and ahci to know when the controller will not be talked to as legacy. when set, software will only talk to the ich6 us ing ahci. the ich6 will not have to allow command processing via both ahci and legacy mechanisms. when cleared, software will only talk to the ich6 using legacy mechanisms. software shall set this bit to 1 before accessing other ahci registers. 30:2 reserved. returns 0. 1 interrupt enable (ie) ? r/w. this global bit enables interrupts from the ich6. 0 = all interrupt sources from all ports are disabled. 1 = interrupts are allowed from the ahci controller. 0 hba reset (hr) ? r/w. resets ich6 ahci controller. 0 = no effect 1 = when set by sw, this bit causes an internal reset of the ich6 ahci controller. all state machines that relate to data transfers and queui ng return to an idle condition, and all ports are re-initialized via comreset. note: for further details, consult section 12.3.3 of the serial ata advanced host controller interface specification.
intel ? i/o controller hub 6 (ich6) family datasheet 489 sata controller registers (d31:f2) 12.3.1.3 is?interrupt stat us register (d31:f2) address offset: abar + 08h ? 0bh attribute: r/wc, ro default value: 00000000h size: 32 bits this register indicates which of the ports with in the controller have an interrupt pending and require service. bit description 31:4 reserved. returns 0. 3 (mobile only) reserved. returns 0. 3 (desktop only) interrupt pending status port[3] (ips[3]) ? r/wc . 0 = no interrupt pending. 1 = port 3 has an interrupt pending. software can us e this information to determine which ports require service after an interrupt. 2 interrupt pending status port[2] (ips[2]) ? r/wc 0 = no interrupt pending. 1 = port 2 has an interrupt pending. software can us e this information to determine which ports require service after an interrupt. 1 (mobile only) reserved. returns 0. 1 (desktop only) interrupt pending status port[1] (ips[1]) ? r/wc . 0 = no interrupt pending. 1 = port 1has an interrupt pending. software can use this information to determine which ports require service after an interrupt. 0 interrupt pending status port[0] (ips[0]) ? r/wc . 0 = no interrupt pending. 1 = port 0 has an interrupt pending. software can us e this information to determine which ports require service after an interrupt.
490 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.1.4 pi?ports implemen ted register (d31:f2) address offset: abar + 0c h?0fh attribute: r/wo, ro default value: 00000000h size: 32 bits this register indicates which ports are exposed to the ich6. it is loaded by platform bios. it indicates which ports that the device supports are av ailable for software to use. for ports that are not available, software must not read or write to registers within that port. 12.3.1.5 vs?ahci version (d31:f2) address offset: abar + 10h?13h attribute: ro default value: 00010000h size: 32 bits this register indicates the major and minor version of the ahci specification. it is bcd encoded. the upper two bytes represent the major version number, and the lower two bytes represent the minor version number. example: version 3.12 would be represented as 00030102h. the current version of the specification is 1.0 (00010000h). bit description 31:4 reserved. returns 0. 3 (desktop only) ports implemented port 3 (pi3) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 3 (mobile only) ports implemented port 3 (pi3) ? ro. 0 = the port is not implemented. 2 ports implemented port 2 (pi2) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 1 (desktop only) ports implemented port 1 (pi1) ? r/wo. 0 = the port is not implemented. 1 = the port is implemented. 1 (mobile only) ports implemented port 1 (pi1) ? ro. 0 = the port is not implemented. 0 ports implemented port 0 (pi0) ? r/wo . 0 = the port is not implemented. 1 = the port is implemented. bit description 31:16 major version number (mjr) ? ro. this field indicates the major version is 1 15:0 minor version number (mnr) ? ro. this field indicates the minor version is 0.
intel ? i/o controller hub 6 (ich6) family datasheet 491 sata controller registers (d31:f2) 12.3.2 port registers (d31:f2) table 12-5. port [3:0] dma register address map abar + offset mnemonic register 100?103h p0clb port 0 command list base address 104?107h p0clbu port 0 command list base address upper 32-bits 108?10bh p0fb port 0 fis base address 10c?10fh p0fbu port 0 fis base address upper 32-bits 110?113h p0is port 0 interrupt status 114?117h p0ie port 0 interrupt enable 118?11ch p0cmd port 0 command 11c?11fh ? reserved 120?123h p0tfd port 0 task file data 124?127h p0sig port 0 signature 128?12bh p0ssts port 0 serial ata status 12c?12fh p0sctl port 0 serial ata control 130?133h p0serr port 0 serial ata error 134?137h p0sact port 0 serial ata active 138?13bh p0ci port 0 command issue 13c?17fh ? reserved 180?1ffh (mobile only) ? reserved registers are not available and software must not read from or write to registers. 180?183h p1clb port 1 command list base address 184?187h p1clbu port 1 command list base address upper 32-bits 188?18bh p1fb port 1 fis base address 18c?18fh p1fbu port 1 fis base address upper 32-bits 190?193h p1is port 1 interrupt status 194?197h p1ie port 1 interrupt enable 198?19ch p1cmd port 1 command 19c?19fh ? reserved 1a0?1a3h p1tfd port 1 task file data 1a4?1a7h p1sig port 1 signature 1a8?1abh p1ssts port 1 serial ata status 1ac?1afh p1sctl port 1 serial ata control 1b0?1b3h p1serr port 1 serial ata error 1b4?1b7h p1sact port 1 serial ata active 1b8?1bbh p1ci port 1 command issue 1bc?1ffh ? reserved
492 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 200?203h p2clb port 2 command list base address 204?207h p2clbu port 2 command list base address upper 32-bits 208?20bh p2fb port 2 fis base address 20c?20fh p2fbu port 2 fis base address upper 32-bits 210?213h p2is port 2 interrupt status 214?217h p2ie port 2 interrupt enable 218?21ch p2cmd port 2 command 21c?21fh ? reserved 220?223h p2tfd port 2 task file data 224?227h p2sig port 2 signature 228?22bh p2ssts port 2 serial ata status 22c?22fh p2sctl port 2 serial ata control 230?233h p2serr port 2 serial ata error 234?237h p2sact port 2 serial ata active 238?23bh p2ci port 2 command issue 23c?27fh ? reserved 280?2ffh (mobile only) ? reserved registers are not available and software must not read from or write to registers. 280?283h p3clb port 3 command list base address 284?287h p3clbu port 3 command list base address upper 32-bits 288?28bh p3fb port 3 fis base address 28c?28fh p3fbu port 3 fis base address upper 32-bits 290?293h p3is port 3 interrupt status 294?297h p3ie port 3 interrupt enable 298?29ch p3cmd port 3 command 19c?19fh ? reserved 2a0?2a3h p3tfd port 3 task file data 2a4?2a7h p3sig port 3 signature 2a8?2abh p3ssts port 3 serial ata status 2ac?2afh p3sctl port 3 serial ata control 2b0?2b3h p3serr port 3 serial ata error 2b4?2b7h p3sact port 3 serial ata active 2b8?2bbh p3ci port 3 command issue 2bc?2ffh ? reserved table 12-5. port [3:0] dma register address map abar + offset mnemonic register
intel ? i/o controller hub 6 (ich6) family datasheet 493 sata controller registers (d31:f2) 12.3.2.1 pxclb?port [3:0] comma nd list base a ddress register (d31:f2) address offset: port 0: abar + 100h attribute: r/w, ro port 1: abar + 180h (desktop only) port 2: abar + 200h port 3: abar + 280h (desktop only) default value: undefined size: 32 bits 12.3.2.2 pxclbu?port [3:0] comma nd list base address upper 32-bits register (d31:f2) address offset: port 0: abar + 104h attribute: r/w port 1: abar + 184h (desktop only) port 2: abar + 204h port 3: abar + 284h (desktop only) default value: undefined size: 32 bits 12.3.2.3 pxfb?port [3:0] fis ba se address register (d31:f2) address offset: port 0: abar + 108h attribute: r/w, ro port 1: abar + 188h (desktop only) port 2: abar + 208h port 3: abar + 288h (desktop only) default value: undefined size: 32 bits bit description 31:10 command list base address (clb) ? r/w . this field indicates the 32-bit base for the command list for this port. this base is used when fetching commands to exec ute. the structure pointed to by this address range is 1 kb in length. this addres s must be 1-kb aligned as indicated by bits 31:10 being read/write. note that these bits are not reset on a hba reset. 9:0 reserved ? ro bit description 31:0 command list base address upper (clbu) ? r/w . this field indicates the upper 32-bits for the command list base address for this port. this ba se is used when fetching commands to execute. note that these bits are not reset on a hba reset. bit description 31:8 fis base address (fb) ? r/w . this field indicates the 32-bit base for received fises. the structure pointed to by this address range is 256 bytes in length. this address must be 256-byte aligned, as indicated by bits 31:3 being read/write. note that these bits are not reset on a hba reset. 7:0 reserved ? ro
494 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.2.4 pxfbu?port [3:0] fi s base address upper 32-bits register (d31:f2) address offset: port 0: abar + 10ch attribute: r/w port 1: abar + 18ch port 2: abar + 20ch port 3: abar + 28ch default value: undefined size: 32 bits 12.3.2.5 pxis?port [3 :0] interrupt status register (d31:f2) address offset: port 0: abar + 110h attribute: r/wc, ro port 1: abar + 190h (desktop only) port 2: abar + 210h port 3: abar + 290h (desktop only) default value: 00000000h size: 32 bits bit description 31:3 command list base address upper (clbu) ? r/w . this field indicates the upper 32-bits for the received fis base for this port. note that these bits are not reset on a hba reset. 2:0 reserved bit description 31 cold port detect status (cpds) ? ro . cold presence not supported. 30 task file error status (tfes) ? r/wc. this bit is set whenever the status register is updated by the device and the error bit (pxtfd.bit 0) is set. 29 host bus fatal error status (hbfs) ? r/wc . this bit indicates that the intel ? ich6 encountered an error that it cannot recover from due to a bad so ftware pointer. in pci, such an indication would be a target or master abort. 28 host bus data error status (hbds) ? r/wc . indicates that the ich6 encountered a data error (uncorrectable ecc / parity) when reading from or writing to system memory. 27 interface fatal error status (ifs) ? r/wc . indicates that the ich6 encountered an error on the sata interface which caused the transfer to stop. 26 interface non-fatal error status (infs) ? r/wc. indicates that the ich6 encountered an error on the sata interface but was able to continue operation. 25 reserved 24 overflow status (ofs) ? r/wc . indicates that the ich6 received more bytes from a device than was specified in the prd table for the command. 23 incorrect port multiplier status (ipms) ? r/wc. indicates that the ich6 received a fis from a device whose port multiplier field did not match what was expected. note: port multiplier not supported by ich6. 22 phyrdy change status (prcs) ? ro. when set to 1 indicates the internal phyrdy signal changed state. this bit reflects the state of pxser r.diag.n. unlike most of the other bits in the register, this bit is ro and is only cleared when pxserr.diag.n is cleared. note that the internal phyrdy signal also transiti ons when the port interface enters partial or slumber power management states. partial and slumber must be disabled when surprise removal notification is desired, otherwise the power management state transitions will appear as false insertion and removal events. 21:8 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 495 sata controller registers (d31:f2) 7 device interlock status (dis) ? r/wc. when set, indicates that a platform interlock switch has been opened or closed, which may lead to a change in t he connection state of t he device.this bit is only valid in systems that support an interloc k switch (cap.sis [abar+00:bit 28] set). for systems that do not support an interloc k switch, this bit will always be 0. 6 port connect change status (pcs) ? ro . this bit reflects the state of pxserr.diag.x. (abar+130h/1d0h/230h/2d0h, bit 26) unlike other bits in this register, this bit is only cleared when pxserr.diag.x is cleared. 0 = no change in current connect status. 1 = change in current connect status. 5 descriptor processed (dps) ? r/wc . a prd with the i bit set has transferred all its data. 4 unknown fis interrupt (ufs) ? ro . when set to ?1? indicates that an unknown fis was received and has been copied into system memory. this bit is cleared to ?0? by software clearing the pxserr.diag.f (abar+130h/1d0h/230h/2d0h, bit 25) bit to ?0?. note that this bit does not directly reflect the pxserr.diag.f bit. pxserr.diag.f is set immediately when an unknown fis is detected, whereas this bit is set when the fis is posted to memory. software should wait to act on an unknown fis until this bit is set to ?1? or the two bits may become out of sync. 3 set device bits interrupt (sdbs) ? r/wc . a set device bits fis has been received with the i bit set and has been copied into system memory. 2 dma setup fis interrupt (dss) ? r/wc . a dma setup fis has been received with the i bit set and has been copied into system memory. 1 pio setup fis interrupt (pss) ? r/wc . a pio setup fis has been received with the i bit set, it has been copied into system memory, and the dat a related to that fis has been transferred. 0 device to host register fis interrupt (dhrs) ? r/wc . a d2h register fis has been received with the i bit set, and has been copied into system memory. bit description
496 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.2.6 pxie?port [3 :0] interrupt enable register (d31:f2) address offset: port 0: abar + 114h attribute: r/w, ro port 1: abar + 194h (desktop only) port 2: abar + 214h port 3: abar + 294h (desktop only) default value: 00000000h size: 32 bits this register enables and disables the reporting of the corresponding interrupt to system software. when a bit is set (?1?) and the corresponding interrupt condition is active, then an interrupt is generated. interrupt sources that are disabled (?0?) are still refl ected in the status registers. bit description 31 cold presence detect enable (cpde) ? ro. cold presence detect not supported. 30 task file error enable (tfee) ? r/w . when set, and ghc.ie and pxtfd.sts.err (due to a reception of the error register from a received fis) are set, the intel ? ich6 will generate an interrupt. 29 host bus fatal error enable (hbfe) ? r/w . when set, and ghc.ie and pxs.hbfs are set, the ich6 will generate an interrupt. 28 host bus data error enable (hbde) ? r/w . when set, and ghc.ie and pxs.hbds are set, the ich6 will generate an interrupt. 27 host bus data error enable (hbde) ? r/w. when set, ghc.ie is set, and pxis.hbds is set, the ich6 will generate an interrupt. 26 interface non-fatal error enable (infe) ? r/w. when set, ghc.ie is set, and pxis.infs is set, the ich6 will generate an interrupt. 25 reserved - should be written as 0 24 overflow error enable (ofe) ? r/w . when set, and ghc.ie and pxs.ofs are set, the ich6 will generate an interrupt. 23 incorrect port multiplier enable (ipme) ? r/w. when set, and ghc.ie and pxis.ipms are set, the ich6 will generate an interrupt. note: should be written as 0. port multiplier not supported by ich6. 22 phyrdy change interrupt enable (prce) ? r/w. when set, and ghc.ie is set, and pxis.prcs is set, the ich6 shall generate an interrupt. 21:8 reserved - should be written as 0 7 device interlock enable (die) ? r/w. when set, and pxis.dis is set, the ich6 will generate an interrupt. for systems that do not support an interlock switch, this bit shall be a read-only 0. 6 port change interrupt enable (pce) ? r/w . when set, and ghc.ie and pxs.pcs are set, the ich6 will generate an interrupt. 5 descriptor processed interrupt enable (dpe) ? r/w . when set, and ghc.ie and pxs.dps are set, the ich6 will generate an interrupt 4 unknown fis interrupt enable (ufie) ? r/w . when set, and ghc.ie is set and an unknown fis is received, the ich6 will generate this interrupt. 3 set device bits fis interrupt enable (sdbe) ? r/w . when set, and ghc.ie and pxs.sdbs are set, the ich6 will generate an interrupt. 2 dma setup fis interr upt enable (dse) ? r/w . when set, and ghc.ie and pxs.dss are set, the ich6 will generate an interrupt. 1 pio setup fis interr upt enable (pse) ? r/w . when set, and ghc.ie and pxs.pss are set, the ich6 will generate an interrupt. 0 device to host register fis interrupt enable (dhre) ? r/w . when set, and ghc.ie and pxs.dhrs are set, the ich6 will generate an interrupt.
intel ? i/o controller hub 6 (ich6) family datasheet 497 sata controller registers (d31:f2) 12.3.2.7 pxcmd?port [3:0] command register (d31:f2) address offset: port 0: abar + 118h attribute: r/w, ro, r/wo port 1: abar + 198h (desktop only) port 2: abar + 218h port 3: abar + 298h (desktop only) default value: 0000w00wh size: 32 bits where w = 00?0b (for ?, see bit description) bit description 31:28 interface communication control (icc) ? r/w . this is a four bit field which can be used to control reset and power states of the interface. writes to this field will cause actions on the interface, either as primitives or an oob s equence, and the resulting status of the interface will be reported in the pxssts register (address offset port 0:abar+124h, port 1: abar+1a4h, port 2: abar+224h, port 3: abar+2a4h). when system software writes a non-reserved value ot her than no-op (0h), the ich6 will perform the action and update this field back to idle (0h). if software writes to this field to change the state to a state the link is already in (e.g. interface is in the active state and a request is made to go to t he active state), the ich6 will take no action and return this field to idle. note: when the alpe bit (bit 26) is set, then this register should not be set to 02h or 06h. 27 aggressive slumber / partial (asp) ? r/w . when set, and the alpe bit (bit 26) is set, the ich6 will aggressively enter the slumber state when it cl ears the pxci register and the pxsact register is cleared. when cleared, and the alpe bit is set, the ic h6 will aggressively enter the partial state when it clears the pxci register and the pxsact register is cleared. 26 aggressive link power management enable (alpe) ? r/w . when set, the ich6 will aggressively enter a lower link power state (parti al or slumber) based upon the setting of the asp bit (bit 27). 25 drive led on atapi enable (dlae) ? r/w . when set, the ich6 will drive the led pin active for atapi commands (pxclb[chz.a] set) in addition to ata commands. when cleared, the ich6 will only drive the led pin active for ata commands. see section 5.17.5 for details on the activity led. 24 hdevice is atapi (atapi) ? r/w. when set, the connected device is an atapi device. this bit is used by the ich6 to control whether or not to generate the desktop led when commands are active. see section 5.17.5 for details on the activity led. 23:20 reserved value definition fh?7h reserved 6h slumber: this will cause the intel ? ich6 to request a transition of the interface to the slumber state. the sata device may reject the request and the interface will remain in its current state 5h?3h reserved 2h partial: this will cause the ich6 to request a transition of the interface to the partial state. the sata device may reject the request and the interface will remain in its current state. 1h active: this will cause the ich6 to reques t a transition of the interface into the active 0h no-op / idle: when software reads this valu e, it indicates the ich6 is not in the process of changing the interface state or sending a device reset, and a new link command may be issued.
498 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 19 interlock switch attached to port (isp) ? r/wo. when interlock switches are supported in the platform (cap.sis [abar+00h:bit 28] set), this indica tes whether this particular port has an interlock switch attached. this bit can be used by system software to enable such features as aggressive power management, as disconnects can always be detected regardless of phy state with an interlock switch. when this bit is set, it is expected that hpcp (bit 18) in this register is also set. the ich6 takes no action on the state of this bit ? it is for system software only. for example, if this bit is cleared, and an interlock switch toggles, the i ch6 still treats it as a proper interlock switch event. note that these bits are not reset on a hba reset. 18 hot plug capable port (hpcp) ? r/wo. 0 = port is not capable of hot-plug. 1 = port is hot-plug capable. this indicates whether the platform exposes th is port to a device which can be hot-plugged. sata by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed (it may be screwed into the chassis, for exampl e). this bit can be used by system software to indicate a feature such as "eject device" to t he end-user. the ich6 takes no action on the state of this bit - it is for system software only. for ex ample, if this bit is cleared, and a hot-plug event occurs, the ich6 still treats it as a proper hot-plug event. note that these bits are not reset on a hba reset. 17 port multiplier attached (pma) ? ro / r/w. when this bit is set, a port multiplier is attached to the ich6 for this port. when cleared, a port mu ltiplier is not attached to this port. this bit is ro 0 when cap.pms (offset abar+00h:bit 17) = 0 and r/w when cap.pms = 1. note: port multiplier not supported by ich6. 16 port multipler fis based switching enable (pmf se) ? ro. the ich6 does not support fis-based switching. 15 controller running (cr) ? ro. when this bit is set, the dma engines for a port are running. see section 5.2.2 of the serial ata ahci specification for details on when this bit is set and cleared by the ich6. 14 fis receive running (fr) ? ro. when set, the fis receive dma engine for the port is running. see section 12.2.2 of the serial ata ahci specification for details on when this bit is set and cleared by the ich6. 13 interlock switch state (iss) ? ro. for systems that support interlock switches (via cap.sis [abar+00h:bit 28]), if an interlock switch exists on this port (via isp in this register), this bit indicates the current state of the interlock switch. a 0 indi cates the switch is closed, and a 1 indicates the switch is opened. for systems that do not support interlock switches, or if an interlock switch is not attached to this port, this bit reports 0. 12:8 current command slot (ccs) ? ro . this field indicates the current command slot the ich6 is processing. this field is valid w hen the st bit is set in this regi ster, and is constantly updated by the ich6. this field can be updated as soon as the ich6 recognizes an active command slot, or at some point soon after when it begins processing the command. this field is used by software to determine the current command issue location of the ich6. in queued mode, software shall not use this field, as its value does not represent the current command being executed. software shall only use pxci and pxsact when running queued commands. 7:5 reserved 4 fis receive enable (fre) ? r/w. when set, the ich6 may post received fises into the fis receive area pointed to by pxfb (abar +108h/188h/208h/288h) and pxfbu (abar+10ch/18ch/ 20ch/28ch). when cleared, received fises are not ac cepted by the ich6, except for the first d2h (device-to-host) register fis after the initialization sequence. system software must not set this bit until pxfb (pxfbu) have been programmed with a valid pointer to the fis receive area, and if software wi shes to move the base, this bit must first be cleared, and software must wait for the fr bit (bit 14) in this register to be cleared. 3 port selector activate (psa) ? ro. port selector not supported. defaults to 0. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 499 sata controller registers (d31:f2) 12.3.2.8 pxtfd?port [3 :0] task file data register (d31:f2) address offset: port 0: abar + 120h attribute: ro port 1: abar + 1a0h (desktop only) port 2: abar + 220h port 3: abar + 2a0h (desktop only) default value: 0000007fh size: 32 bits this is a 32-bit register that co pies specific fields of the task file when fises are received. the fises that contain this information are: d2h register fis pio setup fis set device bits fis 2 power on device (pod) ? ro . cold presence detect not supported. defaults to 1. 1 spin-up device (sud) ? r/w / ro this bit is r/w and defaults to 0 for systems that support staggered spin-up (r/w when cap.sss (abar+00h:bit 27) is 1). bit is ro 1 for syst ems that do not support staggered spin-up (when cap.sss is 0). 0 = no action. 1 = on an edge detect from 0 to 1, the ich6 st arts a comreset initialization sequence to the device. 0 start (st) ? r/w . when set, the ich6 may process the command list. when cleared, the ich6 may not process the command list. whenever this bit is changed from a 0 to a 1, the ich6 starts processing the command list at ent ry 0. whenever this bit is c hanged from a 1 to a 0, the pxci register is cleared by the ich6 upon the ich6 putting the controller into an idle state. refer to section 12.2.1 of the serial ata ahci s pecification for important restrictions on when st can be set to 1. bit description bit description 31:16 reserved 15:8 error (err) ? ro . contains the latest copy of the task file error register. 7:0 status (sts) ? ro . contains the latest copy of the task file status register. fields of note in this register that affect ahci. bit field definition 7 bsy indicates the interface is busy 6:4 n/a not applicable 3 drq indicates a data transfer is requested 2:1 n/a not applicable 0 err indicates an error during the transfer
500 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.2.9 pxsig?port [3:0] si gnature register (d31:f2) address offset: port 0: abar + 124h attribute: ro port 1: abar + 1a4h (desktop only) port 2: abar + 224h port 3: abar + 2a4h (desktop only) default value: ffffffffh size: 32 bits this is a 32-bit register which contains the initial signature of an attach ed device when the first d2h register fis is received from that devi ce. it is updated once after a reset sequence. bit description 31:0 signature (sig) ? ro . this field c ontains the signature received from a device on the first d2h register fis. the bit order is as follows: bit field 31:24 lba high register 23:16 lba mid register 15:8 lba low register 7:0 sector count register
intel ? i/o controller hub 6 (ich6) family datasheet 501 sata controller registers (d31:f2) 12.3.2.10 pxssts?port [3:0] serial ata status register (d31:f2) address offset: port 0: abar + 128h attribute: ro port 1: abar + 1a8h (desktop only) port 2: abar + 228h port 3: abar + 2a8h (desktop only) default value: 00000000h size: 32 bits this is a 32-bit register that conveys the current state of the interface and host. the ich6 updates it continuously and asynchronously. when the ich6 transmits a comreset to the device, this register is updated to its reset values. bit description 31:12 reserved 11:8 interface power management (ipm) ? ro . this field indicates the current interface state: all other values reserved. 7:4 current interface speed (spd) ? ro. this field indicates the negotiated interface communication speed. all other values reserved. ich6 supports only generation 1 communication rates (1.5 gb/sec). 3:0 device detection (det) ? ro . this field indicates the interf ace device detection and phy state: all other values reserved. value description 0h device not present or co mmunication not established 1h interface in active state 2h interface in partial power management state 6h interface in slumber power management state value description 0h device not present or co mmunication not established 1h generation 1 communication rate negotiated value description 0h no device detected and phy communication not established 1h device presence detected but phy communication not established 3h device presence detected and phy communication established 4h phy in offline mode as a result of the interface being disabled or running in a bist loopback mode
502 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.2.11 pxsctl?port [3:0] serial ata control re gister (d31:f2) address offset: port 0: abar + 12ch attribute: r/w, ro port 1: abar + 1ach (desktop only) port 2: abar + 22ch port 3: abar + 2ach (desktop only) default value: 00000004h size: 32 bits this is a 32-bit read-write regi ster by which software controls sata capabilities. writes to the scontrol register result in an action being take n by the ich6 or the interface. reads from the register return the last value written to it. bit description 31:20 reserved 19:16 port multiplier port (pmp) ? ro . this field is not used by ahci 15:12 select power management (spm) ? ro . this field is not used by ahci 11:8 interface power management transitions allowed (ipm) ? r/w . this field indicates which power states the ich6 is allowed to transition to: all other values reserved 7:4 speed allowed (spd) ? r/w. indicates the highest allowable speed of the interface. this speed is limited by the cap.iss (abar+00h:bit 23:20) field. all other values reserved note: ich6 supports only generation 1 communication rates (1.5 gb/sec). 3:0 device detection initialization (det) ? r/w . this field c ontrols the ich6?s device detection and interface initialization. all other values reserved. when this field is written to a 1h, the ich6 init iates comreset and starts the initialization process. when the initialization is complete, this field s hall remain 1h until set to another value by software. this field may only be changed to 1h or 4h when pxcmd. st is 0. changing this field while the ich6 is running results in undefined behavior. value description 0h no interface restrictions 1h transitions to the partial state disabled 2h transitions to the slumber state disabled 3h transitions to both partial and slumber states disabled value description 0h no speed negotiation restrictions 1h limit speed negotiation to g eneration 1 communication rate value description 0h no device detection or initialization action requested 1h perform interface communication in itialization sequence to establish communication. this is functional ly equivalent to a hard reset and results in the interface being re set and communications re-initialized 4h disable the serial ata interface and put phy in offline mode
intel ? i/o controller hub 6 (ich6) family datasheet 503 sata controller registers (d31:f2) 12.3.2.12 pxserr?port [3:0] serial ata error register (d31:f2) address offset: port 0: abar + 130h attribute: r/wc port 1: abar + 1b0h (desktop only) port 2: abar + 230h port 3: abar + 2b0h (desktop only) default value: 00000000h size: 32 bits bit description 31:16 diagnostics (diag) ? r/wc . this field c ontains diagnostic error inform ation for use by diagnostic software in validating correct oper ation or isolatin g failure modes: bits description 31:27 reserved 26 exchanged (x) : when set to one this bit indicates a cominit signal was received. this bit is reflected in the interrupt register pxis.pcs. 25 unrecognized fis type (f) : indicates that one or more fiss were received by the transport layer with good crc, but had a type field that was not recognized. 24 transport state transition error (t) : indicates that an error has occurred in the transition from one state to another within the transport la yer since the last time this bit was cleared. 23 link sequence error (s) : indicates that one or more link state machine error conditions was encountered. the link layer state mach ine defines the condi tions under which the link layer detects an erroneous transition. 22 handshake error (h) : indicates that one or more r_err handshake response was received in response to frame transmission. such errors may be the result of a crc error detected by the recipient, a di sparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame. 21 crc error (c) : indicates that one or more crc er rors occurred with the link layer. 20 disparity error (d) : this field is not used by ahci. 19 10b to 8b decode error (b) : indicates that one or more 10b to 8b decoding errors occurred. 18 comm wake (w) : indicates that a comm wake signal was detected by the phy. 17 phy internal error (i) : indicates that the phy detected some internal error. 16 phyrdy change (n) : when set to 1 this bit indicates that the internal phyrdy signal changed state since the last time this bit was clea red. in the ich6, this bit will be set when phyrdy changes from a 0 -> 1 or a 1 -> 0. t he state of this bit is then reflected in the pxis.prcs interrupt status bit and an interrupt will be generated if enabled. software clears this bit by writing a 1 to it.
504 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2) 12.3.2.13 pxsact?port [3:0] serial ata active (d31:f2) address offset: port 0: abar + 134h attribute: r/w port 1: abar + 1b4h (desktop only) port 2: abar + 234h port 3: abar + 2b4h (desktop only) default value: 00000000h size: 32 bits 15:0 error (err) ? r/wc . the err field contains error inform ation for use by host software in determining the appropriate response to the error condition. if one or more of bits 11:8 of this register ar e set, the controller will stop the current transfer. bits description 15:12 reserved 11 internal error (e) : the sata controller failed due to a master or target abort when attempting to access system memory. 10 protocol error (p) : a violation of the serial ata prot ocol was detected. note: the ich6 does not set this bit for all protocol viol ations that may occur on the sata link. 9 persistent communication or data integrity error (c) : a communication error that was not recovered occurred that is expected to be persistent. persistent communications errors may arise from faulty interconnect wi th the device, from a device that has been removed or has failed, or a number of other causes. 8 transient data integrity error (t) : a data integrity error occurred that was not recovered by the interface. 7:2 reserved 1 recovered communications error (m) : communications between the device and host was temporarily lost but was re-established. this can arise from a device temporarily being removed, from a temporary loss of phy synchronization, or from other causes and may be derived from the phynrdy signal between the phy and link layers. 0 recovered data integrity error (i) : a data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. bit description bit description 31:0 device status (ds) ? r/w . system software sets this bit for sata queuing operations prior to setting the pxci.ci bit in the same command slot entry . this field is cleared vi a the set device bits fis. this field is also cleared when pxcmd.st (abar+118h/198h/218h/298h:bit 0) is cleared by software, and as a result of a comreset or srst.
intel ? i/o controller hub 6 (ich6) family datasheet 505 sata controller registers (d31:f2) 12.3.2.14 pxci?port [3:0] comma nd issue register (d31:f2) address offset: port 0: abar + 138h attribute: r/w port 1: abar + 1b8h (desktop only) port 2: abar + 238h port 3: abar + 2b8h (desktop only) default value: 00000000h size: 32 bits bit description 31:0 commands issued (ci) ? r/w . this field is set by software to i ndicate to the ich6 that a command has been built-in system memory for a command slot and may be sent to the device. when the ich6 receives a fis which clears the bsy and drq bits for the command, it clears the corresponding bit in this register for that command slot. this field is also cleared when pxcmd.st (abar+118h/198h/218h/298h:bit 0) is cleared by software.
506 intel ? i/o controller hub 6 (i ch6) family datasheet sata controller registers (d31:f2)
intel ? i/o controller hub 6 (ich6) family datasheet 507 uhci controllers registers 13 uhci controllers registers 13.1 pci configuration registers (usb?d29:f0/f1/f2/f3) note: register address locations that are not shown in table 13-1 and should be treated as reserved (see section 6.2 for details). note: refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register table 13-1. uhci controller pci regist er address map (usb?d29:f0/f1/f2/f3) offset mnemonic register name function 0 default function 1 default function 2 default function 3 default type 00?01h vid vendor identification 8086h 8086h 8086h 8086h ro 02?03h did device identification 2658h 2659h 265ah 265bh ro 04?05h pcicmd pci command 0000h 0000h 0000h 0000h r/w, ro 06?07h pcists pci status 0280h 0280h 0280h 0280h r/wc, ro 08h rid revision identification see register description. see register description. see register description. see register description. ro 09h pi programming interface 00h 00h 00h 00h ro 0ah scc sub class code 03h 03h 03h 03h ro 0bh bcc base class code 0ch 0ch 0ch 0ch ro 0dh mlt master latency timer 00h 00h 00h 00h ro 0eh headtyp header type 80h 00h 00h 00h ro 20?23h base base address 00000001h 00000001h 00000001h 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h 0000h 0000h 0000h r/wo 2e?2fh sid subsystem identification 0000h 0000h 0000h 0000h r/wo 3ch int_ln interrupt line 00h 00h 00h 00h r/w 3dh int_pn interrupt pin see register description. see register description. see register description. see register description. ro 60h usb_relnum serial bus release number 10h 10h 10h 10h ro c0?c1h usb_legkey usb legacy keyboard/ mouse control 2000h 2000h 2000h 2000h r/w, ro r/wc c4h usb_res usb resume enable 00h 00h 00h 00h r/w c8h cwp core well policy 00h 00h 00h 00h r/w
508 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.1.1 vid?vendor identification register (usb?d29:f0/f1/f2/f3) address offset: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 13.1.2 did?device identification register (usb?d29:f0/f1/f2/f3) address offset: 02 ? 03h attribute: ro default value: uhci #1 = 2658h size: 16 bits uhci #2 = 2659h uhci #3 = 265ah uhci #4 = 265bh 13.1.3 pcicmd?pci command re gister (usb?d29:f0/f1/f2/f3) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel bit description 15:0 device id ? ro. this is a 16-bit value assigned to the ich6 usb host controllers bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable. the function is able to generate its interrupt to the interrupt controller. 1 = disable. the function is not capable of generating interrupts. note: the corresponding interrupt status bit is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable ? ro. reserved as 0. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disable 1 = enable. ich6 can act as a mast er on the pci bus for usb transfers. 1 memory space enable (mse) ? ro. hardwired to 0. 0 i/o space enable (iose) ? r/w. this bit controls acce ss to the i/o space registers. 0 = disable 1 = enable accesses to the usb i/o registers. the base address register for usb should be programmed before this bit is set.
intel ? i/o controller hub 6 (ich6) family datasheet 509 uhci controllers registers 13.1.4 pcists?pci status regi ster (usb?d29:f0/f1/f2/f3) address offset: 06 ? 07h attribute: r/wc, ro default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. writing a 0 to the bit has no effect. 13.1.5 rid?revision id entification register (usb?d29:f0/f1/f2/f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when a data parity error data parity error is detected on writes to the uhci register space or on read completions returned to the host controller. 14 reserved as 0b. read only. 13 received master abort (rma) ? r/wc. 0 = no master abort generated by usb. 1 = usb, as a master, generated a master abort. 12 reserved. always read as 0. 11 signaled target abort (sta) ? r/wc. 0 = ich6 did not terminate transaction for usb function with a target abort. 1 = usb function is targeted with a transaction t hat the ich6 terminates with a target abort. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. these read only bits indicate the ich6's devsel# timing when performing a positive decode. ich6 generates devsel# with medium timing for usb. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable ? ro. hardwired to 0. 4 capabilities list ? ro. hardwired to 0. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = interrupt is de-asserted. 1 = interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register
510 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.1.6 pi?programming interface register (usb?d29:f0/f1/f2/f3) address offset: 09h attribute: ro default value: 00h size: 8 bits 13.1.7 scc?sub class code register (usb?d29:f0/f1/f2/f3) address offset: 0ah attribute: ro default value: 03h size: 8 bits 13.1.8 bcc?base class code register (usb?d29:f0/f1/f2/f3) address offset: 0bh attribute: ro default value: 0ch size: 8 bits 13.1.9 mlt?master latency timer register (usb?d29:f0/f1/f2/f3) address offset: 0dh attribute: ro default value: 00h size: 8 bits bit description 7:0 programming interface ? ro. 00h = no specific register level programming interface defined. bit description 7:0 sub class code (scc) ? ro. 03h = usb host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller. bit description 7:0 master latency timer (mlt) ? ro. the usb controller is implemented internal to the ich6 and not arbitrated as a pci device. therefore the dev ice does not require a master latency timer.
intel ? i/o controller hub 6 (ich6) family datasheet 511 uhci controllers registers 13.1.10 headtyp?header type register (usb?d29:f0/f1/f2/f3) address offset: 0eh attribute: ro default value: fn 0: 80h size: 8 bits fn 1: 00h fn 2: 00h fn 3: 00h for functions 1, 2, and 3, this register is hardwired to 00h. for function 0, bit 7 is determined by the values in the usb function disable bits (11:8 of the function disable register chipset configuration registers:offset 3418h). 13.1.11 base?base address register (usb?d29:f0/f1/f2/f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32 bits bit description 7 multi-function device ? ro. 0 = single-function device. 1 = multi-function device. since the upper functions in this device can be individual ly hidden, this bit is based on the function- disable bits in chipset configurat ion space:offset 3418h as follows: 6:0 configuration layout. hardwired to 00h, which indicates the standard pc i configuration layout. d29:f7_disable (bit 15) d29:f3_disable (bit 11) d29:f2_disable (bit10) d29:f1_disable (bit 9) multi-function device (this bit) 0b x x x 1 x0bx x 1 xx0bx 1 xxx0b1 11110 bit description 31:16 reserved 15:5 base address ? r/w. bits [15:5] correspond to i/o addres s signals ad [15:5], respectively. this gives 32 bytes of relocatable i/o space. 4:1 reserved 0 resource type indicator (rte) ? ro. hardwired to 1 to indicate that the base address field in this register maps to i/o space.
512 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.1.12 svid ? subsystem vend or identification register (usb?d29:f0/f1/f2/f3) address offset: 2ch?2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 13.1.13 sid ? subsystem identification register (usb?d29:f0/f1/f2/f3) address offset: 2eh ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core 13.1.14 int_ln?interrupt line register (usb?d29:f0/f1/f2/f3) address offset: 3ch attribute: r/w default value: 00h size: 8 bits bit description 15:0 subsystem vendor id (svid) ? r/wo. bios sets the value in this register to identify the subsystem vendor id. the usb_svid register, in co mbination with the usb subsystem id register, enables the operating system to distinguish each subsystem from the others. note: the software can write to this register only once per core well reset. writes should be done as a single, 16-bit cycle. bit description 15:0 subsystem id (sid) ? r/wo. bios sets the value in this r egister to identify the subsystem id. the sid register, in combination with the svid regi ster (d29:f0/f1/f2/f3:2c), enables the operating system to distinguish each subsystem from other(s). the value r ead in this register is the same as what was written to the ide_sid register. note: the software can write to this register only once per core well reset. writes should be done as a single, 16-bit cycle. bit description 7:0 interrupt line (int_ln) ? ro. this data is not used by the ich6. it is to communicate to software the interrupt line that the interrupt pin is connected to.
intel ? i/o controller hub 6 (ich6) family datasheet 513 uhci controllers registers 13.1.15 int_pn?interru pt pin register (usb?d29:f0/f1/f2/f3) address offset: 3dh attribute: ro default value: function 0: see description size: 8 bits function 1: see description function 2: see description function 3: see description 13.1.16 usb_relnum?serial bu s release number register (usb?d29:f0/f1/f2/f3) address offset: 60h attribute: ro default value: 10h size: 8 bits bit description 7:0 interrupt line (int_ln) ? ro. this value tells the software which interrupt pin each usb host controller uses. the upper 4 bits are hardwired to 0000b; the lower 4 bits are determine by the interrupt pin default values that are programm ed in the memory-mapped configuration space as follows: function 0 d29ip.u0p (chipset configurat ion registers:offset 3108:bits 3:0) function 1 d29ip.u1p (chipset configurat ion registers:offset 3108:bits 7:4) function 2 d29ip.u2p (chipset configurat ion registers:offset 3108:bits 11:8) function 3 d29ip.u3p (chipset configurat ion registers:offset 3108:bits 15:12) note: this does not determine the mapping to the pirq pins. bit description 7:0 serial bus release number ? ro. 10h = usb controller is compliant with the usb specification , release 1.0.
514 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.1.17 usb_legkey?usb legacy keyboard/mouse control register (usb?d29:f0/f1/f2/f3) address offset: c0 ? c1h attribute: r/w, r/wc, ro default value: 2000h size: 16 bits this register is implemented separately in each of the usb uhci functions . however, the enable and status bits for the trapping lo gic are or?d and shared, respectivel y, since their functionality is not specific to any one host controller. bit description 15 smi caused by end of pass-through (smibyendps) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred 14 reserved 13 pci interrupt enable (usbpirqen) ? r/w. this bit is used to prevent the usb controller from generating an interrupt due to transactions on its ports. note that, when disabl ed, it will probably be configured to generate an smi using bit 4 of this register. default to 1 for compatibility with older usb software. 0 = disable 1 = enable 12 smi caused by usb interrupt (smibyusb) ? ro. this bit indicates if an interrupt event occurred from this controller. the interrupt from the cont roller is taken before the enable in bit 13 has any effect to create this read-only bit. note that even if the corresponding enable bit is not set in bit 4, this bit may still be active. it is up to the smm code to use the enable bit to determine the exact cause of the smi#. 0 = software should clear the interrupts via the usb co ntrollers. writing a 1 to this bit will have no effect. 1 = event occurred. 11 smi caused by port 64 write (trapby64w) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. it is up to the smm code to use the enable bit to determine th e exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 10 smi caused by port 64 read (trapby64r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. it is up to the smm code to use the enable bit to det ermine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 9 smi caused by port 60 write (trapby60w) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. it is up to the smm code to use the enable bit to determine th e exact cause of the smi#. note that the a20gate pass-through logic allows specific port 64h writes to complete without setting this bit. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred. 8 smi caused by port 60 read (trapby60r) ? r/wc. this bit indicates if the event occurred. note that even if the corresponding enable bit is not set in the bit 0, then this bi t will still be active. it is up to the smm code to use the enable bi t to determine the exact cause of the smi#. 0 = software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = event occurred.
intel ? i/o controller hub 6 (ich6) family datasheet 515 uhci controllers registers 13.1.18 usb_res?usb re sume enable register (usb?d29:f0/f1/f2/f3) address offset: c4h attribute: r/w default value: 00h size: 8 bits 7 smi at end of pass-through enable (smiatendps) ? r/w. this bit enables smi at the end of a pass-through. this can occur if an smi is gener ated in the middle of a pass-through, and needs to be serviced later. 0 = disable 1 = enable 6 pass through state (pstate) ? ro. 0 = if software needs to reset this bit, it shoul d set bit 5 in all of the host controllers to 0. 1 = indicates that the state machine is in the middle of an a20gate pass-through sequence. 5 a20gate pass-through enable (a20passen) ? r/w. 0 = disable. 1 = enable. allows a20gate sequence pass-thr ough function. a spec ific cycle sequence involving writes to port 60h and 64h does not result in the setting of the smi status bits. 4 smi on usb irq enable (usbsmien) ? r/w. 0 = disable 1 = enable. usb interrupt will cause an smi event. 3 smi on port 64 writes enable (64wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 11 will cause an smi event. 2 smi on port 64 reads enable (64ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 10 will cause an smi event. 1 smi on port 60 writes enable (60wen) ? r/w. 0 = disable 1 = enable. a 1 in bit 9 will cause an smi event. 0 smi on port 60 reads enable (60ren) ? r/w. 0 = disable 1 = enable. a 1 in bit 8 will cause an smi event. bit description bit description 7:2 reserved 1 port1en ? r/w. enable port 1 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events. 0 port0en ? r/w. enable port 0 of the usb controller to respond to wakeup events. 0 = the usb controller will not look at this port for a wakeup event. 1 = the usb controller will monitor this port for remote wakeup and connect/disconnect events.
516 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.1.19 cwp?core well policy register (usb?d29:f0/f1/f2/f3) address offset: c8h attribute: r/w default value: 00h size: 8 bits 13.2 usb i/o registers some of the read/write register bi ts that deal with changing the state of the usb hub ports function such that on read back they reflect the current state of the port, a nd not necessarily the state of the last write to the register. this allows the software to poll the state of the port and wait until it is in the proper state before proceedin g. a host controller reset, gl obal reset, or port reset will immediately terminate a transfer on the affected ports and disa ble the port. this affects the usbcmd register, bit 4 and the portsc registers, bits [12,6,2]. see individual bit descriptions for more detail. notes: 1. these registers are word writable only. byte wr ites to these registers have unpredictable effects. bit description 7:1 reserved 0 static bus master status policy enable (sbmspe) ? r/w. 0 = the uhci host controller dynamically sets th e bus master status bit (power management 1 status register,[pmbase+00h], bit 4) based on t he memory accesses that are scheduled. the default setting provides a more accurate indicati on of snoopable memory accesses in order to help with software-invoked entry to c3 and c4 power states 1 = the uhci host controller statically forces the bus master status bit in power management space to 1 whenever the hchalted bit (usb status register, base+02h, bit 5) is cleared. note: the pci power management registers are enabled in the pci device 31: function 0 space (pm_io_en), and can be moved to an y i/o location (128-byte aligned). table 13-2. usb i/o registers base + offset mnemonic register name default type 00?01h usbcmd usb command 0000h r/w 02?03h usbsts usb status 0020h r/wc 04?05h usbintr usb interrupt enable 0000h r/w 06?07h frnum frame number 0000h r/w (see note 1) 08?0bh frbaseadd frame list base address undefined r/w 0ch sofmod start of frame modify 40h r/w 0d?0fh ? reserved ? ? 10?11h portsc0 port 0 status/control 0080h r/wc, ro, r/w (see note 1) 12?13h portsc1 port 1 status/control 0080h r/wc, ro, r/w (see note 1)
intel ? i/o controller hub 6 (ich6) family datasheet 517 uhci controllers registers 13.2.1 usbcmd?usb command register i/o offset: base + (00 ? 01h) attribute: r/w default value: 0000h size: 16 bits the command register indicates th e command to be executed by th e serial bus host controller. writing to the register causes a co mmand to be executed. the table following the bit description provides additional information on the operation of the run/stop and debug bits. bit description 15:7 reserved 8 loop back test mode ? r/w. 0 = disable loop back test mode. 1 = ich6 is in loop back test mode. when both ports are connected together, a write to one port will be seen on the other port and the data will be stored in i/o offset 18h. 7 max packet (maxp) ? r/w. this bit selects the maximum packet size that can be used for full speed bandwidth reclamation at the end of a frame. th is value is used by the host controller to determine whether it should initiate another trans action based on the time remaining in the sof counter. use of reclamation packets larger than t he programmed size will cause a babble error if executed during the critical window at frame end. the babble error results in the offending endpoint being stalled. software is responsible for ensuri ng that any packet wh ich could be executed under bandwidth reclamation be within this size limit. 0 = 32 bytes 1 = 64 bytes 6 configure flag (cf) ? r/w. this bit has no effect on the hardw are. it is provided only as a semaphore service for software. 0 = indicates that software has not co mpleted host controller configuration. 1 = hcd software sets this bit as the last action in its process of confi guring the host controller. 5 software debug (swdbg) ? r/w. the swdbg bit must only be manipulated when the controller is in the stopped state. this can be determined by checking the hchalted bit in the usbsts register. 0 = normal mode. 1 = debug mode. in sw debug mode, the host controller clears the run/stop bit after the completion of each usb transaction. the next trans action is executed when software sets the run/stop bit back to 1. 4 force global resume (fgr) ? r/w. 0 = software resets this bit to 0 after 20 ms has elapsed to stop sending the global resume signal. at that time all usb devices s hould be ready for bus activity. t he 1 to 0 transition causes the port to send a low speed eop signal. this bit wi ll remain a 1 until the eop has completed. 1 = host controller sends the global resume si gnal on the usb, and sets this bit to 1 when a resume event (connect, disconnect, or k-state) is detected while in global suspend mode. 3 enter global suspend mode (egsm) ? r/w. 0 = software resets this bit to 0 to come out of global suspend mode. software writes this bit to 0 at the same time that force global resume (bit 4) is written to 0 or after writing bit 4 to 0. 1 = host controller enters the global suspend mode. no usb transactions occur during this time. the host controller is able to receive resume signals from usb and interrupt the system. software must ensure that the run/stop bit (b it 0) is cleared prior to setting this bit.
518 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 2 global reset (greset) ? r/w. 0 = this bit is reset by the software after a minimu m of 10 ms has elapsed as specified in chapter 7 of the usb specification. 1 = global reset. the host controller sends the gl obal reset signal on the usb and then resets all its logic, including the internal hub registers. the hub registers are reset to their power on state. chip hardware reset has the same effect as global reset (bit 2), except that the host controller does not send the global reset on usb. 1 host controller reset (hcreset) ? r/w. the effects of hcreset on h ub registers are slightly different from chip hardware reset and global usb reset. the hcreset affects bits [8,3:0] of the port status and control register (portsc) of each port. hcreset resets the state machines of the host controller including the connect/disconnec t state machine (one for each port). when the connect/disconnect state machine is reset, the output that signals c onnect/disconnect are negated to 0, effectively signaling a disconnect, even if a device is attached to the port. this virtual disconnect causes the port to be disabled. this di sconnect and disabling of the port causes bit 1 (connect status change) and bit 3 (port enable/d isable change) of the portsc (d29:f0/f1/f2/ f3:base + 10h) to get set. the disconnect also causes bit 8 of portsc to reset. about 64 bit times after hcreset goes to 0, the connect and low-speed detect will take place, and bits 0 and 8 of the portsc will change accordingly. 0 = reset by the host controller when the reset process is complete. 1 = reset. when this bit is set, the host controller module resets its internal timers, counters, state machines, etc. to their initial value. any trans action currently in progress on usb is immediately terminated. 0 run/stop (rs) ? r/w. when set to 1, the ich6 proceeds with execution of the schedule. the ich6 continues execution as l ong as this bit is set. when this bit is cleared, the ich6 completes the current transaction on the usb and then halts. the hc halted bit in the status register indicates when the host controller has fi nished the transaction and has entered the stopped state. the host controller clears this bit when the following fatal errors occur: consistency check failure, pci bus errors. 0 = stop 1 = run note: this bit should only be cleared if there are no active transaction descriptors in the executable schedule or software will reset the host controller prior to setting this bit again. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 519 uhci controllers registers when the usb host controller is in software de bug mode (usbcmd register bit 5=1), the single stepping software debug operation is as follows: to enter software debug mode: 1. hcd puts host controller in stop state by setting the run/stop bit to 0. 2. hcd puts host controller in debug mode by setting the swdbg bit to 1. 3. hcd sets up the correct command list and start of frame value for starting point in the frame list single step loop. 4. hcd sets run/stop bit to 1. 5. host controller executes next active td, sets run/stop bit to 0, and stops. 6. hcd reads the usbcmd register to check if the single step execution is completed (hchalted=1). 7. hcd checks results of td execution. go to st ep 4 to execute next td or step 8 to end software debug mode. 8. hcd ends software debug mode by setting swdbg bit to 0. 9. hcd sets up normal command list and frame list table. 10. hcd sets run/stop bit to 1 to resume normal schedule execution. in software debug mode, when the run/stop bit is set, the host controller starts. when a valid td is found, the run/stop bit is reset. when the td is finished, the hchalted bit in the usbsts register (bit 5) is set. the sw debug mode skips over inactive tds and only halts after an active td has been executed. when the last active td in a frame has been execu ted, the host controller waits until the next sof is sent and then fetches the first td of the next frame before halting. this hchalted bit can also be used outside of software debug mode to indicate when the host controller has detected the run/stop bit and has completed the current tran saction. outside of the software debug mode, setting the run/stop bit to 0 always resets the sof counter so that when the run/stop bit is set the host controller starts over again from the frame list location pointed to by the frame list index (see frnum register description) rather than continuing where it stopped. table 13-3. run/stop, debug bit interaction sw dbg (bit 5), run/stop (bit 0) operation swdbg (bit 5) run/stop (bit 0) description 00 if executing a command, the host controller completes the command and then stops. the 1.0 ms frame counter is re set and command list execution resumes from start of frame using the frame list pointer selected by the current value in the frnum register. (while run/stop=0, the frnum register (d29:f0/f1/f2/ f3:base + 06h) can be reprogrammed). 01 execution of the command list resumes fr om start of frame using the frame list pointer selected by the current value in the frnum register. the host controller remains running until the run/stop bit is cleared (by software or hardware). 10 if executing a command, the host controller completes the command and then stops and the 1.0 ms frame counter is froz en at its current value. all status are preserved. the host controller begins ex ecution of the command list from where it left off when the run/stop bit is set. 11 execution of the command list resumes from where the previous execution stopped. the run/stop bit is set to 0 by the host controller when a td is being fetched. this causes the host controller to stop again after the execution of the td (single step). when the host controll er has completed execution, the hc halted bit in the status register is set.
520 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.2.2 usbsts?usb status register i/o offset: base + (02 ? 03h) attribute: r/wc default value: 0020h size: 16 bits this register indicates pending interrupts and va rious states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. bit description 15:6 reserved 5 hchalted ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller has stopped executing as a resu lt of the run/stop bit being set to 0, either by software or by the host controller hardware (debug mode or an internal error). default. 4 host controller process error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller has detected a fatal error. th is indicates that the host controller suffered a consistency check failur e while processing a transfer descri ptor. an example of a consistency check failure would be finding an illegal pid field while processing the packet header portion of the td. when this error occurs, the host c ontroller clears the run/stop bit in the command register (d29:f0/f1/f2/f3:base + 00h, bit 0) to prevent fu rther schedule execution. a hardware interrupt is generated to the system. 3 host system error ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = a serious error occurred during a host system ac cess involving the host controller module. in a pci system, conditions that set this bit to 1 in clude pci parity error, pci master abort, and pci target abort. when this error occurs, the hos t controller clears the run/stop bit in the command register to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system. 2 resume detect (rsm_det) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller received a ?resume? signal fr om a usb device. this is only valid if the host controller is in a gl obal suspend state (command register, d29:f0/f1/f2/f3:base + 00h, bit 3 = 1). 1 usb error interrupt ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = completion of a usb transaction resulted in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit (d29:f0/f1/f2/f3:base + 04h, bit 2) set, both this bit and bit 0 are set. 0 usb interrupt (usbint) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the host controller sets this bit when the cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its io c bit set. also set when a short packet is detected (actual length field in td is less t han maximum length field in td), and short packet detection is enabled in that td.
intel ? i/o controller hub 6 (ich6) family datasheet 521 uhci controllers registers 13.2.3 usbintr?usb inte rrupt enable register i/o offset: base + (04 ? 05h) attribute: r/w default value: 0000h size: 16 bits this register enables and disables reporting of the corresponding in terrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. fatal errors (host controller processor error, (d29:f0/f1/f2/f3:base + 02h, bit 4, usbsts register) cannot be disabled by the host controller. interrupt sources th at are disabled in this register still appear in the status register to allow the software to poll for events. 13.2.4 frnum?frame number register i/o offset: base + (06 ? 07h) attribute: r/w (writes must be word writes) default value: 0000h size: 16 bits bits [10:0] of this register co ntain the current frame number that is included in the frame sof packet. this register reflects the count value of th e internal frame number counter. bits [9:0] are used to select a particular entr y in the frame list during schedu led execution. this register is updated at the end of each frame time. this register must be written as a word. byte wr ites are not supported. this register cannot be written unless the host controller is in the stopped state as indicated by the hchalted bit (d29:f0/f1/f2/f3:base + 02h, bit 5). a write to this register while the run/stop bit is set (d29:f0/f1/f2/f3:base + 00h, bit 0) is ignored. bit description 15:5 reserved 4 scratchpad (sp) ? r/w. 3 short packet interrupt enable ? r/w. 0 = disabled. 1 = enabled. 2 interrupt on complete enable (ioc) ? r/w. 0 = disabled. 1 = enabled. 1 resume interrupt enable ? r/w. 0 = disabled. 1 = enabled. 0 timeout/crc interrupt enable ? r/w. 0 = disabled. 1 = enabled. bit description 15:11 reserved 10:0 frame list current index/frame number ? r/w. this field provides the frame number in the sof frame. the value in this register increment s at the end of each time frame (approximately every 1 ms). in addition, bits [9:0] are used for the frame list current index and correspond to memory address signals [11:2].
522 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.2.5 frbaseadd?frame li st base address register i/o offset: base + (08 ? 0bh) attribute: r/w default value: undefined size: 32 bits this 32-bit register contains the beginning address of the frame list in the system memory. hcd loads this register prior to starting the schedule execution by the host contro ller. when written, only the upper 20 bits are used. the lower 12 bits are written as 0?s (4-kb ali gnment). the contents of this register are combin ed with the frame number counter to en able the host controller to step through the frame list in sequence. the two least significant bits are always 00. this requires dword-alignment for all list entries. this configuration supports 1024 frame list entries. bit description 31:12 base address ? r/w. these bits correspond to memo ry address signals [31:12], respectively. 11:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 523 uhci controllers registers 13.2.6 sofmod?start of frame modify register i/o offset: base + (0ch) attribute: r/w default value: 40h size: 8 bits this 1-byte register is used to modify the value used in the generation of sof timing on the usb. only the 7 least significant bits are used. when a new value is written into these 7 bits, the sof timing of the next frame will be ad justed. this feature can be used to adjust out any offset from the clock source that generates the clock that drives the sof counter. this register can also be used to maintain real time synchronization with the rest of the system so that all devices have the same sense of real time. using this register, the fram e length can be adjusted across the full range required by the usb specification. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. it may be reprogrammed by usb system software at any time. its value will take effect from the beginn ing of the next frame. this register is reset upon a host controller reset or global reset. software must maintain a copy of its value for reprogramming if necessary. bit description 7 reserved 6:0 sof timing value ? r/w. guidelines for t he modification of frame time are contained in chapter 7 of the usb specification. the sof cycle time ( number of sof counter clock periods to generate a sof frame length) is equal to 11936 + value in this field. the default value is decimal 64 which gives a sof cycle time of 12000. for a 12 mhz sof count er clock input, this produces a 1 ms frame period. the following table indicates what sof timi ng value to program into this field for a certain frame period. frame length (# 12 mhz clocks) (decimal) sof timing value (this register) (decimal) 11936 0 11937 1 ?? 11999 63 12000 64 12001 65 ?? 12062 126 12063 127
524 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers 13.2.7 portsc[0,1]?port st atus and control register i/o offset: port 0/2/4/6: base + (10 ? 11h) attribute: r/wc, ro, port 1/3/5/7: base + (12 ? 13h) r/w (word writes only) default value: 0080h size: 16 bits note: for function 0, this applies to ich6 usb ports 0 and 1; for function 1, this applies to ich6 usb ports 2 and 3; for function 2, this applies to ich6 usb ports 4 and 5; and for function 3, this applies to ich6 usb ports 6 and 7. after a power-up reset, global reset, or host contro ller reset, the initial conditions of a port are: no device connected, port disabled, and the bus line status is 00 (single-ended 0). port reset and enable sequence when software wishes to reset a usb device it will assert the port reset bit in the port status and control register. the minimum reset signaling time is 10 ms and is enforced by software. to complete the reset sequence, software clears the po rt reset bit. the intel uhci controller must re- detect the port connect after reset signaling is comp lete before the controller will allow the port enable bit to de set by software. this time is approximately 5.3 us. software has several possible options to meet the timing requirement and a partial list is inumerated below: ? iterate a short wait, setting the port enable bit and reading it b ack to see if the enable bit is set. ? poll the connect status bit and wait for the hard ware to recognize the c onnect prior to enabling the port. ? wait longer than the hardware detect time afte r clearing the port reset and prior to enabling the port. bit description 15:13 reserved ? ro. 12 suspend ? r/w . this bit should not be written to a 1 if global suspend is active (bit 3=1 in the usbcmd register). bit 2 and bit 12 of this register define the hub states as follows: when in suspend state, downstream propagation of data is blocked on this port, except for single-ended 0 resets (global reset and port reset). the blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. in the suspend state, the port is sensitive to resume detection. note t hat the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the usb. 1 = port in suspend state. 0 = port not in suspend state. note: normally, if a transaction is in progress w hen this bit is set, the port will be suspended when the current transaction completes. however, in the case of a specific error condition (out transaction with babble), the ich6 may issu e a start-of-frame, and then suspend the port. 11 overcurrent indicator ? r/wc. set by hardware. 0 = software clears this bit by writing a 1 to it. 1 = overcurrent pin has gone from i nactive to active on this port. bits [12,2] hub state x,0 disable 0, 1 enable 1, 1 suspend
intel ? i/o controller hub 6 (ich6) family datasheet 525 uhci controllers registers 10 overcurrent active ? ro. this bit is set and cleared by hardware. 0 = indicates that the overcurr ent pin is inactive (high). 1 = indicates that the overcu rrent pin is active (low). 9 port reset ? r/w . 0 = port is not in reset. 1 = port is in reset. when set, the port is disabled and sends t he usb reset signaling. 8 low speed device attached (ls) ? ro . 0 = full speed device is attached. 1 = low speed device is attached to this port. 7 reserved ? ro. always read as 1. 6 resume detect (rsm_det) ? r/w. software sets this bit to a 1 to drive resume signaling. the host controller sets this bit to a 1 if a j-to-k tr ansition is detected for at least 32 microseconds while the port is in the suspend state. the ich6 will then reflect the k- state back onto the bus as long as the bit remains a 1, and the port is still in the suspend state (bit 12,2 are ?11?). writing a 0 (from 1) causes the port to send a low speed eop. this bi t will remain a 1 until the eop has completed. 0 = no resume (k-state) detected/driven on port. 1 = resume detected/driven on port. 5:4 line status ? ro . these bits reflect the d+ (bit 4) and d? (bit 5) signals lines? logical levels. these bits are used for fault detect and recovery as we ll as for usb diagnostics. this field is updated at eof2 time (see chapter 11 of the usb specification). 3 port enable/disable change ? r/wc . for the root hub, this bit gets set only when a port is disabled due to disconnect on that port or due to the appropriate conditions existing at the eof2 point (see chapter 11 of the usb specification). 0 = no change. software clears this bit by writing a 1 to the bit location. 1 = port enabled/disabled status has changed. 2 port enabled/disabled (port_en) ? r/w . ports can be enabled by host software only. ports can be disabled by either a fault conditi on (disconnect event or other faul t condition) or by host software. note that the bit status does not change until the port state actually changes and that there may be a delay in disabling or enabling a port if there is a transaction currently in progress on the usb. 0 = disable 1 = enable 1 connect status change ? r/wc . this bit indicates that a c hange has occurred in the port?s current connect status (see bit 0). the hub device sets this bit for any changes to the port device connect status, even if system software has not cleared a connect status change. if, for example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting? an already-set bit (i.e., the bit will remain set). however, the hub transfers the change bit only once when the host controller requests a data transfer to the status change endpoint. system software is responsible for determining state change history in such a case. 0 = no change. software clears this bit by writing a 1 to it. 1 = change in current connect status. 0 current connect status ? ro . this value reflects the current state of the port, and may not correspond directly to the event that caused the connect status change bit (bit 1) to be set. 0 = no device is present. 1 = device is present on port. bit description
526 intel ? i/o controller hub 6 (i ch6) family datasheet uhci controllers registers
intel ? i/o controller hub 6 (ich6) family datasheet 527 ehci controller registers (d29:f7) 14 ehci controller registers (d29:f7) 14.1 usb ehci configuration registers (usb ehci?d29:f7) note: register address locations that are not shown in table 14-1 should be treated as reserved (see section 6.2 for details). note: all configuration registers in this section are in th e core well and reset by a core well reset and the d3-to-d0 warm reset, except as noted. table 14-1. usb ehci pci register addre ss map (usb ehci?d29:f7) (sheet 1 of 2) offset mnemonic register name default value type 00?01h vid vendor identification 8086h ro 02?03h did device identification 265ch ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0290h r/w, ro 08h rid revision identification see register description ro 09h pi programming interface 20h ro 0ah scc sub class code 03h ro 0bh bcc base class code 0ch ro 0dh pmlt primary master latency timer 00h ro 10?13h mem_base memory base address 00000000h r/w, ro 2c?2dh svid usb ehci subsystem vendor identification xxxxh r/w (special) 2e?2fh sid usb ehci subsystem identification xxxxh r/w (special) 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 50h pwr_capid pci power management capability id 01h ro 51h nxt_ptr1 next item pointer 58h r/w (special) 52?53h pwr_cap power management capabilities c9c2h r/w (special) 54?55h pwr_cntl_sts power management control/status 0000h r/w, r/wc, ro 58h debug_capid debug port capability id 0ah ro 59h nxt_ptr2 next item pointer #2 00h ro
528 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.1 vid?vendor identification register (usb ehci?d29:f7) offset address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 14.1.2 did?device identification register (usb ehci?d29:f7) offset address: 02 ? 03h attribute: ro default value: 265ch size: 16 bits 5a?5bh debug_base debug port base offset 20a0h ro 60h usb_relnum usb release number 20h ro 61h fl_adj frame length adjustment 20h r/w 62?63h pwake_cap port wake capabilities 01ffh r/w 64?67h ? reserved ? ? 68?6bh leg_ext_cap usb ehci legacy support extended capability 00000001h r/w, ro 6c?6fh leg_ext_cs usb ehci legacy extended support control/status 00000000h r/w, r/wc, ro 70?73h special_smi intel specific usb 2.0 smi 00000000h r/w, r/wc 74?7fh ? reserved ? ? 80h access_cntl access control 00h r/w fc?ffh usb2ir usb2 initialization register 00001706h r/w table 14-1. usb ehci pci register addres s map (usb ehci?d29:f7) (sheet 2 of 2) offset mnemonic register name default value type bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. bit description 15:0 device id ? ro. this is a 16-bit value assigned to the intel ? ich6 usb ehci controller.
intel ? i/o controller hub 6 (ich6) family datasheet 529 ehci controller registers (d29:f7) 14.1.3 pcicmd?pci command register (usb ehci?d29:f7) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = the function is capable of generating interrupts. 1 = the function can not generate its interrupt to the interrupt controller. note that the corresponding interrupt status bit (d29: f7:06h, bit 3) is not affected by the interrupt enable. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = disables ehc?s capability to generate an serr#. 1 = the enhanced host controller ( ehc) is capable of generati ng (internally) serr# when it receive a completion status other than ?successfu l? for one of its dma-initiated memory reads on dmi (and subsequently on its internal interface). 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? ro. hardwired to 0. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? r/w. 0 = disables this functionality. 1 = enables the ich6 to act as a master on the pci bus for usb transfers. 1 memory space enable (mse) ? r/w. this bit controls access to the usb 2.0 memory space registers. 0 = disables this functionality. 1 = enables accesses to the usb 2.0 registers. the base address register (d29:f7:10h) for usb 2.0 should be programmed before this bit is set. 0 i/o space enable (iose) ? ro. hardwired to 0.
530 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.4 pcists?pci status register (usb ehci?d29:f7) address offset: 06 ? 07h attribute: r/w, ro default value: 0290h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. wr iting a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. hardwired to 0. 14 signaled system error (sse) ? r/w. 0 = no serr# signaled by ich6. 1 = this bit is set by the ich6 when it signals serr# (internally). the ser_en bit (bit 8 of the command register) must be 1 for this bit to be set. 13 received master abort (rma) ? r/w. 0 = no master abort received by ehc on a memory access. 1 = this bit is set when ehc, as a master, rece ives a master abort status on a memory access. this is treated as a host error and halts the dma engines. this event can optionally generate an serr# by setting the serr# enable bit . 12 received target abort (rta) ? r/w. 0 = no target abort received by ehc on memory access. 1 = this bit is set when ehc, as a master, receives a target abort status on a memory access. this is treated as a host error and halts the dm a engines. this event can optionally generate an serr# by setting the serr# enable bit (d29:f7:04h, bit 8). 11 signaled target abort (sta) ? ro. th is bit is used to indicate when the ehci function responds to a cycle with a target abort. there is no reas on for this to happen, so this bit will be hardwired to 0. 10:9 devsel# timing status (devt_sts) ? ro. this 2-bit field defines the timing for devsel# assertion. 8 master data parity error detected (dped) ? r/w. 0 = no data parity error detected on usb2.0 read completion packet. 1 = this bit is set by the ich6 when a data pari ty error is detected on a usb 2.0 read completion packet on the internal interface to the ehci hos t controller and bit 6 of the command register is set to 1. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66 mhz _cap) ? ro. hardwired to 0. 4 capabilities list (cap_li st) ? ro. hardwired to 1 indicating that offset 34h contains a valid capabilities pointer. 3 interrupt status ? ro. this bit reflects the state of this function?s interrupt at the input of the enable/disable logic. 0 = this bit will be 0 when the interrupt is de-asserted. 1 = this bit is a 1 when the interrupt is asserted. the value reported in this bit is independent of the value in the interrupt enable bit. 2:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 531 ehci controller registers (d29:f7) 14.1.5 rid?revision id entification register (usb ehci?d29:f7) offset address: 08h attribute: ro default value: see bit description size: 8 bits 14.1.6 pi?programming interface register (usb ehci?d29:f7) address offset: 09h attribute: ro default value: 20h size: 8 bits 14.1.7 scc?sub class code register (usb ehci?d29:f7) address offset: 0ah attribute: ro default value: 03h size: 8 bits 14.1.8 bcc?base class code register (usb ehci?d29:f7) address offset: 0bh attribute: ro default value: 0ch size: 8 bits bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. a value of 20h indicate s that this usb 2.0 host controller conforms to the ehci specification. bit description 7:0 sub class code (scc) ? ro. 03h = universal serial bus host controller. bit description 7:0 base class code (bcc) ? ro. 0ch = serial bus controller.
532 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.9 pmlt?primary master latency timer register (usb ehci?d29:f7) address offset: 0dh attribute: ro default value: 00h size: 8 bits 14.1.10 mem_base?memory base address register (usb ehci?d29:f7) address offset: 10 ? 13h attribute: r/w, ro default value: 00000000h size: 32 bits 14.1.11 svid?usb ehci subsys tem vendor id register (usb ehci?d29:f7) address offset: 2c ? 2dh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none bit description 7:0 master latency timer count (mltc) ? ro. hardwired to 00h. because the ehci controller is internally implemented with arbi tration on an interface (and not pci), it does not need a master latency timer. bit description 31:10 base address ? r/w. bits [31:10] correspond to memo ry address signals [31:10], respectively. this gives 1-kb of locatable memory space aligned to 1-kb boundaries. 9:4 reserved 3 prefetchable ? ro. hardwired to 0 indicating that this range should not be prefetched. 2:1 type ? ro. hardwired to 00b indicating that th is range can be mapped anywhere within 32-bit address space. 0 resource type indicator (rte) ? ro. hardwired to 0 indicating that the base address field in this register maps to memory space. bit description 15:0 subsystem vendor id (svid) ? r/w (special). this register, in combination with the usb 2.0 subsystem id register, enables th e operating system to distinguis h each subsystem from the others. note: writes to this register are enabled when the wrt_rdonly bit (d29:f7:80h, bit 0) is set to 1.
intel ? i/o controller hub 6 (ich6) family datasheet 533 ehci controller registers (d29:f7) 14.1.12 sid?usb ehci subsystem id register (usb ehci?d29:f7) address offset: 2e ? 2fh attribute: r/w (special) default value: xxxxh size: 16 bits reset: none 14.1.13 cap_ptr?capabilities pointer register (usb ehci?d29:f7) address offset: 34h attribute: ro default value: 50h size: 8 bits 14.1.14 int_ln?interrupt line register (usb ehci?d29:f7) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 14.1.15 int_pn?interru pt pin register (usb ehci?d29:f7) address offset: 3dh attribute: ro default value: see descr iption size: 8 bits bit description 15:0 subsystem id (sid) ? r/w (special). bios sets the value in this register to identify the subsystem id. this register, in combination with the s ubsystem vendor id register, enables the operating system to distinguish each subsystem from other(s). note: writes to this register are enabled when the wrt_rdonly bit (d29:f7:80h, bit 0) is set to 1. bit description 7:0 capabilities pointer (cap_ptr) ? ro. this register points to the starting offset of the usb 2.0 capabilities ranges. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich6. it is used as a scratchpad register to communicate to software the interr upt line that the interrupt pin is connected to. bit description 7:0 interrupt pin ? ro. this reflects the value of d29ip.ei p (chipset configuration registers:offset 3108:bits 31:28). note: bits 7:4 are always 0h
534 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.16 pwr_capid?pci powe r management capability id register (usb ehci?d29:f7) address offset: 50h attribute: ro default value: 01h size: 8 bits 14.1.17 nxt_ptr1?next it em pointer #1 register (usb ehci?d29:f7) address offset: 51h attribute: r/w (special) default value: 58h size: 8 bits bit description 7:0 power management capability id ? ro. a value of 01h indicates that this is a pci power management capabilities field. bit description 7:0 next item pointer 1 value ? r/w (special). this register defaul ts to 58h, which indicates that the next capability registers begin at configuration offset 58h. this register is writable when the wrt_rdonly bit (d29:f7:80h, bit 0) is set. this allows bios to effectively hide the debug port capability registers, if necessary. this regist er should only be written dur ing system initialization before the plug-and-play software has enabled any master-initiated traffic. only values of 58h (debug port visible) and 00h (debug port invisible) ar e expected to be programmed in this register. note: register not reset by d3-to-d0 warm reset.
intel ? i/o controller hub 6 (ich6) family datasheet 535 ehci controller registers (d29:f7) 14.1.18 pwr_cap?power manage ment capabilities register (usb ehci?d29:f7) address offset: 52 ? 53h attribute: r/w (special) default value: c9c2h size: 16 bits notes: 1. normally, this register is read-only to report ca pabilities to the power management software. to report different power management capabilities, depending on the system in which the ich6 is used, bits 15:11 and 8:6 in this register are writable when the wrt_rdonly bit (d29:f7:80h, bit 0) is set. the value written to this register does not affect the hardware other than changing the value returned during a read. 2. reset: core well, but not d3-to-d0 warm reset. bit description 15:11 pme support (pme_sup) ? r/w (special). this 5-bit field indicates th e power states in which the function may assert pme#. the intel ? ich6 ehc does not support the d1 or d2 states. for all other states, the ich6 ehc is capable of generating pme#. software should never need to modify this field. 10 d2 support (d2_sup) ? r/w (special). 0 = d2 state is not supported 1 = d2 state is supported 9 d1 support (d1_sup) ? r/w (special). 0 = d1 state is not supported 1 = d1 state is supported 8:6 auxiliary current (aux_cur) ? r/w (special). the ich6 ehc reports 375 ma maximum suspend well current required when in the d3 cold state. this value can be written by bios when a more accurate value is known. 5 device specific initialization (dsi )? r/w (special). the ich6 reports 0, indicating that no device-specific initia lization is required. 4reserved 3 pme clock (pme_clk) ? r/w (special). the ich6 reports 0, indicating that no pci clock is required to generate pme#. 2:0 version (ver) ? r/w (special). the ich6 reports 010b, indicating that it complies with revision 1.1 of the pci power management specification.
536 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.19 pwr_cntl_sts?power management control/status register (usb ehci?d29:f7) address offset: 54 ? 55h attribute: r/w, r/wc, ro default value: 0000h size: 16 bits note: reset (bits 15, 8): suspend well, and not d3-to-d0 warm reset nor core well reset. 14.1.20 debug_capid?debug po rt capability id register (usb ehci?d29:f7) address offset: 58h attribute: ro default value: 0ah size: 8 bits bit description 15 pme status ? r/wc. 0 = writing a 1 to this bit will clear it and cause the internal pme to de-assert (if enabled). 1 = this bit is set when the ich6 ehc would norma lly assert the pme# signal independent of the state of the pme_en bit. note: this bit must be explicitly cleared by the operating system eac h time the operating system is loaded. 14:13 data scale ? ro. hardwired to 00b indicating it does not support the associated data register. 12:9 data select ? ro. hardwired to 0000b indicating it does not support the associated data register. 8 pme enable ? r/w. 0 = disable. 1 = enable. enables intel ? ich6 ehc to generate an internal pme signal when pme_status is 1. note: this bit must be explicitly cleared by the operating system eac h time it is initially loaded. 7:2 reserved 1:0 power state ? r/w. this 2-bit field is used both to determine the current power state of ehc function and to set a new power state. the definition of the field values are: 00 = d0 state 11 = d3 hot state if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarde d and no state change occurs. when in the d3 hot state, the ich6 must not accept accesses to the ehc memory range; but the configuration space must still be accessible. when not in the d0 state, the generation of the interrupt output is blocked. specifically, the pirqh is not asserted by the ich6 when not in the d0 state. when software changes this value from the d3 hot state to the d0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. bit description 7:0 debug port capability id ? ro. hardwired to 0ah i ndicating that this is the start of a debug port capability structure.
intel ? i/o controller hub 6 (ich6) family datasheet 537 ehci controller registers (d29:f7) 14.1.21 nxt_ptr2?next it em pointer #2 register (usb ehci?d29:f7) address offset: 59h attribute: ro default value: 00h size: 8 bits 14.1.22 debug_base?debug po rt base offset register (usb ehci?d29:f7) address offset: 5ah ? 5bh attribute: ro default value: 20a0h size: 16 bits 14.1.23 usb_relnum?usb release number register (usb ehci?d29:f7) address offset: 60h attribute: ro default value: 20h size: 8 bits bit description 7:0 next item pointer 2 capability ? ro. hardwired to 00h to indicate there are no more capability structures in this function. bit description 15:13 bar number ? ro. hardwired to 001b to indicate the memory bar begins at offset 10h in the ehci configuration space. 12:0 debug port offset ? ro. hardwired to 0a0h to indicate that the debug port registers begin at offset a0h in the ehci memory range. bit description 7:0 usb release number ? ro. a value of 20h indicates that this controller follows universal serial bus (usb) specification, revision 2.0 .
538 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.24 fl_adj?frame length adjustment register (usb ehci?d29:f7) address offset: 61h attribute: r/w default value: 20h size: 8 bits this feature is used to adjust any offset from th e clock source that generates the clock that drives the sof counter. when a new value is written into th ese six bits, the length of the frame is adjusted. its initial programmed value is system dependent based on the accuracy of hardware usb clock and is initialized by system bios. this register should only be modified when the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_s ts register is a 1. changing value of this register while the host controller is operating yields undefined results. it should not be reprogrammed by usb system software unless the default or bios programmed values are incorrect, or the system is restoring the regi ster while returning from a suspended state. these bits in suspend well and not reset by a d3-to-d0 warm rest or a core well reset. bit description 7:6 reserved ? ro. these bits are reserv ed for future use and should read as 00b. 5:0 frame length timing value ? r/w. each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle time (num ber of sof counter clock periods to generate a sof micro-frame length) is equal to 59488 + value in this field. the default value is decimal 32 (20h), which gives a so f cycle time of 60000. frame length (# 480 mhz clocks) (decimal) frame length timing value (this register) (decimal) 59488 0 59504 1 59520 2 ?? 59984 31 60000 32 ?? 60480 62 60496 63
intel ? i/o controller hub 6 (ich6) family datasheet 539 ehci controller registers (d29:f7) 14.1.25 pwake_cap?port wa ke capability register (usb ehci?d29:f7) address offset: 62 ? 63h attribute: r/w default value: 01ffh size: 16 bits this register is in the suspend power well. the inte nded use of this register is to establish a policy about which ports are to be used for wake events. bit positions 1?8 in the mask correspond to a physical port implemented on the current ehci controller. a 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect/connect or overcurrent events as wa ke-up events. this is an information-only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system-specific policy can be established by bios initializing this regist er to a system-specific value. system software uses the information in this register when enabling devices and ports for remote wake-up. these bits are not reset by a d3-to-d0 warm rest or a core well reset. 14.1.26 leg_ext_cap?usb ehci legacy support extended capability register (usb ehci?d29:f7) address offset: 68 ? 6bh attribute: r/w, ro default value: 00000001h size: 32 bits power well: suspend note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. bit description 15:9 reserved ? ro. 8:1 port wake up capability mask ? r/w. bit positions 1 through 8 correspond to a physical port implemented on this host controller. for example, bit position 1 corresponds to port 1, bit position 2 corresponds to port 2, etc. 0 port wake implemented ? r/w. a 1 in this bit indicates that this register is implemented to software. bit description 31:25 reserved ? ro. hardwired to 00h 24 hc os owned semaphore ? r/w. system software sets this bit to request ownership of the ehci controller. ownership is obtained when this bit reads as 1 and the hc bios owned semaphore bit reads as clear. 23:17 reserved ? ro. hardwired to 00h 16 hc bios owned semaphore ? r/w. the bios sets this bit to establish ownership of the ehci controller. system bios will clear this bit in response to a request for ownership of the ehci controller by system software. 15:8 next ehci capability pointer ? ro. hardwired to 00h to indicate that there are no ehci extended capability structur es in this device. 7:0 capability id ? ro. hardwired to 01h to indicate that this ehci extended capability is the legacy support capability.
540 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.1.27 leg_ext_cs?usb ehci legacy support extended control / status registe r (usb ehci?d29:f7) address offset: 6c ? 6fh attribute: r/w, r/wc, ro default value: 00000000h size: 32 bits power well: suspend note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. bit description 31 smi on bar ? r/wc. software clears this bit by writing a 1 to it. 0 = base address register (bar) not written. 1 = this bit is set to 1 when the base address register (bar) is written. 30 smi on pci command ? r/wc. software clears this bit by writing a 1 to it. 0 = pci command (pcicmd) register not written. 1 = this bit is set to 1 when the pci command (pcicmd) register is written. 29 smi on os ownership change ? r/wc. software clears this bit by writing a 1 to it. 0 = no hc os owned semaphore bit change. 1 = this bit is set to 1 when the hc os owned semaphore bit in the leg_ext_cap register (d29:f7:68h, bit 24) transitions from 1 to 0 or 0 to 1. 28:22 reserved ? ro. hardwired to 00h 21 smi on async advance ? ro. this bit is a shadow bit of the interrupt on async advance bit (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the interrupt on async advance bit in the usb2.0_sts register. 20 smi on host system error ? ro. this bit is a shadow bit of host system error bit in the usb2.0_sts register (d29:f7:caplength + 24h, bit 4). note: to clear this bit system software must writ e a 1 to the host system error bit in the usb2.0_sts register. 19 smi on frame list rollover ? ro. this bit is a shadow bi t of frame list rollover bit (d29:f7:caplength + 24h, bit 3) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the frame list rollover bit in the usb2.0_sts register. 18 smi on port change detect ? ro. this bit is a shadow bit of port change detect bit (d29:f7:caplength + 24h, bit 2) in the usb2.0_sts register. note: to clear this bit system software must writ e a 1 to the port change detect bit in the usb2.0_sts register. 17 smi on usb error ? ro. this bit is a shadow bit of usb error interrupt (usberrint) bit (d29:f7:caplength + 24h, bit 1) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb error interrupt bit in the usb2.0_sts register. 16 smi on usb complete ? ro. this bit is a shadow bit of usb interrupt (usbint) bit (d29:f7:caplength + 24h, bit 0) in the usb2.0_sts register. note: to clear this bit system software must write a 1 to the usb interrupt bit in the usb2.0_sts register. 15 smi on bar enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on bar (d29:f7 :6ch, bit 31) is 1, then the host controller will issue an smi. 14 smi on pci command enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pci comm and (d29:f7:6ch, bit 30) is 1, then the host controller will issue an smi.
intel ? i/o controller hub 6 (ich6) family datasheet 541 ehci controller registers (d29:f7) 14.1.28 special_smi?intel sp ecific usb 2.0 smi register (usb ehci?d29:f7) address offset: 70 ? 73h attribute: r/w, r/wc default value: 00000000h size: 32 bits power well: suspend note: these bits are not reset by a d3-to-d0 warm rest or a core well reset. 13 smi on os ownership enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and the os owner ship change bit (d29:f7:6ch, bit 29) is 1, the host controller will issue an smi. 12:6 reserved ? ro. hardwired to 00h 5 smi on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on asyn c advance bit (d29:f7:6ch, bit 21) is a 1, the host controller will issue an smi immediately. 4 smi on host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on host system error (d29:f7:6ch, bit 20) is a 1, the host controller will issue an smi. 3 smi on frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on fram e list rollover bit (d29:f7:6ch, bit 19) is a 1, the host controller will issue an smi. 2 smi on port change enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on po rt change detect bit (d29:f7:6ch, bit 18) is a 1, the host controller will issue an smi. 1 smi on usb error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on u sb error bit (d29:f7:6ch, bit 17) is a 1, the host controller will issue an smi immediately. 0 smi on usb complete enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the smi on usb complete bit (d29:f7:6ch, bit 16) is a 1, the host controller will issue an smi immediately. bit description bit description 31:30 reserved ? ro. hardwired to 00h 29:22 smi on portowner ? r/wc. software clears these bits by writing a 1 to it. 0 = no port owner bit change. 1 = bits 29:22 correspond to the port owner bits for ports 1 (22) through 8 (29). these bits are set to 1 when the associated port owner bits transition from 0 to 1 or 1 to 0. 21 smi on pmcsr ? r/wc. software clears these bits by writing a 1 to it. 0 = power state bits not modified. 1 = software modified the power state bits in the power management control/status (pmcsr) register (d29:f7:54h). 20 smi on async ? r/wc. software clears these bits by writing a 1 to it. 0 = no async schedule enable bit change 1 = async schedule enable bit transitioned from 1 to 0 or 0 to 1.
542 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 19 smi on periodic ? r/wc. software clears this bit by writing a 1 it. 0 = no periodic schedul e enable bit change. 1 = periodic schedule enable bit transitions from 1 to 0 or 0 to 1. 18 smi on cf ? r/wc. software clears th is bit by writing a 1 it. 0 = no configure flag (cf) change. 1 = configure flag (cf) transitions from 1 to 0 or 0 to 1. 17 smi on hchalted ? r/wc. software clears this bit by writing a 1 it. 0 = hchalted did not transition to 1 (as a result of the run/stop bit being cleared). 1 = hchalted transitions to 1 (as a result of the run/stop bit being cleared). 16 smi on hcreset ? r/wc. software clears this bit by writing a 1 it. 0 = hcreset did not transitioned to 1. 1 = hcreset transitioned to 1. 15:14 reserved ? ro. hardwired to 00h 13:6 smi on portowner enable ? r/w. 0 = disable. 1 = enable. when any of these bits are 1 and the corresponding smi on portowner bits are 1, then the host controller will issue an smi. unus ed ports should have their corresponding bits cleared. 5 smi on pmscr enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on pmscr is 1, then the host controller will issue an smi. 4 smi on async enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on async is 1, then the host controller will issue an smi 3 smi on periodic enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on periodic is 1, then the host controller will issue an smi. 2 smi on cf enable ? r/w. 0 = disable. 1 = enable. when this bit is 1 and smi on cf is 1, then the host controller will issue an smi. 1 smi on hchalted enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hcha lted is 1, then the host controller will issue an smi. 0 smi on hcreset enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1 and smi on hcrese t is 1, then host controller will issue an smi. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 543 ehci controller registers (d29:f7) 14.1.29 access_cntl?acce ss control register (usb ehci?d29:f7) address offset: 80h attribute: r/w default value: 00h size: 8 bits 14.1.30 usb2ir?usb2 initialization register (usb ehci?d29:f7) address offset: fc-ffh attribute: r/w default value: 00001706h size: 32 bits bit description 7:1 reserved 0 wrt_rdonly ? r/w. when set to 1, this bit enables a select group of normally read-only registers in the ehc function to be written by soft ware. registers that may only be written when this mode is entered are noted in the summary tables and detailed description as ?read/write-special?. the registers fall into two categories: 1. system-configured parameters, and 2. status bits bit description 31:8 reserved 7 usb ehci initialization field 2 ? r/w. mobile: bios must clear this bit to 0b. desktop: bios must set this bit to 1b. 6 reserved 5 usb ehci initialization field 1 ? r/w. bios must clear this bit to 0b. 4:0 reserved
544 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2 memory-mapped i/o registers the ehci memory-mapped i/o space is composed of two sets of registers: capability registers and operational registers. note: the ich6 ehci controller will not accept memory transactions (neither reads nor writes) as a target that are locked transacti ons. the locked transactions should not be forwarded to pci as the address space is known to be allocated to usb. note: when the ehci function is in the d3 pci power state, accesses to the usb 2.0 memory range are ignored and result a master abort. similarly, if the memory space enable (mse) bit (d29:f7:04h, bit 1) is not set in the command register in configuration space, the me mory range will not be decoded by the ich6 enhanced host controller (ehc). if the mse bit is not set, then the ich6 must default to allowing any memory accesses for the range specified in the bar to go to pci. this is because the range may not be valid and, therefore, the cycle must be made available to any other targets that may be currently using that range. 14.2.1 host controller capability registers these registers specify the limits, restrictio ns and capabilities of the host controller implementation. within the host controller capability registers, only the structural parameters register is writable. these registers are implemen ted in the suspend well and is only reset by the standard suspend-well hardware reset, not by hcreset or the d3-to-d0 reset. note: ?read/write special? means that the register is normally read-only, but may be written when the wrt_rdonly bit is set. because these register s are expected to be programmed by bios during initialization, their contents must not get modi fied by hcreset or d3-to-d0 internal reset. 14.2.1.1 caplength?capabilit y registers length register offset: mem_base + 00h attribute: ro default value: 20h size: 8 bits table 14-2. enhanced host controller capability registers mem_base + offset mnemonic register default type 00h caplength capabilities registers length 20h ro 02?03h hciversion host controller interface version number 0100h ro 04?07h hcsparams host controller structural parameters 00104208h r/w (special), ro 08?0bh hccparams host controller capability parameters 00006871h ro bit description 7:0 capability register length value ? ro. this regist er is used as an offset to add to the memory base register (d29:f7:10h) to find the beginning of the operational register space. this field is hardwired to 20h indicating that the oper ation registers begin at offset 20h.
intel ? i/o controller hub 6 (ich6) family datasheet 545 ehci controller registers (d29:f7) 14.2.1.2 hciversion?host controll er interface version number register offset: mem_base + 02 ? 03h attribute: ro default value: 0100h size: 16 bits 14.2.1.3 hcsparams?host contro ller structural parameters offset: mem_base + 04 ? 07h attribute: r/w (special), ro default value: 00104208h size: 32 bits note: this register is reset by a suspend well reset and not a d3-to-d0 reset or hcreset. note: this register is writable when the wrt_rdonly bit is set. bit description 15:0 host controller interface version number ? ro. this is a two-byte register containing a bcd encoding of the version number of interface t hat this host controller interface conforms. bit description 31:24 reserved ? ro. default=0h. 23:20 debug port number (dp_n) ? ro (special). hardwired to 1h indicating that the debug port is on the lowest numbered port on the ich6. 19:16 reserved 15:12 number of companion controllers (n_cc) ? r/w (special). this field indicates the number of companion controllers associated with this usb ehci host controller. a 0 in this field indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed dev ices are supported on the host controller root ports. a value of 1 or more in this field indicates t here are companion usb uhci host controller(s). port- ownership hand-offs are supported. high, full - and low-speed devices are supported on the host controller root ports. the ich6 allows the default value of 4h to be over-written by bios . when removing classic controllers, they should be disabled in the following order: fu nction 3, function 2, function 1, and function 0, which correspond to ports 7: 6, 5:4, 3:2, and 1:0, respectively. 11:8 number of ports per companion controller (n_pcc) ? ro. hardwired to 2h. th is field indicates the number of ports supported per companion host contro ller. it is used to indicate the port routing configuration to system software. 7:4 reserved. these bits are reserved and default to 0. 3:0 n_ports ? r/w (special). this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. the ich6 reports 8h by default. however, software may write a value less than 8 for some platform configurations. a 0 in this field is undefined.
546 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.1.4 hccparams?host controll er capability parameters register offset: mem_base + 08 ? 0bh attribute: ro default value: 00006871h size: 32 bits bit description 31:16 reserved 15:8 ehci extended capabilities pointer (eecp) ? ro. this field is hardwired to 68h, indicating that the ehci capabilities list exists and begins at offset 68h in the pci configuration space. 7:4 isochronous scheduling threshold ? ro. this field indicates, relative to the current position of the executing host controller, where software can reliably update the isochr onous schedule. when bit 7 is 0, the value of the least signi ficant 3 bits indicates the number of micro-frames a host controller hold a set of isochronous data structures (one or more ) before flushing the state. when bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. refer to the ehci specification for details on how software uses this information for scheduling isochr onous transfers. this field is hardwired to 7h. 3 reserved. these bits are re served and should be set to 0. 2 asynchronous schedule park capability ? ro. this bit is hardwired to 0 indicating that the host controller does not support this optional feature 1 programmable frame list flag ? ro. 0 = system software must use a frame list length of 1024 elements with this host controller. the usb2.0_cmd register (d29:f7:caplength + 20h, bits 3:2) frame list size field is a read- only register and must be set to 0. 1 = system software can specify and use a smaller frame list and configure the host controller via the usb2.0_cmd register frame list size field. the frame list mu st always be aligned on a 4k page boundary. this requirement ensures that t he frame list is always physically contiguous. 0 64-bit addressing capability ? ro . this field documents the addressing range capability of this implementation. the value of this field determines whether software should use the 32-bit or 64-bit data structures. values for this fi eld have the follow ing interpretation: 0 = data structures using 32-bit address memory pointers 1 = data structures using 64-bit address memory pointers this bit is hardwired to 1. note: ich6 only implements 44 bits of addres sing. bits 63:44 will always be 0.
intel ? i/o controller hub 6 (ich6) family datasheet 547 ehci controller registers (d29:f7) 14.2.2 host controller operational registers this section defines the enhanced host controller operational registers. th ese registers are located after the capabilities registers. the operationa l register base must be dword-aligned and is calculated by adding the value in the first capabi lities register (caplength) to the base address of the enhanced host controller register a ddress space (mem_base). since caplength is always 20h, table 14-3 already accounts for this offset. a ll registers are 32 bits in length. note: software must read and write these register s using only dword accesses.these registers are divided into two sets. the first set at offsets mem_base + 00:3bh are implemented in the core power well. unless otherwise noted, the core well registers are reset by the assertion of any of the following: ? core well hardware reset ? hcreset ? d3-to-d0 reset table 14-3. enhanced host controller operational register address map mem_base + offset mnemonic register name default special notes type 20?23h usb2.0_cmd usb 2.0 command 00080000h r/w, ro 24?27h usb2.0_sts usb 2.0 status 00001000h r/wc, ro 28?2bh usb2.0_intr usb 2.0 interrupt enable 00000000h r/w 2c?2fh frindex usb 2.0 frame index 00000000h r/w, 30?33h ctrlds- segment control data structure segment 00000000h r/w, ro 34?37h perodi- clistbase period frame list base address 00000000h r/w 38?3bh asynclis- taddr current asynchronous list address 00000000h r/w 3c?5fh ? reserved 0h ro 60?63h configglag configure flag 00000000h suspend r/w 64?67h port0sc port 0 status and control 00003000h suspend r/w, r/wc, ro 68?6bh port1sc port 1 status and control 00003000h suspend r/w, r/wc, ro 6c?6fh port2sc port 2 status and control 00003000h suspend r/w, r/wc, ro 70?73h port3sc port 3 status and control 00003000h suspend r/w, r/wc, ro 74?77h port4sc port 4 status and control 00003000h suspend r/w, r/wc, ro 78?7bh port5sc port 5 status and control 00003000h suspend r/w, r/wc, ro 7c?7fh port6sc port 6 status and control 00003000h suspend r/w, r/wc, ro 80?83h port7sc port 7 status and control 00003000h suspend r/w, r/wc, ro 84?9fh ? reserved undefined ro a0?b3h ? debug port registers undefined see register description b4?3ffh ? reserved undefined ro
548 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) the second set at offsets mem_base + 60h to the end of the implemented register space are implemented in the suspend power well. unless ot herwise noted, the suspend well registers are reset by the assertion of either of the following: ? suspend well hardware reset ? hcreset 14.2.2.1 usb2.0_cmd?usb 2.0 command register offset: mem_base + 20?23h attribute: r/w, ro default value: 00080000h size: 32 bits bit description 31:24 reserved. these bits are reserved and s hould be set to 0 when writing this register. 23:16 interrupt threshold control ? r/w. system software uses this field to select the maximum rate at which the host controller will issue interrupts. the only valid values are defined below. if software writes an invalid value to this r egister, the results are undefined. 15:8 reserved. these bits are reserved and should be se t to 0 when writing this register. 11:8 unimplemented asynchronous park mode bits. hard wired to 000b indicating the host controller does not support this optional feature. 7 light host controller reset ? ro. hardwired to 0. the ich6 does not impl ement this optional reset. 6 interrupt on async advance doorbell ? r/w. this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. 0 = the host controller sets this bit to a 0 after it has set the interrupt on async advance status bit (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register to a 1. 1 = software must write a 1 to this bit to ring the doorbell. when the host c ontroller has evicted all appropriate cached schedule state, it sets the interrupt on async advance status bit in the usb2.0_sts register. if the interrupt on async advance enable bit in the usb2.0_intr register (d29:f7:caplength + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the next interrupt threshold. see the ehci specification for operational details. note: software should not write a 1 to this bit when the asynchronous schedul e is inactive. doing so will yield undefined results. 5 asynchronous schedule enable ? r/w. default 0b. this bit cont rols whether the host controller skips processing the asynchronous schedule. 0 = do not process the asynchronous schedule 1 = use the asynclistaddr register to access the asynchronous schedule. 4 periodic schedule enable ? r/w. default 0b. this bit controls whether the host controller skips processing the periodic schedule. 0 = do not process the periodic schedule 1 = use the periodiclistbase regist er to access the periodic schedule. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms)
intel ? i/o controller hub 6 (ich6) family datasheet 549 ehci controller registers (d29:f7) note: the command register indicates the command to be ex ecuted by the serial bus host controller. writing to the register causes a command to be executed. 3:2 frame list size ? ro. the ich6 hardwires this fi eld to 00b because it only supports the 1024-element frame list size. 1 host controller reset (hcreset) ? r/w. this control bit used by software to reset the host controller. the effects of this on root hub regi sters are similar to a chip hardware reset (i.e., rsmrst# assertion and pwrok de-assertion on the ich6). when software writes a 1 to this bit, the host controll er resets its internal pi pelines, timers, counters, state machines, etc. to their initial value. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. note: pci configuration registers and ho st controller capability registers are not effected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effects described in the ehci spec. software must re-initialize the host c ontroller in order to return the host controller to an operational state. this bit is set to 0 by the host controller when the reset process is complete. software cannot terminate the reset process early by writing a 0 to this register. software should not set this bit to a 1 when the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_sts register is a 0. attempting to reset an actively running host cont roller will result in undefined behavior. this reset me be used to leave ehci port test modes. 0 run/stop (rs) ? r/w. 0 = stop (default) 1 = run. when set to a 1, the host controller pr oceeds with execution of the schedule. the host controller continues exec ution as long as this bit is set. w hen this bit is set to 0, the host controller completes the current transaction on the usb and then halts. the hchalted bit in the usb2.0_sts register indicates when the host controller has finished the transaction and has entered the stopped state. software should not write a 1 to this field unl ess the host controller is in the halted state (i.e., hchalted in the usbsts register is a 1). t he halted bit is cleared immediately when the run bit is set. the following table explains how the different co mbinations of run and halted should be interpreted: memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being cleared. bit description run/stop halted interpretation 0b 0b in the process of halting 0b 1b halted 1b 0b running 1b 1b invalid - the hchalted bit clears immediately
550 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.2.2 usb2.0_sts?usb 2.0 status register offset: mem_base + 24?27h attribute: r/wc, ro default value: 00001000h size: 32 bits this register indicates pending interrupts and va rious states of the host controller. the status resulting from a transaction on the serial bus is no t indicated in this regi ster. see the interrupts description in section 4 of the ehci specification for additional information concerning usb 2.0 interrupt conditions. note: for the writable bits, software must write a 1 to clear bits that are set. writing a 0 has no effect. bit description 31:16 reserved. these bits are reserved and s hould be set to 0 when writing this register. 15 asynchronous schedule status ? ro. this bit reports the current real status of the asynchronous schedule. 0 = status of the asynchronous schedule is disabled. (default) 1 = status of the asynchronous schedule is enabled. note: the host controller is not required to immediately disable or enable the asynchronous schedule when software transitions the asynchronous schedule enable bit (d29:f7:caplength + 20h, bit 5) in the usb2 .0_cmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 periodic schedule status ? ro. this bit reports the current real status of the periodic schedule. 0 = status of the periodic sc hedule is disabled. (default) 1 = status of the periodic schedule is enabled. note: the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit (d29:f7:caplength + 20h, bit 4) in the usb2.0_cmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 reclamation ? ro. 0=default. this read-only status bit is used to detect an empty asynchronous schedule. the operational model and vali d transitions for this bit are described in section 4 of the ehci specification. 12 hchalted ? ro. 0 = this bit is a 0 when the run/stop bit is a 1. 1 = the host controller sets this bit to 1 after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g., internal error). (default) 11:6 reserved 5 interrupt on async advance ? r/wc. 0=default. system software can force the host controller to issue an interrupt the next time t he host controller advances the as ynchronous schedule by writing a 1 to the interrupt on async advance doorbell bit (d29:f7:caplength + 20h, bit 6) in the usb2.0_cmd register. this bit indicates the assertion of that interrupt source. 4 host system error ? r/wc. 0 = no serious error occurred during a host system access involving the host controller module 1 = the host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. a hardwar e interrupt is generated to the system. memory read cycles initiated by the ehc that receive any status other than successful will result in this bit being set. when this error occurs, the host controller clears the run/stop bit in the usb2.0_cmdregister (d29:f7:caplength + 20h, bit 0) to prevent further execution of the scheduled tds. a hardware interrupt is generated to the system (if enabled in the interrupt enable register).
intel ? i/o controller hub 6 (ich6) family datasheet 551 ehci controller registers (d29:f7) 3 frame list rollover ? r/wc. 0 = no frame list index rollover from its maximum value to 0. 1 = the host controller sets this bit to a 1 when the frame list index (see section) rolls over from its maximum value to 0. since the ich6 only supports the 1024-entry frame list size, the frame list index rolls over every time frnum13 toggles. 2 port change detect ? r/wc. this bit is allowed to be ma intained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bi ts (including: force port resume, overcurrent change, enable/disable change and c onnect status change). regardles s of the implementation, when this bit is readable (i.e., in the d0 state), it must provide a valid view of the port status registers. 0 = no change bit transition from a 0 to 1 or no fo rce port resume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 = the host controller sets this bit to 1 when any port for which the port owner bit is set to 0 has a change bit transition from a 0 to 1 or a force port re sume bit transition from 0 to 1 as a result of a j-k transition detected on a suspended port. 1 usb error interrupt (usberrint) ? r/wc. 0 = no error condition. 1 = the host controller sets this bit to 1 when completion of a usb transaction results in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and bit 0 are set. see the ehci specification for a list of the usb errors that will result in this interrupt being asserted. 0 usb interrupt (usbint) ? r/wc. 0 = no completion of a usb transaction whose trans fer descriptor had its ioc bit set. no short packet is detected. 1 = the host controller sets this bit to 1 when t he cause of an interrupt is a completion of a usb transaction whose transfer descriptor had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). bit description
552 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.2.3 usb2.0_intr?usb 2.0 interrupt enable register offset: mem_base + 28?2bh attribute: r/w default value: 00000000h size: 32 bits this register enables and disables reporting of th e corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the usb2.0_sts register to allow the software to poll for events. each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see se ction 4 of the ehci specification), or not. bit description 31:6 reserved. these bits are reserved and should be 0 when writing this register. 5 interrupt on async advance enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the inte rrupt on async advance bit (d29:f7:caplength + 24h, bit 5) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is a cknowledged by software clearing the interrupt on async advance bit. 4 host system error enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the host system error status bit (d29:f7:caplength + 24h, bit 4) in the usb2.0_sts register is a 1, the hos t controller will issue an interrupt. the interrupt is acknowledged by software clearing the host system error bit. 3 frame list rollover enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the frame list rollover bit (d29:f7:caplength + 24h, bit 3) in the usb2.0_sts register is a 1, the host cont roller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 2 port change interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the port c hange detect bit (d29:f7:caplength + 24h, bit 2) in the usb2.0_sts register is a 1, the host cont roller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. 1 usb error interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the usberrint bit (d29:f7:caplength + 24h, bit 1) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by so ftware by clearing the usberrint bit in the usb2.0_sts register. 0 usb interrupt enable ? r/w. 0 = disable. 1 = enable. when this bit is a 1, and the u sbint bit (d29:f7:caplength + 24h, bit 0) in the usb2.0_sts register is a 1, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by so ftware by clearing the usbint bit in the usb2.0_sts register.
intel ? i/o controller hub 6 (ich6) family datasheet 553 ehci controller registers (d29:f7) 14.2.2.4 frindex?fram e index register offset: mem_base + 2c?2fh attribute: r/w default value: 00000000h size: 32 bits the sof frame number valu e for the bus sof token is derived or alternatively managed from this register. refer to section 4 of the ehci specificat ion for a detailed explanation of the sof value management requirements on the host controller. the value of frindex must be within 125 s (1 micro-frame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow register. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames. (1 millisecond). an example implementation to achieve this behavior is to increment so fv each time the fr index[2:0] increments from 0 to 1. software must use the value of frindex to de rive the current micro- frame number, both for high-speed isochronous scheduling purposes and to provide the get micro-frame number function required to client driver s. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software write s to frindex. writes to frindex must also write-through frindex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software should never write a frindex value wher e the three least significant bits are 111b or 000b. note: this register is used by the host controller to index into the periodic frame list. the register updates every 125 microseconds (once each micr o-frame). bits [12:3] are used to select a particular entry in the periodic frame list during periodic schedule ex ecution. the number of bits used for the index is fixed at 10 for the ich6 since it only supports 1024-entry frame lists. this register must be written as a dword. word and byte writes produce undefined results. this register cannot be written unless the host controller is in the halted state as indicated by the hchalted bit (d29:f7:caplength + 24h, bit 12). a write to this register while the run/stop bit (d29:f7:caplength + 20h, bit 0) is set to a 1 (usb2.0_cmd register) produces undefined results. writes to this register also effect the sof value. see sect ion 4 of the ehci specification for details. bit description 31:14 reserved 13:0 frame list current index/frame number ? r/w. the value in this register increments at the end of each time frame (e.g., micro-frame). bits [12:3] are used for the frame list current i ndex. this means that each location of the frame list is accessed 8 times (frames or micro- frames) before moving to the next index.
554 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.2.5 ctrldssegment?control data structure segment register offset: mem_base + 30?33h attribute: r/w, ro default value: 00000000h size: 32 bits this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. since the ich6 hardwires the 64-bit addressing capability field in hccparams to 1, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concatenated with the li nk pointer from either the periodiclistbase, asyncl istaddr, or any control data structure link field to construct a 64-bit address. this register allows the host softwa re to locate all control data structures within the same 4 gb memory segment. 14.2.2.6 periodiclistbase?peri odic frame list base address register offset: mem_base + 34?37h attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains the beginning addr ess of the periodic frame list in the system memory. since the ich6 host controller operates in 64-bit mode (as indicated by the 1 in the 64-bit addressing capability field in the hccsparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data st ructure address comes fr om the ctrldssegment register. hcd loads this register prior to starting the schedule execution by the host controller. the memory structure referenced by this physical memo ry pointer is assumed to be 4-kbyte aligned. the contents of this register ar e combined with the fr ame index register (fri ndex) to enable the host controller to st ep through the periodic frame list in sequence. bit description 31:12 upper address[63:44] ? ro. hardwired to 0s. the ich6 ehc is only capable of generating addresses up to 16 terabytes (44 bits of address). 11:0 upper address[43:32] ? r/w. th is 12-bit field corresponds to addr ess bits 43:32 when forming a control data structure address. bit description 31:12 base address (low) ? r/w. these bits correspond to memory address signals [31:12], respectively. 11:0 reserved. must be written as 0?s. during runtime, the value of these bits are undefined.
intel ? i/o controller hub 6 (ich6) family datasheet 555 ehci controller registers (d29:f7) 14.2.2.7 asynclistaddr?current asynchronous list address register offset: mem_base + 38?3bh attribute: r/w default value: 00000000h size: 32 bits this 32-bit register contains th e address of the next asynchronous queue head to be executed. since the ich6 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit addressing capability field in the hccparams register) (offset 08h, bit 0), then the most significant 32 bits of every control data structure address comes from the ctrldssegment register (offset 08h). bits [4:0] of this register cannot be modified by system software and will always return 0?s when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte aligned. 14.2.2.8 configflag?conf igure flag register offset: mem_base + 6 0?63h attribute: r/w default value: 00000000h size: 32 bits this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. bit description 31:5 link pointer low (lpl) ? r/w. these bits correspond to memory address signals [31:5], respectively. this field may only reference a queue head (qh). 4:0 reserved. these bits are reserved and their value has no effect on operation. bit description 31:1 reserved. read from this field will always return 0. 0 configure flag (cf) ? r/w. host software sets this bit as the last action in its process of configuring the host controller. this bit controls the default port-routing contro l logic. bit values and side-effects are listed below. see section 4 of the ehci specification for operation details. 0 = port routing control logic default-routes each port to the classic host controllers (default). 1 = port routing control logic default-rout es all ports to this host controller.
556 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.2.9 portsc?port n stat us and control register offset: port 0: mem_base + 64 ? 67h port 1: mem_base + 68 ? 6bh port 2: mem_base + 6c ? 6fh port 3: mem_base + 70 ? 73h port 4: mem_base + 74 ? 77h port 5: mem_base + 78 ? 7bh port 6: mem_base + 7c ? 7fh port 7: mem_base + 80 ? 83h attribute: r/w, r/wc, ro default value: 00003000h size: 32 bits a host controller must implement one or more port registers. software uses the n_port information from the structural parameters register to determine how many ports need to be serviced. all ports have the structure defined below. software must not write to unreported port status and control registers. this register is in the suspend power well. it is only reset by hardware when the suspend power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no device connected ? port disabled. when a device is attached, the port state transitions to the attached state and system software will process this as with any status change notification. refer to sect ion 4 of the ehci specification for operational requirements for how change events interact with port suspend mode. bit description 31:23 reserved. these bits are reserved for future use and will return a value of 0?s when read. 22 wake on overcurrent enable (wkoc_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the overcurrent active bit (bit 4 of this register) is set. 21 wake on disconnect enable (wkdscnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from connected to disconnec ted (i.e., bit 0 of this register changes from 1 to 0). 20 wake on connect enable (wkcnnt_e) ? r/w. 0 = disable. (default) 1 = enable. writing this bit to a 1 enables the setting of the pme status bit in the power management control/status register (offset 54, bit 15) when the current connect status changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1).
intel ? i/o controller hub 6 (ich6) family datasheet 557 ehci controller registers (d29:f7) 19:16 port test control ? r/w. when this field is 0?s, the por t is not operating in a test mode. a non- zero value indicates that it is operating in test m ode and the specific test mode is indicated by the specific value. the encoding of the test mode bits are (0110b ? 1111b are reserved): refer to usb specification revision 2.0, chapter 7 for details on each test mode. 15:14 reserved ? r/w. should be written to =00b. 13 port owner ? r/w. default = 1b. this bit unconditionally goes to a 0 when the configured flag bit in the usb2.0_cmd register makes a 0 to 1 transition. system software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed dev ice). software writes a 1 to this bit when the attached device is not a high-speed device. a 1 in this bit means that a companion host controller owns and controls the port. see section 4 of t he ehci specification for operational details. 12 port power (pp) ? ro. read-only with a value of 1. this indicates that the port does have power. 11:10 line status ? ro.these bits reflect the current logical levels of the d+ (bit 11) and d? (bit 10) signal lines. these bits are used for de tection of low-speed usb devices prior to the port reset and enable sequence. this field is valid only when the port en able bit is 0 and the current connect status bit is set to a 1. 00 = se0 10 = j-state 01 = k-state 11 = undefined 9 reserved. this bit will return a 0 when read. 8 port reset ? r/w. default = 0. when software writes a 1 to this bit (from a 0), the bus reset sequence as defined in the usb specif ication, revision 2.0 is started. software writes a 0 to this bit to terminate the bus reset sequence. software must keep this bit at a 1 long enough to guarantee the reset sequence completes as specified in the usb specification, revision 2.0. 1 = port is in reset. 0 = port is not in reset. note: when software writes a 0 to this bit, there ma y be a delay before the bi t status changes to a 0. the bit status will not read as a 0 until after the reset has completed. if the port is in high- speed mode after reset is complete, the host cont roller will automatically enable this port (e.g., set the port enable bit to a 1). a host controller mu st terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1. for example: if the port detects that the atta ched device is high-speed during reset, then the host controller must have the port in the enabled st ate within 2 ms of software writing this bit to a 0. the hchalted bit (d29:f7:caplength + 24h, bit 12) in the usb2.0_sts register should be a 0 before software attempts to use this bit. the host controller may hold port reset asserted to a 1 when the hchalted bit is a 1. this bit is 0 if port power is 0 note: system software should not attempt to reset a port if the hchalted bit in the usb2.0_sts register is a 1. doing so wi ll result in undefined behavior. bit description value maximum interrupt interval 0000b test mode not enabled (default) 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b force_enable
558 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 7 suspend ? r/w. 0 = port not in suspend state.(default) 1 = port in suspend state. port enabled bit and suspend bit of this register define the port states as follows: when in suspend state, downstream propagation of data is blocked on this port, except for port reset. note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port depending on the activity on the port. the host controller will unconditionally set this bit to a 0 when software sets the force port resume bit to a 0 (from a 1). a write of 0 to th is bit is ignored by the host controller. if host software sets this bit to a 1 when the po rt is not enabled (i.e., port enabled bit is a 0) the results are undefined. 6 force port resume ? r/w. 0 = no resume (k-state) detected/driven on port. (default) 1 = resume detected/driven on port. software sets th is bit to a 1 to driv e resume signaling. the host controller sets this bit to a 1 if a j-to-k transition is detected while the port is in the suspend state. when this bit transitions to a 1 be cause a j-to-k transition is detected, the port change detect bit (d29:f7:caplength + 24h, bit 2) in the usb2.0_sts register is also set to a 1. if software sets this bit to a 1, the host controller must not set the port change detect bit. note: when the ehci controller owns the por t, the resume sequence follows the defined sequence documented in the usb specification, revision 2.0. the re sume signaling (full- speed 'k') is driven on the port as long as this bit remains a 1. software must appropriately time the resume and set this bit to a 0 when the appropriate amount of time has elapsed. writing a 0 (from 1) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). this bit will remain a 1 until t he port has switched to the high- speed idle. 5 overcurrent change ? r/wc. the functionality of this bit is not dependent upon the port owner. software clears this bit by writing a 1 to it. 0 = no change. (default) 1 = there is a change to overcurrent active. 4 overcurrent active ? ro. 0 = this port does not have an overcurrent condition. (default) 1 = this port currently has an overcurrent condition. th is bit will automaticall y transition from 1 to 0 when the over current condition is removed. t he ich6 automatically disables the port when the overcurrent active bit is 1. 3 port enable/disable change ? r/wc. for the root hub, this bit gets set to a 1 only when a port is disabled due to the appropriate conditi ons existing at the eof2 point (see chapter 11 of the usb specification for the definition of a port error). this bit is not set due to the disabled-to-enabled transition, nor due to a disconnect. software clears this bit by writing a 1 to it. 0 = no change in status. (default). 1 = port enabled/disabled status has changed. bit description port enabled suspend port state 0 x disabled 1 0 enabled 1 1 suspend
intel ? i/o controller hub 6 (ich6) family datasheet 559 ehci controller registers (d29:f7) 2 port enabled/disabled ? r/w. ports can only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writi ng a 1 to this bit. ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. note that the bit status does not change until the port state actual ly changes. there may be a delay in disabling or enabling a port due to other host controller and bus events. 0 = disable 1 = enable (default) 1 connect status change ? r/wc. this bit indicates a change has occurred in the port?s current connect status. software sets this bit to 0 by writing a 1 to it. 0 = no change (default). 1 = change in current connect status. the host contro ller sets this bit for all changes to the port device connect status, even if sy stem software has not cleared an existing connect status change. for example, the insertion status cha nges twice before system software has cleared the changed condition, hub hardware will be ?setting? an al ready-set bit (i.e., the bit will remain set). 0 current connect status ? ro. this value reflects the current state of the port, and may not correspond directly to the event that caused t he connect status change bit (bit 1) to be set. 0 = no device is present. (default) 1 = device is present on port. bit description
560 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.3 usb 2.0-based debug port register the debug port?s registers are located in the sa me memory area, defined by the base address register (mem_base), as the standard ehci re gisters. the base offset for the debug port registers (a0h) is declared in th e debug port base offset capability register at configuration offset 5ah (d29:f7:offset 5ah). the specific ehci po rt that supports this debug capability (port 0) is indicated by a 4-bit field (bits 20 ? 23) in the hcsparams register of the ehci controller. the address map of the debug port registers is shown in table 14-4 . notes: 1. all of these registers are implemented in the co re well and reset by pltrst#, ehc hcreset, and a ehc d3-to-d0 transition . 2. the hardware associated with this register provides no checks to ensure that software programs the interface correctly. how the hardware behaves when programmed illegally is undefined. 14.2.3.1 cntl_sts?control/status register offset: mem_base + a0h attribute: r/w, r/wc, ro, wo default value: 00000000h size: 32 bits table 14-4. debug port register address map mem_base + offset mnemonic register name default type a0?a3h cntl_sts control/status 00000000h r/w, r/wc, ro, wo a4?a7h usbpid usb pids 00000000h r/w, ro a8?abh databuf[3:0] data buffer (bytes 3:0) 00000000h r/w ac?afh databuf[7:4] data buffer (bytes 7:4) 00000000h r/w b0?b3h config configuration 00007f01h r/w bit description 31 reserved 30 owner_cnt ? r/w. 0 = ownership of the debug port is not fo rced to the ehci controller (default) 1 = ownership of the debug port is forced to the ehci controller (i.e. immedi ately taken away from the companion classic usb host controller) if the port was already owned by the ehci controller, then setting this bit has no effect. this bit overrides all of the ownership-related bits in the standard ehci registers. 29 reserved 28 enabled_cnt ? r/w. 0 = software can clear this by writing a 0 to it. the hardware clears this bit for the same conditions where the port enable/disable change bit (i n the portsc register) is set. (default) 1 = debug port is enabled for operation. software can directly set this bit if the port is already enabled in the associated portsc register (this is enforced by the hardware). 27:17 reserved 16 done_sts ? r/wc. software can clear this by writing a 1 to it. 0 = request not complete 1 = set by hardware to indicate that the request is complete.
intel ? i/o controller hub 6 (ich6) family datasheet 561 ehci controller registers (d29:f7) notes: 1. software should do read-modify-write operations to this register to preserve the contents of bits not being modified. this include reserved bits. 2. to preserve the usage of reserved bits in the futu re, software should always write the same value read from the bit until it is defined. reserved bits will always return 0 when read. 15:12 link_id_sts ? ro. this field identifie s the link interface. 0h = hardwired. indicates that it is a usb debug port. 11 reserved. this bit returns 0 when read. writes have no effect. 10 in_use_cnt ? r/w. set by software to indicate that t he port is in use. cleared by software to indicate that the port is free and may be used by other software. this bit is cleared after reset. (this bit has no affect on hardware.) 9:7 exception_sts ? ro. this field indicates the except ion when the error_good#_sts bit is set. this field should be ignored if the error_good#_sts bit is 0. 000 =no error. (default) note: this should not be seen, si nce this field should only be checked if there is an error. 001 =transaction error: indicates the usb 2.0 transaction had an error (crc, bad pid, timeout, etc.) 010 =hardware error. request was attempted (or in progress) when port was suspended or reset. all other combinations are reserved 6 error_good#_sts ? ro. 0 = hardware clears this bit to 0 after the proper completion of a read or write. (default) 1 = error has occurred. details on the nature of the error are provided in the exception field. 5 go_cnt ? wo. 0 = hardware clears this bit when hardware sets the done_sts bit. (default) 1 = causes hardware to perform a read or write request. note: writing a 1 to this bit when it is al ready set may result in undefined behavior. 4 write_read#_cnt ? r/w. software clears this bit to indicate that the current request is a read. software sets this bit to indicate that the current request is a write. 0 = read (default) 1 = write 3:0 data_len_cnt ? r/w. this field is used to indicate t he size of the data to be transferred. default = 0h. for write operations, this field is set by software to indicate to the hardware how many bytes of data in data buffer are to be transferred to the consol e. a value of 0h indicates that a zero-length packet should be sent. a value of 1?8 indicates 1?8 bytes are to be transferred. values 9?fh are illegal and how hardware behaves if used is undefined. for read operations, this field is se t by hardware to indicate to software how many bytes in data buffer are valid in response to a read operation. a value of 0h indicates that a zero length packet was returned and the state of data buffer is not defined. a value of 1?8 indicates 1?8 bytes were received. hardware is not allowed to return values 9?fh. the transferring of data always starts with byte 0 in the data area and moves toward byte 7 until the transfer size is reached. bit description
562 intel ? i/o controller hub 6 (i ch6) family datasheet ehci controller registers (d29:f7) 14.2.3.2 usbpid?usb pids register offset: mem_base + a4h attribute: r/w, ro default value: 00000000h size: 32 bits this dword register is used to communicate pid information between the usb debug driver and the usb debug port. the debug port uses some of th ese fields to generate usb packets, and uses other fields to return pid information to the usb debug driver. 14.2.3.3 databuf[7:0]?data bu ffer bytes[7:0] register offset: mem_base + a8?afh attribute: r/w default value: 0000000000000000h size: 64 bits this register can be accessed as 8 separate 8- bit registers or 2 separate 32-bit register. 14.2.3.4 config?configuration register offset: mem_base + b0?b3h attribute: r/w default value: 00007f01h size: 32 bits bit description 31:24 reserved: these bits wi ll return 0 when read. writes will have no effect. 23:16 received_pid_sts[23:16] ? ro. hardware updates this fi eld with the received pid for transactions in either direction. when the controller is writing data, this field is updated with the handshake pid that is received from the device. when the host controller is reading data, this field is updated with the data packet pid (if the device sent data), or the handshake pid (if the device naks the request). this field is valid w hen the hardware clears the go_done#_cnt bit. 15:8 send_pid_cnt[15:8] ? r/w. hardware sends this pid to begin the data packet when sending data to usb (i.e., write_read#_cnt is asserted). software typically sets this field to either data0 or data1 pid values. 7:0 token_pid_cnt[7:0] ? r/w. hardware sends this pid as the token pid for each usb transaction. software typically sets this fiel d to either in, out, or setup pid values. bit description 63:0 databuffer[63:0] ? r/w. this field is the 8 bytes of t he data buffer. bits 7:0 correspond to least significant byte (byte 0). bits 63:56 corres pond to the most significant byte (byte 7). the bytes in the data buffer must be written with data before software initiates a write request. for a read request, the data buffer contains valid dat a when done_sts bit (offset a0, bit 16) is cleared by the hardware, error_good#_sts (offse t a0, bit 6) is cleared by the hardware, and the data_length_cnt field (offset a0, bits 3:0) indicates the number of bytes that are valid. bit description 31:15 reserved 14:8 usb_address_cnf ? r/w. this 7-bit field identifies the usb device address used by the controller for all token pi d generation. (default = 7fh) 7:4 reserved 3:0 usb_endpoint_cnf ? r/w. this 4-bit field identifies the endpoint used by the controller for all token pid generation. (default = 01h)
intel ? i/o controller hub 6 (ich6) family datasheet 563 smbus controller registers (d31:f3) 15 smbus controller registers (d31:f3) 15.1 pci configuration registers (smbus?d31:f3) note: registers that are not shown should be treated as reserved (see section 6.2 for details). 15.1.1 vid?vendor identificat ion register (smbus?d31:f3) address: 00 ? 01h attribute: ro default value: 8086h size: 16 bits table 15-1. smbus controller pci register address map (smbus?d31:f3) offset mnemonic register name default type 00?01h vid vendor identification 8086 ro 02?03h did device identification 266ah ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0280h ro, r/wc 08h rid revision identification see register description. ro 09h pi programming interface 00h ro 0ah scc sub class code 05h ro 0bh bcc base class code 0ch ro 20?23h smb_base smbus base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h ro 2e?2fh sid subsystem identification 0000h r/wo 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see description ro 40h hostc host configuration 00h r/w bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel
564 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.1.2 did?device identification register (smbus?d31:f3) address: 02 ? 03h attribute: ro default value: 266ah size: 16 bits 15.1.3 pcicmd?pci command register (smbus?d31:f3) address: 04 ? 05h attributes:ro, r/w default value: 0000h size:16 bits bit description 15:0 device id ? ro. bit description 15:11 reserved 10 interrupt disable ? r/w. 0 = enable 1 = disables smbus to assert its pirqb# signal. 9 fast back to back enable (fbe) ? ro. hardwired to 0. 8 serr# enable (serr_en) ? r/w. 0 = enables serr# generation. 1 = disables serr# generation. 7 wait cycle control (wcc) ? ro. hardwired to 0. 6 parity error response (per) ? r/w. 0 = disable 1 = sets detected parity error bit (d31:f3:06, bit 15) when a parity error is detected. 5 vga palette snoop (vps) ? ro. hardwired to 0. 4 postable memory write enable (pmwe) ? ro. hardwired to 0. 3 special cycle enable (sce) ? ro. hardwired to 0. 2 bus master enable (bme) ? ro. hardwired to 0. 1 memory space enable (mse) ? ro. hardwired to 0. 0 i/o space enable (iose) ? r/w. 0 = disable 1 = enables access to the sm bus i/o space regi sters as defined by the base address register.
intel ? i/o controller hub 6 (ich6) family datasheet 565 smbus controller registers (d31:f3) 15.1.4 pcists?pci status register (smbus?d31:f3) address: 06 ? 07h attributes:ro, r/wc default value: 0280h size: 16 bits note: for the writable bits, software must write a 1 to cl ear bits that are set. writing a 0 to the bit has no effect. 15.1.5 rid?revision identific ation register (smbus?d31:f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = parity error detected. 14 signaled system error (sse) ? r/wc. 0 = no system error detected. 1 = system error detected. 13 received master abort (rma) ? ro. hardwired to 0. 12 received target abort (rta) ? ro. hardwired to 0. 11 signaled target abort (sta) ? r/wc. 0 = ich6 did not terminate transaction fo r this function with a target abort. 1 = the function is targeted with a transaction that the intel ? ich6 terminates with a target abort. 10:9 devsel# timing status (devt) ? ro. this 2-bit field defines the timing for devsel# assertion for positive decode. 01 = medium timing. 8 data parity error detected (dped) ? ro. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. 6 user definable features (udf) ? ro. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 0 because there are no capability list structures in this function 3 interrupt status (ints) ? ro. this bit indicates that an inte rrupt is pending. it is independent from the state of the interrupt enable bit in the pci command register. 2:0 reserved bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register
566 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.1.6 pi?programming interfa ce register (smbus?d31:f3) offset address: 09h attribute: ro default value: 00h size: 8 bits 15.1.7 scc?sub class code register (smbus?d31:f3) address offset: 0ah attributes: ro default value: 05h size: 8 bits 15.1.8 bcc?base class code register (smbus?d31:f3) address offset: 0bh attributes: ro default value: 0ch size: 8 bits 15.1.9 smb_base?smbus base address register (smbus?d31:f3) address offset: 20 ? 23h attribute: r/w, ro default value: 00000001h size: 32-bits bit description 7:0 reserved bit description 7:0 sub class code (scc) ? ro. 05h = sm bus serial controller bit description 7:0 base class code (bcc) ? ro. 0ch = serial controller. bit description 31:16 reserved ? ro 15:5 base address ? r/w. this field provides the 32-byte system i/o base address for the ich6 smb logic. 4:1 reserved ? ro 0 io space indicator ? ro. hardwired to 1 indicating that the smb logic is i/o mapped.
intel ? i/o controller hub 6 (ich6) family datasheet 567 smbus controller registers (d31:f3) 15.1.10 svid?subsyst em vendor identification register (smbus?d31:f2/f4) address offset: 2ch ? 2dh attribute:ro default value: 0000h size: 16 bits lockable: no power well:core 15.1.11 sid?subsystem iden tification register (smbus?d31:f2/f4) address offset: 2eh ? 2fh attribute:r/wo default value: 0000h size: 16 bits lockable: no power well:core 15.1.12 int_ln?interrupt li ne register (smbus?d31:f3) address offset: 3ch attributes: r/w default value: 00h size: 8 bits 15.1.13 int_pn?interrupt pi n register (s mbus?d31:f3) address offset: 3dh attributes: ro default value: see de scription size: 8 bits bit description 15:0 subsystem vendor id (svid) ? ro. the svid register, in combination with the subsystem id (sid) register, enables the operating system (os) to di stinguish subsystems from each other. the value returned by reads to this register is the same as that which was written by bios into the ide svid register. note: software can write to this register only once per core well reset. writes should be done as a single 16-bit cycle. bit description 15:0 subsystem id (sid) ? ro. the sid register, in combinati on with the svid register, enables the operating system (os) to distinguish subsystems from each other. the value returned by reads to this register is the same as that which wa s written by bios into the ide sid register. note: software can write to this register only once per core well reset. writes should be done as a single 16-bit cycle. bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the ich6. it is to communicate to software the interrupt line that the interrupt pin is connected to pirqb#. bit description 7:0 interrupt pin (int_pn) ? ro. this field reflects the value of d31ip.smip in chipset configuration space.
568 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.1.14 hostc?host configurati on register (smbus?d31:f3) address offset: 40h attribute: r/w default value: 00h size: 8 bits bit description 7:3 reserved 2 i 2 c_en ? r/w. 0 = smbus behavior. 1 = the ich6 is enabled to communicate with i 2 c devices. this will change the formatting of some commands. 1 smb_smi_en ? r/w. 0 = smbus interrupts will not generate an smi#. 1 = any source of an smb interrupt will instead be routed to generate an smi#. refer to section 5.21.4 (interrupts / smi#). this bit needs to be set for smbalert# to be enabled. 0 smbus host enable (hst_en) ? r/w. 0 = disable the smbus host controller. 1 = enable. the smb host controller interface is enabled to execute commands. the intren bit (offset smbase + 02h, bit 0) needs to be enabled for the smb host controller to interrupt or smi#. note that the smb host controller will not respond to any new requests until all interrupt requests have been cleared.
intel ? i/o controller hub 6 (ich6) family datasheet 569 smbus controller registers (d31:f3) 15.2 smbus i/o registers table 15-2. smbus i/o register address map smb_base + offset mnemonic register name default type 00h hst_sts host status 00h r/wc, ro, r/wc (special) 02h hst_cnt host control 00h r/w, wo 03h hst_cmd host command 00h r/w 04h xmit_slva transmit slave address 00h r/w 05h hst_d0 host data 0 00h r/w 06h hst_d1 host data 1 00h r/w 07h host_block_db host block data byte 00h r/w 08h pec packet error check 00h r/w 09h rcv_slva receive slave address 44h r/w 0a?0bh slv_data receive slave data 0000h ro 0ch aux_sts auxiliary status 00h r/wc, ro 0dh aux_ctl auxiliary control 00h r/w 0eh smlink_pin_ctl smlink pin control (tco compatible mode) see register description r/w, ro 0fh smbus_pin_ctl smbus pin control see register description r/w, ro 10h slv_sts slave status 00h r/wc 11h slv_cmd slave command 00h r/w 14h notify_daddr notify device address 00h ro 16h notify_dlow notify data low byte 00h ro 17h notify_dhigh notify data high byte 00h ro
570 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.2.1 hst_sts?host status register (smbus?d31:f3) register offset: smbase + 00h attribute: r/wc, r/wc (special), ro default value: 00h size: 8-bits all status bits are set by hardware and cleared by the software writing a one to the particular bit position. writing a 0 to any bit position has no effect. bit description 7 byte done status (ds) ? r/wc. 0 = software can clear this by writing a 1 to it. 1 = host controller received a byte (for block re ad commands) or if it has completed transmission of a byte (for block write commands) when the 32-by te buffer is not being used. note that this bit will be set, even on the last byte of the tr ansfer. this bit is not set when transmission is due to the lan interface heartbeat. this bit has no meaning for block transfe rs when the 32-byte buffer is enabled. note: when the last byte of a block message is receiv ed, the host controller will set this bit. however, it will not immediately set the intr bit (bit 1 in this register). when the interrupt handler clears the ds bit, the message is consi dered complete, and the host controller will then set the intr bit (and generate another interrupt). thus, for a block message of n bytes, the ich6 will generate n+1 interrupts. the interrupt handler needs to be implemented to handle these cases. 6 inuse_sts ? r/wc (special). this bi t is used as semaphore among various independent software threads that may need to use the ich6?s smbus logic, and has no other effect on hardware. 0 = after a full pci reset, a read to this bit returns a 0. 1 = after the first read, subsequent reads will return a 1. a write of a 1 to this bit will reset the next read value to 0. writing a 0 to this bit has no effe ct. software can poll this bit until it reads a 0, and will then own the usage of the host controller. 5 smbalert_sts ? r/wc. 0 = interrupt or smi# was not generated by smbalert #. software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was t he smbalert# signal. this bit is only cleared by software writing a 1 to the bit position or by rsmrst# going low. if the signal is programmed as a gpi, then this bit will never be set. 4 failed ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt or smi# was a fail ed bus transaction. this bit is set in response to the kill bit being set to terminate the host transaction. 3 bus_err ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = the source of the interrupt of smi# was a transaction collision.
intel ? i/o controller hub 6 (ich6) family datasheet 571 smbus controller registers (d31:f3) 15.2.2 hst_cnt?host contro l register (smbus?d31:f3) register offset: smbase + 02h attribute: r/w, wo default value: 00h size: 8-bits note: a read to this register will clear the byte pointer of the 32-byte buffer. 2 dev_err ? r/wc. 0 = software clears this bit by writing a 1 to it. t he ich6 will then de-assert the interrupt or smi#. 1 = the source of the interrupt or smi# was due to one of the following: ?illegal command field, ?unclaimed cycle (host initiated), ?host device time-out error. 1 intr ? r/wc (special). this bit can only be set by termination of a command. intr is not dependent on the intren bit (offset smbase + 02h, bit 0) of the host controller register (offset 02h). it is only dependent on the termination of the command. if the intren bit is not set, then the intr bit will be set, although the interrupt will not be generated. software can poll the intr bit in this non-interrupt case. 0 = software clears this bit by writing a 1 to it. the ich6 then de-asserts the interrupt or smi#. 1 = the source of the interrupt or smi# was the successful completion of its last command. 0 host_busy ? ro. 0 = cleared by the ich6 when the current transaction is completed. 1 = indicates that the ich6 is running a command fr om the host interface. no smb registers should be accessed while this bit is set, except the block data byte register. the block data byte register can be accessed when this bit is set only when the smb_cmd bits in the host control register are programmed for block command or i 2 c read command. this is necessary in order to check the done_sts bit. bit description bit description 7 pec_en . ? r/w. 0 = smbus host controller does not perfo rm the transaction with the pec phase appended. 1 = causes the host controller to perform the smbus transaction with the packet error checking phase appended. for writes, the value of the pec byte is transferred from the pec register. for reads, the pec byte is loaded in to the pec register. this bit must be written prior to the write in which the start bit is set. 6 start ? wo. 0 = this bit will always return 0 on reads. the host _busy bit in the host status register (offset 00h) can be used to identify when the intel ? ich6 has finished the command. 1 = writing a 1 to this bit initiates the comm and described in the smb_cmd field. all registers should be setup prior to writing a 1 to this bit position. 5 last_byte ? wo. this bit is used fo r block read commands. 1 = software sets this bit to indicate that the nex t byte will be the last byte to be received for the block. this causes the ich6 to send a nack (instead of an ack) after receiving the last byte. note: once the second_to_sts bit in tco2_sts register (d31:f0, tcobase+6h, bit 1) is set, the last_byte bit also gets set. wh ile the second_to_sts bit is set, the last_byte bit cannot be cleared. this prevents the ich6 from running some of the smbus commands (block read/write, i 2 c read, block i 2 c write).
572 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 4:2 smb_cmd ? r/w. the bit encoding below indicates which command the ich6 is to perform. if enabled, the ich6 will generate an interrupt or smi# when the command has completed if the value is for a non-supported or reserved command, the ich6 will set the device error (dev_err) status bit (offset smbase + 00h, bit 2) and generate an inte rrupt when the start bit is set. the ich6 will perform no command, and will not operate until dev_err is cleared. 000 = quick : the slave address and read/write value (bit 0) are stored in the transmit slave address register. 001 = byte : this command uses the transmit slave address and command registers. bit 0 of the slave address register determines if this is a read or write command. 010 = byte data : this command uses the transmit slave address, command, and data0 registers. bit 0 of the slave address register determines if this is a read or write command. if it is a read, the data0 register will contain the read data. 011 = word data : this command uses the transmit slave address, command, data0 and data1 registers. bit 0 of the slave address register det ermines if this is a read or write command. if it is a read, after the command completes, the data0 and data1 registers will contain the read data. 100 = process call: this command uses the transmit slav e address, command, data0 and data1 registers. bit 0 of the slave address register det ermines if this is a read or write command. after the command completes, the data0 and data1 registers will contain the read data. 101 = block : this command uses the transmit slave addr ess, command, data0 registers, and the block data byte register. for block write, th e count is stored in the data0 register and indicates how many bytes of dat a will be transferred. for blo ck reads, the count is received and stored in the data0 register. bit 0 of the slave address register selects if this is a read or write command. for writes, data is retrieved from the first n (where n is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. 110 = i 2 c read : this command uses the transmit sl ave address, command, data0, data1 registers, and the block data byte register. t he read data is stored in the block data byte register. the ich6 continues reading data until the nak is received. 111 = block process: this command uses the transmit slave address, command, data0 and the block data byte register. for block write, th e count is stored in the data0 register and indicates how many bytes of dat a will be transferred. for blo ck read, the count is received and stored in the data0 register. bit 0 of the sl ave address register always indicate a write command. for writes, data is retrieved from the first m (where m is equal to the specified count) addresses of the sram array. for reads, the data is stored in the block data byte register. note: e32b bit in the auxiliary control register must be set for this command to work. 1 kill ? r/w. 0 = normal smbus host controller functionality. 1 = kills the current host transaction taking place, sets the failed status bit, and asserts the interrupt (or smi#). this bit, once set, must be cleared by software to allow the smbus host controller to function normally. 0 intren ? r/w. 0 = disable. 1 = enable the generation of an interrupt or smi# upon the completion of the command. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 573 smbus controller registers (d31:f3) 15.2.3 hst_cmd?host command register (smbus?d31:f3) register offset: smbase + 03h attribute: r/w default value: 00h size: 8 bits 15.2.4 xmit_slva?transmit slave address register (smbus?d31:f3) register offset: smbase + 04h attribute: r/w default value: 00h size: 8 bits this register is transmitted by th e host controller in the slave ad dress field of the smbus protocol. 15.2.5 hst_d0?host data 0 register (smbus?d31:f3) register offset: smbase + 05h attribute: r/w default value: 00h size: 8 bits 15.2.6 hst_d1?host data 1 register (smbus?d31:f3) register offset: smbase + 06h attribute: r/w default value: 00h size: 8 bits bit description 7:0 this 8-bit field is transmitted by the host controller in the command field of the smbus protocol during the execution of any command. bit description 7:1 address ? r/w. this field provides a 7-bit address of the targeted slave. 0 rw ? r/w. direction of the host transfer. 0 = write 1 = read bit description 7:0 data0/count ? r/w. this field contains the 8-bit data sent in the data0 field of the smbus protocol. for block write commands, this register reflects the number of bytes to transfer. this register should be programmed to a value between 1 and 32 for block counts. a count of 0 or a count above 32 will result in unpr edictable behavior. the host controller does not check or log illegal block counts. bit description 7:0 data1 ? r/w. this 8-bit register is transmitted in t he data1 field of the smbus protocol during the execution of any command.
574 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.2.7 host_block_db?host block data byte register (smbus?d31:f3) register offset: smbase + 07h attribute: r/w default value: 00h size: 8 bits 15.2.8 pec?packet error check (pec) register (smbus?d31:f3) register offset: smbase + 08h attribute: r/w default value: 00h size: 8 bits bit description 7:0 block data (bdta) ? r/w. this is either a register, or a pointer into a 32-byte block array, depending upon whether the e32b bit is set in the auxiliary control register. when the e32b bit (offset smbase + 0dh, bit 1) is cleared, this is a r egister containing a byte of data to be sent on a block write or read from on a block read, just as it behaved on the ich3. when the e32b bit is set, reads and writes to this r egister are used to access the 32-byte block data storage array. an internal index pointer is used to address the array, which is reset to 0 by reading the hctl register (offset 02h). the index pointer then increments automatically upon each access to this register. the transfer of block data into (read) or out of (write) this storage array during an smbus transaction always starts at index address 0. when the e2b bit is set, for writes, software will writ e up to 32-bytes to this register as part of the setup for the command. after the host controller has sent the address, command, and byte count fields, it will send the bytes in t he sram pointed to by this register. when the e2b bit is cleared for writes, software will place a single byte in this register. after the host controller has sent the address, co mmand, and byte count fields, it will send the byte in this register. if there is more data to send, software will write the next series of bytes to the sram pointed to by this register and clear the done_sts bit. the cont roller will then send the next byte. during the time between the last byte being transmitted to the next byte being transmitted, the controller will insert wait-states on the interface. when the e2b bit is set for reads, after receiving the byte count into the data0 register, the first series of data bytes go into the sram pointed to by this register. if the byte count has been exhausted or the 32-byte sram has been filled, the controller will generate an smi# or interrupt (depending on configuration) and set t he done_sts bit. software will then read the data. during the time between when the last byte is read from the sram to when the done_sts bit is cleared, the controller will insert wait-states on the interface. bit description 7:0 pec_data ? r/w. this 8-bit register is written with the 8- bit crc value that is used as the smbus pec data prior to a write transaction. for read transactions, the pec data is loaded from the smbus into this register and is then read by software. software must ensure that the inuse_sts bit is properly maintained to avoid having this field ov er-written by a write transaction following a read transaction.
intel ? i/o controller hub 6 (ich6) family datasheet 575 smbus controller registers (d31:f3) 15.2.9 rcv_slva?receive slave address register (smbus?d31:f3) register offset: smbase + 09h attribute: r/w default value: 44h size: 8 bits lockable: no power well: resume 15.2.10 slv_data?receive slave data register (smbus?d31:f3) register offset: smbase + 0ah?0bh attribute: ro default value: 0000h size: 16 bits lockable: no power well: resume this register contains the 16-bit data value writt en by the external smbus master. the processor can then read the value from this register. this register is reset by rsmrst#, but not pltrst# . 15.2.11 aux_sts?auxiliary stat us register (smbus?d31:f3) register offset: smbase + 0ch attribute: r/wc, ro default value: 00h size: 8 bits lockable: no power well: resume . bit description 7reserved 6:0 slave_addr ? r/w. this field is the slave address that the intel ? ich6 decodes for read and write cycles. the default is not 0, so the smbus slave interface can respond even before the processor comes up (or if the processor is dead). th is register is cleared by rsmrst#, but not by pltrst#. bit description 15:8 data message byte 1 (data_msg1) ? ro. see section 5.21.7 for a discussion of this field. 7:0 data message byte 0 (data_msg0) ? ro. see section 5.21.7 for a discussion of this field. bit description 7:2 reserved 1 smbus tco mode (stco) ? ro. this bit reflects the strap setting of tco compatible mode vs. advanced tco mode. 0 = intel ? ich6 is in the compatible tco mode. 1 = ich6 is in the advanced tco mode. 0 crc error (crce) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set if a received message contained a crc error. when this bit is set, the derr bit of the host status register wi ll also be set. this bit will be set by the controller if a software abort occurs in the middle of the crc portion of the cycle or an abort happens after the ich6 has received the final data bit transmitted by an external slave.
576 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.2.12 aux_ctl?auxiliary cont rol register (smbus?d31:f3) register offset: smbase + 0dh attribute: r/w default value: 00h size: 8 bits lockable: no power well: resume . 15.2.13 smlink_pin_ctl?smli nk pin control register (smbus?d31:f3) register offset: smbase + 0eh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. this register is only applicable in the tco compatible mode. bit description 7:2 reserved 1 enable 32-byte buffer (e32b) ? r/w. 0 = disable. 1 = enable. when set, the host block data register is a pointer into a 32-byte buffer, as opposed to a single register. this enables t he block commands to transfer or receive up to 32-bytes before the ich6 generates an interrupt. 0 automatically append crc (aac) ? r/w. 0 = ich6 will not automatically append the crc. 1 = the ich6 will automatically append the crc. this bit must not be changed during smbus transactions or undetermined behavior will resul t. it should be programmed only once during the lifetime of the function. bit description 7:3 reserved 2 smlink_clk_ctl ? r/w. 0 = ich6 will drive the smlink0 pin low, i ndependent of what the other smlink logic would otherwise indicate for the smlink0 pin. 1 = the smlink0 pin is not overdriven low. the other smlink l ogic controls the state of the pin. (default) 1 smlink1_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink1 pin. this allows software to read the current state of the pin. 0 = low 1 = high 0 smlink0_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smlink0 pin. this allows software to read the current state of the pin. 0 = low 1 = high
intel ? i/o controller hub 6 (ich6) family datasheet 577 smbus controller registers (d31:f3) 15.2.14 smbus_pin_ctl?smb us pin control register (smbus?d31:f3) register offset: smbase + 0fh attribute: r/w, ro default value: see below size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 15.2.15 slv_sts?slave status register (smbus?d31:f3) register offset: smbase + 10h attribute: r/wc default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. all bits in this register are implemented in the 64 khz clock domain. therefore, software must poll this register until a write takes effect before assuming that a write has completed internally. bit description 7:3 reserved 2 smbclk_ctl ? r/w. 1 = the smbclk pin is not overdriven low. the other smbus l ogic controls the state of the pin. 0 = ich6 drives the smbclk pin low, independent of what the other smb logic would otherwise indicate for the smbclk pin. (default) 1 smbdata_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbdata pin. this allows software to read the current state of the pin. 0 = low 1 = high 0 smbclk_cur_sts ? ro. this read-only bit has a default value that is dependent on an external signal level. this pin returns the value on the smbc lk pin. this allows software to read the current state of the pin. 0 = low 1 = high bit description 7:1 reserved 0 host_notify_sts ? r/wc. the ich6 sets this bit to a 1 when it has completely received a successful host notify command on the smlink pins. software reads this bit to determine that the source of the interrupt or smi# was the reception of the host notify command. software clears this bit after reading any information needed from the noti fy address and data registers by writing a 1 to this bit. note that the ich6 will allow the notify address and data registers to be over-written once this bit has been cleared. when this bit is 1, the ich6 will nack the first byte (host address) of any new ?host notify? commands on the smlink. writing a 0 to this bit has no effect.
578 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3) 15.2.16 slv_cmd?slave command register (smbus?d31:f3) register offset: smbase + 11h attribute: r/w default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 15.2.17 notify_daddr?notify device address register (smbus?d31:f3) register offset: smbase + 14h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:2 reserved 2 smbalert_dis ? r/w. 0 = allows the generation of the interrupt or smi#. 1 = software sets this bit to block the generation of the interrupt or smi# due to the smbalert# source. this bit is logically inverted and anded with the smbalert_sts bit (offset smbase + 00h, bit 5). the resulting signal is distributed to the smi# and/or interrupt generation logic. this bit does not effect the wake logic. 1 host_notify_wken ? r/w. software sets this bit to 1 to enable the reception of a host notify command as a wake event. when enabled this event is ?or?ed in with the other smbus wake events and is reflected in the smb_wak_sts bit of the general purpose event 0 status register. 0 = disable 1 = enable 0 host_notify_intren ? r/w. software sets this bit to 1 to enable the generation of interrupt or smi# when host_notify_sts (offset smbase + 10h, bit 0) is 1. this enable does not affect the setting of the host_notify_sts bit. when the inte rrupt is generated, either pirqb# or smi# is generated, depending on the value of the smb_smi_en bit (d31:f3:40h, bit 1). if the host_notify_sts bit is set when this bit is writt en to a 1, then the interrupt (or smi#) will be generated. the interrupt (or smi#) is logically generated by and?ing the sts and intren bits. 0 = disable 1 = enable bit description 7:1 device_address ? ro. this field contains the 7-bit device address received during the host notify protocol of the smbus 2.0 specification. so ftware should only consider this field valid when the host_notify_sts bit (d31:f3:smbase +10, bit 0) is set to 1. 0reserved
intel ? i/o controller hub 6 (ich6) family datasheet 579 smbus controller registers (d31:f3) 15.2.18 notify_dlow?notify data low byte register (smbus?d31:f3) register offset: smbase + 16h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. 15.2.19 notify_dhigh?notify data high byte register (smbus?d31:f3) register offset: smbase + 17h attribute: ro default value: 00h size: 8 bits note: this register is in the resume well and is reset by rsmrst#. bit description 7:0 data_low_byte ? ro. this field contains the first (low ) byte of data received during the host notify protocol of the smbus 2.0 specification. software should only consider this field valid when the host_notify_sts bit (d31:f3:smbase +10, bit 0) is set to 1. bit description 7:0 data_high_byte ? ro. this field contains the second (h igh) byte of data received during the host notify protocol of the smbus 2.0 specificati on. software should only c onsider this field valid when the host_notify_sts bit (d31:f3 :smbase +10, bit 0) is set to 1.
580 intel ? i/o controller hub 6 (i ch6) family datasheet smbus controller re gisters (d31:f3)
intel ? i/o controller hub 6 (ich6) family datasheet 581 ac ?97 audio controller registers (d30:f2) 16 ac ?97 audio controller registers (d30:f2) 16.1 ac ?97 audio pci configuration space (audio?d30:f2) note: registers that are not shown s hould be treated as reserved. note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. all resume well registers will not be reset by the d3 hot to d0 transition. table 16-1. ac ?97 audio pci regi ster address map (audio?d30:f2) offset mnemonic register name default access 00?01h vid vendor identification 8086h ro 02?03h did device identification 266eh ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0280h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00 ro 0ah scc sub class code 01h ro 0bh bcc base class code 04h ro 0eh headtyp header type 00h ro 10?13h nambbar native audio mixer base address 00000001h r/w, ro 14?17h nammbar native audio bus mastering base address 00000001h r/w, ro 18?1bh mmbar mixer base address (mem) 00000000h r/w, ro 1c?1fh mbbar bus master base address (mem) 00000000h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 40h pcid programmable codec id 09h r/w 41h cfg configuration 00h r/w 50?51h pid pci power management capability id 0001h ro 52?53h pc pc -power management capabilities c9c2h ro 54?55h pcs power management control and status 0000h r/w, r/wc
582 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) core well registers not reset by the d3 hot to d0 transition: ? offset 2ch ? 2dh ? subsystem vendor id (svid) ? offset 2eh ? 2fh ? subsystem id (sid) ? offset 40h ? programmable codec id (pcid) ? offset 41h ? configuration (cfg) resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h ? 55h ? power management control and status (pcs) ? bus mastering register: global status register, bits 17:16 ? bus mastering regist er: sdata_in map register, bits 7:3 16.1.1 vid?vendor identificati on register (audio?d30:f2) offset: 00 ? 01h attribute: ro default value: 8086h size: 16 bits lockable: no power well: core 16.1.2 did?device identificat ion register (audio?d30:f2) offset: 02 ? 03h attribute: ro default value: 266eh size: 16 bits lockable: no power well: core bit description 15:0 vendor id. this is a 16-bit value assigned to intel. bit description 15:0 device id.
intel ? i/o controller hub 6 (ich6) family datasheet 583 ac ?97 audio controller registers (d30:f2) 16.1.3 pcicmd?pci command register (audio?d30:f2) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits lockable: no power well: core pcicmd is a 16-bit control register. refer to th e pci 2.3 specification for complete details on each bit. bit description 15:11 reserved. read 0. 10 interrupt disable (id) ? r/w. 0 = the intx# signals may be asserted and msis may be generated. 1 = the ac ?97 controller?s intx# signal w ill be de-asserted and it may not generate msis. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? ro. not implemented. hardwired to 0. 7 wait cycle control (wcc) ? ro. not implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps). not implemented. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce). not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. controls standard pci bus mastering capabilities. 0 = disable 1 = enable 1 memory space enable (mse) ? r/w. enables memory space addresses to the ac ?97 audio controller. 0 = disable 1 = enable 0 i/o space enable (iose) ? r/w. this bit controls access to the ac ?97 audio controller i/o space registers. 0 = disable (default). 1 = enable access to i/o space. the native pci mode base address register should be programmed prior to setting this bit. note: this bit becomes writable when the iose bit in offset 41h is set. if at any point software decides to clear the iose bit, softwa re must first clear the ios bit.
584 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.1.4 pcists?pci status register (a udio?d30:f2) offset: 06 ? 07h attribute: ro, r/wc default value 0280h size: 16 bits lockable: no power well: core pcista is a 16-bit status register. refer to th e pci 2.3 specification for complete details on each bit. bit description 15 detected parity error (dpe). not implemented. hardwired to 0. 14 signaled system error (sse) ? ro. not implemented. hardwired to 0. 13 master abort status (mas) ? r/wc. software clears this bit by writing a 1 to it. 0 = no master abort generated. 1 = bus master ac '97 2.3 interface func tion, as a master, generates a master abort. 12 reserved ? ro. will always read as 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field reflects the ich6's devsel# timing when performing a positive decode. 01b = medium timing. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwired to 1. this bit indicates that the ich6 as a target is capable of fast back-to-back transactions. 6 udf supported ? ro. not implemented. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. indicates that the controller cont ains a capabiliti es pointer list. the first item is pointed to by l ooking at configuration offset 34h. 3 interrupt status (is) ? ro. 0 = this bit is 0 after the interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. 2:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 585 ac ?97 audio controller registers (d30:f2) 16.1.5 rid?revision identific ation register (audio?d30:f2) offset: 08h attribute: ro default value: see bit description size: 8 bits lockable: no power well: core 16.1.6 pi?programming inter face register (audio?d30:f2) offset: 09h attribute: ro default value: 00h size: 8 bits lockable: no power well: core 16.1.7 scc?sub class code register (a udio?d30:f2) address offset: 0ah attribute: ro default value: 01h size: 8 bits lockable: no power well: core 16.1.8 bcc?base class code register (audio?d30:f2) address offset: 0bh attribute: ro default value: 04h size: 8 bits lockable: no power well: core bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. bit description 7:0 sub class code (scc) ? ro. 01h = audio device bit description 7:0 base class code (bcc) ? ro. 04h = multimedia device
586 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.1.9 headtyp?header type register (audio?d30:f2) address offset: 0eh attribute: ro default value: 00h size: 8 bits lockable: no power well: core 16.1.10 nambar?native audio mixer base address register (audio?d30:f2) address offset: 10 ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits lockable: no power well: core the native pci mode audio function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the native audio mixer softwa re interface. the mixer requires 256 bytes of i/o space. native audio mixer and modem co dec i/o registers are located from 00h to 7fh and reside in the codec. access to these registers will be decoded by the ac '97 controller and forwarded over the ac-link to the codec. the codec will then respond with the register value. in the case of the split codec implementation, accesse s to the different codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. note: the tertiary codec cannot be addr essed via this address space. the tertiary space is only available from the new mmbar register. this register powe rs up as read only and only becomes write-able when the iose bit in offset 41h is set. for description of these i/o registers, refer to the audio codec ?97 component specification, version 2.3 . bit description 7:0 header type ? ro. hardwired to 00h. bit description 31:16 hardwired to 0?s. 15:8 base address ? r/w. these bits are used in the i/o space decode of the native audio mixer interface registers. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for the ac ?97 mixer, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. this configuration yiel ds a maximum i/o block size of 256 bytes for this base address. 7:1 reserved. read as 0?s. 0 resource type indicator (rte) ? ro. this bit defaults to 0 and changes to 1 if the iose bit is set (d30:f2:offset 41h, bit 0). when 1, this bit indicates a request for i/o space.
intel ? i/o controller hub 6 (ich6) family datasheet 587 ac ?97 audio controller registers (d30:f2) 16.1.11 nabmbar?native audio bus mastering base address register (audio?d30:f2) address offset: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits lockable: no power well: core the native pci mode audio function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the native mode audio software interface. note: the dma registers for s/pdif* and microphone in 2 cannot be addressed via this address space. these dma functions are only available from th e new mbbar register. this register powers up as read only and only beco mes write-able when the iose bit in offset 41h is set. 16.1.12 mmbar?mixer base addr ess register (audio?d30:f2) address offset: 18 ? 1bh attribute: r/w, ro default value: 00000000h size: 32 bits lockable: no power well: core this bar creates 512 bytes of memory space to signify the ba se address of the register space. the lower 256 bytes of this space map to the same re gisters as the 256-byte i/o space pointed to by nambar. the lower 384 bytes are divided as follows: ? 128 bytes for the primary codec (offsets 00?7fh) ? 128 bytes for the secondary codec (offsets 80?ffh) ? 128 bytes for the tertiary codec (offsets 100h?17fh). ? 128 bytes of reserved space (offsets 180h?1ffh), returning all 0?s. bit description 31:16 hardwired to 0?s 15:6 base address ? r/w. these bits are used in the i/o space decode of the native audio bus mastering interface registers. the number of u pper bits that a device actually implements depends on how much of the address space the device will respond to. for ac '97 bus mastering, the upper 16 bits are hardwired to 0, while bits 15:6 are pr ogrammable. this configur ation yields a maximum i/o block size of 64 bytes for this base address. 5:1 reserved. read as 0?s. 0 resource type indicator (rte) ? ro. this bit defaults to 0 and changes to 1 if the iose bit is set (d30:f2:offset 41h, bit 0). when 1, this bit indicates a request for i/o space. bit description 31:9 base address ? r/w. this field provides the lower 32-bits of the 512-byte memory offset to use for decoding the primary, secondary, and tertiary codec?s mixer spaces. 8:3 reserved. read as 0?s. 2:1 type ? ro. hardwired to 00b to indicate t he base address exists in 32-bit address space 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for memory space.
588 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.1.13 mbbar?bus master base address register (audio?d30:f2) address offset: 1c ? 1fh attribute: r/w, ro default value: 00000000h size: 32 bits lockable: no power well: core this bar creates 256-bytes of memory space to signify the base addre ss of the bus master memory space. the lower 64-bytes of the space point ed to by this regist er point to the same registers as the mbbar. 16.1.14 svid?subsystem vendor identification register (audio?d30:f2) address offset: 2c ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the svid register, in combination with the subsystem id register (d30:f2:2eh), enable the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register . once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. bit description 31:8 base address ? r/w. this field provides the i/o offs et to use for decoding the pcm in, pcm out, and microphone 1 dma engines. 7:3 reserved. read as 0?s. 2:1 type ? ro. hardwired to 00b to indicate t he base address exists in 32-bit address space 0 resource type indicator (rte) ? ro. hardwired to 0 to indicate a request for memory space. bit description 15:0 subsystem vendor id ? r/wo.
intel ? i/o controller hub 6 (ich6) family datasheet 589 ac ?97 audio controller registers (d30:f2) 16.1.15 sid?subsystem identifica tion register (audio?d30:f2) address offset: 2e ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the sid register, in combination with the subsystem vendor id register (d30:f2:2ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. t 16.1.16 cap_ptr?capabilities poin ter register (audio?d30:f2) address offset: 34h attribute: ro default value: 50h size: 8 bits lockable: no power well: core this register indicates the of fset for the capability pointer. 16.1.17 int_ln?interrupt li ne register (audio?d30:f2) address offset: 3ch attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register indicates which pci interrupt li ne is used for the ac ?97 module interrupt. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro . this field indicates that the fi rst capability pointer offset is offset 50h bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich6. it is used to communicate to software the interrupt line that the interrupt pin is connected to.
590 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.1.18 int_pn?interrupt pi n register (audio?d30:f2) address offset: 3dh attribute: ro default value: see description size: 8 bits lockable: no power well: core this register indicates which pci interrupt pin is used for the ac '97 module interrupt. the ac '97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 16.1.19 pcid?programmable co dec identification register (audio?d30:f2) address offset: 40h attribute: r/w default value: 09h size: 8 bits lockable: no power well: core this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. the value in this register must be modified only before any ac ?97 codec accesses. 16.1.20 cfg?configuration register (audio?d30:f2) address offset: 41h attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register is used to specify the id for the secondary and tertiary codecs for i/o accesses. this register is not affected by the d3 hot to d0 transition. bit description 7:0 ac '97 interrupt routing ? ro. this reflects the value of d30ip. aaip in chipset configuration space. bit description 7:4 reserved. 3:2 tertiary codec id (tid ) ? r/w. these bits define the encoded id that is used to address the tertiary codec i/o space. bit 1 is the first bit sent and bit 0 is the second bit sent on acz_sdout during slot 0. 1:0 secondary codec id (scid) ? r/w. these two bits define the encoded id that is used to address the secondary codec i/o space. the two bits are the id that will be placed on slot 0, bits 0 and 1, upon an i/o access to the secondary codec. bit 1 is the first bit sent and bit 0 is the second bit sent on acz_sdout during slot 0. bit description 7:1 reserved?ro. 0 i/o space enable (iose) ? r/w. 0 = disable. the ios bit at offset 04h and the i/o space bars at offset 10h and 14h become read only registers. additionally, bit 0 of the i/o bars at offsets 10h and 14h are hardwired to 0 when this bit is 0. this is the default state for the i/o bars. bios must explicitly set this bit to allow a legacy driver to work. 1 = enable.
intel ? i/o controller hub 6 (ich6) family datasheet 591 ac ?97 audio controller registers (d30:f2) 16.1.21 pid?pci power manageme nt capability identification register (audio?d30:f2) address offset: 50 ? 51h attribute: ro default value: 0001h size: 16 bits lockable: no power well: core 16.1.22 pc?power management capabilities register (audio?d30:f2) address offset: 52 ? 53h attribute: ro default value: c9c2h size: 16 bits lockable: no power well: core this register is not affected by the d3 hot to d0 transition. bit description 15:8 next capability (next) ? ro. this field indicates that the next item in the list is at offset 00h. 7:0 capability id (cap) ? ro.this fi eld indicates that this pointer is a message signaled interrupt capability bit description 15:11 pme support ? ro. this field indicate s pme# can be generated from all d states. 10:9 reserved. 8:6 auxiliary current ? ro. this field reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi)?ro. this field indicates that no device-specific initialization is required. 4 reserved ? ro. 3 pme clock (pmec) ? ro. this field indicates that pci clock is not required to generate pme#. 2:0 version (ver) ? ro. this field indicates support for revision 1.1 of the pci power management specification .
592 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.1.23 pcs?power management control and status register (audio?d30:f2) address offset: 54 ? 55h attribute: r/w, r/wc default value: 0000h size: 16 bits lockable: no power well: resume bit description 15 pme status (pmes) ? r/wc. this bit resides in the resume we ll. software clears th is bit by writing a 1 to it. 0 = pme# signal not asserted by ac ?97 controller. 1 = this bit is set when the ac ?97 controller w ould normally assert the pme# signal independent of the state of the pme_en bit. 14:9 reserved ? ro. 8 power management event enable (pmee) ? r/w. 0 = disable. 1 = enable. when set, and if corresponding pmes is also set, the ac '97 controller sets the ac97_sts bit in the gpe0_sts register 7:2 reserved?ro. 1:0 power state (ps) ? r/w. this field is used both to determ ine the current power state of the ac ?97 controller and to set a new power state. the values are: 00 = d0 state 01 = not supported 10 = not supported 11 = d3 hot state when in the d3 hot state, the ac ?97 controller?s configur ation space is available, but the i/o and memory spaces are not. additi onally, interrupts are blocked. if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs.
intel ? i/o controller hub 6 (ich6) family datasheet 593 ac ?97 audio controller registers (d30:f2) 16.2 ac ?97 audio i/o space (d30:f2) the ac ?97 i/o space includes native audio bus ma ster registers and native mixer registers. for the ich6, the offsets are importan t as they will determine bits 1:0 of the tag field (codec id). audio mixer i/o space can be accessed as a 16-bit fi eld only since the data packet length on ac-link is a word. any s/w access to the codec will be done as a 16-b it access starting from the first active byte. in case no byte enables are activ e, the access will be done at the first word of the qword that contains the address of this request. table 16-2. intel ? ich6 audio mixer register configuration primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10) nambar exposed registers (d30:f2) 00h 80h 100h reset 02h 82h 102h master volume 04h 84h 104h aux out volume 06h 86h 106h mono volume 08h 88h 108h master tone (r & l) 0ah 8ah 10ah pc_beep volume 0ch 8ch 10ch phone volume 0eh 8eh 10eh mic volume 10h 90h 110h line in volume 12h 92h 112h cd volume 14h 94h 114h video volume 16h 96h 116h aux in volume 18h 98h 118h pcm out volume 1ah 9ah 11ah record select 1ch 9ch 11ch record gain 1eh 9eh 11eh record gain mic 20h a0h 120h general purpose 22h a2h 122h 3d control 24h a4h 124h ac ?97 reserved 26h a6h 126h powerdown ctrl/stat 28h a8h 128h extended audio 2ah aah 12ah extended audio ctrl/stat 2ch ach 12ch pcm front dac rate 2eh aeh 12eh pcm surround dac rate 30h b0h 130h pcm lfe dac rate 32h b2h 132h pcm lr adc rate 34h b4h 134h mic adc rate 36h b6h 136h 6ch vol: c, lfe 38h b8h 138h 6ch vol: l, r surround 3ah bah 13ah s/pdif control 3c?56h bc?d6h 13c?156h intel reserved 58h d8h 158h ac ?97 reserved
594 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) note: 1. software should not try to access reserved registers 2. primary codec id cannot be changed. secondary codec id can be changed via bits 1:0 of configuration register 40h. tertiary codec id can be changed vi a bits 3:2 of configuration register 40h. 3. the tertiary offset is only available through the memory space defined by the mmbar register. the bus master registers are located from offset + 00h to offset + 51h and reside in the ac ?97 controller. accesses to these registers do not cause the cycle to be fo rwarded over the ac-link to the codec. s/w could access these registers as byte s, word, dword or qword quantities, but reads must not cross dword boundaries. in the case of the split codec imp lementation accesses to the differen t codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec, address offsets 80h ? ffh for the secondary codec and address offsets 100h ? 17fh for the tertiary codec. the global control (glob_cnt) (d30:f2:2ch) and global status (glob_sta) (d30:f2:30h) registers are aliased to the same global register s in the audio and mode m i/o space. therefore a read/write to these registers in either audio or modem i/o space aff ects the same physical register. bus mastering registers exist in i/o space and resi de in the ac ?97 controller. the six channels, pcm in, pcm in 2, pcm out, mic in, mic 2, an d s/pdif out, each have their own set of bus mastering registers. the followi ng register descriptions apply to all six channels. the register definition section titles use a generic ?x_? in front of the register to indicate that the register applies to all six channels. the nami ng prefix convention used in table 16-3 and in the register description i/o address is as follows: pi = pcm in channel po = pcm out channel mc = mic in channel mc2 = mic 2 channel pi2 = pcm in 2 channel sp = s/pdif out channel. 5ah dah 15ah vendor reserved 7ch fch 17ch vendor id1 7eh feh 17eh vendor id2 table 16-2. intel ? ich6 audio mixer register configuration primary offset (codec id =00) secondary offset (codec id =01) tertiary offset (codec id =10) nambar exposed registers (d30:f2) table 16-3. native audio bus master control registers (sheet 1 of 2) offset mnemonic name default access 00h pi_bdbar pcm in buffer descriptor list base address 00000000h r/w 04h pi_civ pcm in current index value 00h ro 05h pi_lvi pcm in last valid index 00h r/w 06h pi_sr pcm in status 0001h r/wc, ro 08h pi_picb pcm in position in current buffer 0000h ro 0ah pi_piv pcm in prefetched index value 00h ro 0bh pi_cr pcm in control 00h r/w, r/w (special) 10h po_bdbar pcm out buffer descriptor list base address 00000000h r/w
intel ? i/o controller hub 6 (ich6) family datasheet 595 ac ?97 audio controller registers (d30:f2) 14h po_civ pcm out current index value 00h ro 15h po_lvi pcm out last valid index 00h r/w 16h po_sr pcm out status 0001h r/wc, ro 18h po_picb pcm in position in current buffer 0000h ro 1ah po_piv pcm out prefetched index value 00h ro 1bh po_cr pcm out control 00h r/w, r/w (special) 20h mc_bdbar mic. in buffer descriptor list base address 00000000h r/w 24h mc_civ mic. in current index value 00h ro 25h mc_lvi mic. in last valid index 00h r/w 26h mc_sr mic. in status 0001h r/wc, ro 28h mc_picb mic. in position in current buffer 0000h ro 2ah mc_piv mic. in prefetched index value 00h ro 2bh mc_cr mic. in control 00h r/w, r/w (special) 2ch glob_cnt global control 00000000h r/w, r/w (special) 30h glob_sta global status see register description r/w, r/wc, ro 34h cas codec access semaphore 00h r/w (special) 40h mc2_bdbar mic. 2 buffer descriptor list base address 00000000h r/w 44h mc2_civ mic. 2 current index value 00h ro 45h mc2_lvi mic. 2 last valid index 00h r/w 46h mc2_sr mic. 2 status 0001h ro, r/wc 48h mc2_picb mic 2 position in current buffer 0000h ro 4ah mc2_piv mic. 2 prefetched index value 00h ro 4bh mc2_cr mic. 2 control 00h r/w, r/w (special) 50h pi2_bdbar pcm in 2 buffer descriptor list base address 00000000h r/w 54h pi2_civ pcm in 2 current index value 00h ro 55h pi2_lvi pcm in 2 last valid index 00h r/w 56h pi2_sr pcm in 2 status 0001h r/wc, ro 58h pi2_picb pcm in 2 position in current buffer 0000h ro 5ah pi2_piv pcm in 2 prefetched index value 00h ro 5bh pi2_cr pcm in 2 control 00h r/w, r/w (special) 60h spbar s/pdif buffer descriptor list base address 00000000h r/w 64h spciv s/pdif current index value 00h ro 65h splvi s/pdif last valid index 00h r/w 66h spsr s/pdif status 0001h r/wc, ro 68h sppicb s/pdif position in current buffer 0000h ro 6ah sppiv s/pdif prefetched index value 00h ro 6bh spcr s/pdif control 00h r/w, r/w (special) 80h sdm sdata_in map 00h r/w, ro table 16-3. native audio bus master control registers (sheet 2 of 2) offset mnemonic name default access
596 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac ?97 modem (gcr, gsr, casr). all resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 2ch ? 2fh ? bits 6:0 global control (glob_cnt) ? offset 30h ? 33h ? bits [29,15,11:10,0] global status (glob_sta) ? offset 34h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 30h ? 33h ? bits [17:16] global status (glob_sta) 16.2.1 x _bdbar?buffer descriptor base address register (audio?d30:f2) i/o address: nabmbar + 00h (p ibdbar), attribute: r/w nabmbar + 10h (pobdbar), nabmbar + 20h (mcbdbar) mbbar + 40h (mc2bdbar) mbbar + 50h (pi2bdbar) mbbar + 60h (spbar) default value: 00000000h size: 32 bits lockable: no power well: core software can read the register at offset 00h by pe rforming a single 32-bit read from address offset 00h. reads across dword boundaries are not supported. bit description 31:3 buffer descriptor base address[31:3] ? r/w. these bits represent address bits 31:3. the data should be aligned on 8-byte boundaries. each buffer descriptor is 8 bytes long and the list can contain a maximum of 32 entries. 2:0 hardwired to 0.
intel ? i/o controller hub 6 (ich6) family datasheet 597 ac ?97 audio controller registers (d30:f2) 16.2.2 x _civ?current index valu e register (audio?d30:f2) i/o address: nabmbar + 04h (piciv), attribute: ro nabmbar + 14h (pociv), nabmbar + 24h (mcciv) mbbar + 44h (mc2civ) mbbar + 54h (pi2civ) mbbar + 64h (spciv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 04h. note: reads across dword boundaries are not supported. 16.2.3 x _lvi?last valid index re gister (audio?d30:f2) i/o address: nabmbar + 05h (pilvi), attribute: r/w nabmbar + 15h (polvi), nabmbar + 25h (mclvi) mbbar + 45h (mc2lvi) mbbar + 55h (pi2lvi) mbbar + 65h (splvi) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 05h. note: reads across dword boundaries are not supported. bit description 7:5 hardwired to 0 4:0 current index value [4:0] ? ro. these bits represent which buffer descriptor within the list of 32 descriptors is currently being processed. as each de scriptor is processed, this value is incremented. the value rolls over after it reaches 31. bit description 7:5 hardwired to 0. 4:0 last valid index [4:0] ? r/w. this value represents the last va lid descriptor in the list. this value is updated by the software each time it prepar es a new buffer and adds it to the list.
598 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.2.4 x _sr?status register (audio?d30:f2) i/o address: nabmbar + 06h (pisr), attribute: r/wc, ro nabmbar + 16h (posr), nabmbar + 26h (mcsr) mbbar + 46h (mc2sr) mbbar + 56h (pi2sr) mbbar + 66h (spsr) default value: 0001h size: 16 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 16-bit read to offset 06h. reads across dword boundaries are not supported. bit description 15:5 reserved. 4 fifo error (fifoe) ? r/wc. software clears this bit by writing a 1 to it. 0 = no fifo error. 1 = fifo error occurs. pisr register: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thus is lost. posr register: fifo error indicates a fifo underrun. th e sample transmitted in this case should be the last valid sample. the ich6 will set the fifoe bit if the under-run or overrun occurs when there are more valid buffers to process. 3 buffer completion interrupt status (bcis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command by te of the buffer descriptor. it remains active until cleared by software. 2 last valid buffer completion interrupt (lvbci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = last valid buffer has been processed. it remain s active until cleared by software. this bit indicates the occurrence of the event signified by the last valid buffer being processed. thus this is an event status bit that can be cl eared by software once this event has been recognized. this event will cause an interrupt if the enable bit (d30:f2:nabmbar + 0bh, bit 2) in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). while in the case of receives , this bit is set after the data for the last buffer has been written to memory. 1 current equals last valid (celv) ? ro. 0 = cleared by hardware when controller exists stat e (i.e., until a new value is written to the lvi register.) 1 = current index is equal to the value in the last valid index register (d30:f2:nabmbar + 05h), and the buffer pointed to by the civ has been pr ocessed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except this bit reflects the state rather than the event. this bit reflects the state of the controller , and remains set until the controller exits this state. 0 dma controller halted (dch) ? ro. 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controller has processed the last valid buffer.
intel ? i/o controller hub 6 (ich6) family datasheet 599 ac ?97 audio controller registers (d30:f2) 16.2.5 x _picb?position in curre nt buffer register (audio?d30:f2) i/o address: nabmbar + 08h (pipicb), attribute: ro nabmbar + 18h (popicb), nabmbar + 28h (mcpicb) mbbar + 48h (mc2picb) mbbar + 58h (pi2picb) mbbar + 68h (sppicb) default value: 0000h size: 16 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 16-bit read to offset 08h. reads across dword boundaries are not supported. 16.2.6 x _piv?prefetched index valu e register (audio?d30:f2) i/o address: nabmbar + 0a h (pipiv), attribute: ro nabmbar + 1ah (popiv), nabmbar + 2ah (mcpiv) mbbar + 4ah (mc2piv) mbbar + 5ah (pi2piv) mbbar + 6ah (sppiv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0ah. reads across dword boundaries are not supported bit description 15:0 position in current buffer [15:0] ? ro. these bits represent the number of samples left to be processed in the current buffer. once again, this means, the number of samples not yet read from memory (in the case of reads from memory) or not yet written to memory (in the case of writes to memory), irrespective of the number of sa mples that have been transmitted/received across ac-link. bit description 7:5 hardwired to 0. 4:0 prefetched index value [4:0] ? ro. these bits represent which buffer descriptor in the list has been prefetched. the bits in this register are also modulo 32 and roll over after they reach 31.
600 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) 16.2.7 x _cr?control regis ter (audio?d30:f2) i/o address: nabmbar + 0bh (picr) , attribute: r/w, r/w (special) nabmbar + 1bh (pocr), nabmbar + 2bh (mccr) mbbar + 4bh (mc2cr) mbbar + 5bh (pi2cr) mbbar + 6bh (spcr) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. soft ware can also read this register indi vidually by doing a single, 8-bit read to offset 0bh. reads across dword boundaries are not supported. bit description 7:5 reserved. 4 interrupt on completion enable (ioce) ? r/w. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable. interrupt will not occur. 1 = enable. 3 fifo error interrupt enable (feie) ? r/w. this bit controls whet her the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register will be set, but the interrupt will not occur. 1 = enable. interrupt will occur. 2 last valid buffer interrupt enable (lvbie) ? r/w. this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable. 1 reset registers (rr) ? r/w (special). 0 = removes reset condition. 1 = contents of all bus master related registers to be reset, except the interrupt enable bits (bit 4,3,2 of this register). software needs to set this bit but need not clear it since the bit is self clearing. this bit must be set only when the r un/pause bit (d30:f2:2bh, bit 0) is cleared. setting it when the run bit is set will cause undefined consequences. 0 run/pause bus master (rpbm) ? r/w. 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = run. bus master operation starts.
intel ? i/o controller hub 6 (ich6) family datasheet 601 ac ?97 audio controller registers (d30:f2) 16.2.8 glob_cnt?global cont rol register (audio?d30:f2) i/o address: nabmbar + 2ch attr ibute: r/w, r/w (special) default value: 00000000h size: 32 bits lockable: no power well: core bit description 31:30 s/pdif slot map (ssm) ? r/w. if the run/pause bus master bit (bit 0 of offset 2bh) is set, then the value in these bits indicate which slots s/pdif da ta is transmitted on. software must ensure that the programming here does not conflict with the pcm channels being used. if there is a conflict, unpredictable behavior will resu lt ? the hardware will not check for a conflict. 00 = reserved 01 = slots 7 and 8 10 = slots 6 and 9 11 = slots 10 and 11 29:24 reserved. 23:22 pcm out mode (pom) ? r/w. enables the pcm out channel to use 16- or 20-bit audio on pcm out. this does not affect the microphone of s/pd if dma. when greater than 16-bit audio is used, the data structures are aligned as 32-bits per sa mple, with the highest order bits representing the data, and the lower order bits as don?t care. 00 = 16 bit audio (default) 01 = 20 bit audio 10 = reserved. if set, indeterminate behavior will result. 11 = reserved. if set, indeterminate behavior will result. 21:20 pcm 4/6 enable ? r/w. this field configures pcm output for 2-, 4- or 6-channel mode. 00 = 2-channel mode (default) 01 = 4-channel mode 10 = 6-channel mode 11 = reserved 19:7 reserved. 6 acz_sdin2 interrupt enable ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on the acz_sdin2 causes a resume event on the ac-link. note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset. 5 acz_sdin1 interrupt enable ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on the acz_sdin1 causes a resume event on the ac-link. note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset. 4 acz_sdin0 interrupt enable ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on acz_sdin0 causes a resume event on the ac-link. note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset. 3 ac-link shut off (lso) ? r/w. 0 = normal operation. 1 = controller disables all out puts which will be pulled low by internal pull down resistors. note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset.
602 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) note: reads across dword boundaries are not supported. 2 ac ?97 warm reset ? r/w (special). 0 = normal operation. 1 = writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal registers. if software attempts to perform a warm reset while bit_clk is running, the write wi ll be ignored and the bit will not change. this bit is self-clearing (it remains set until the reset co mpletes and bit_clk is seen on the ac-link, after which it clears itself). note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset. 1 ac ?97 cold reset# ? r/w. 0 = writing a 0 to this bit causes a cold reset to oc cur throughout the ac ?97 circuitry. all data in the controller and the codec will be lost. software needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to 0 and hence after reset, the dr iver needs to set this bit to a 1. the value of this bit is retained after suspends; h ence, if this bit is set to a 1 prior to suspending, a cold reset is not generated automat ically upon resuming. note: this bit is in the core well and is not affected by ac ?97 audio function d3 hot to d0 reset. 0 gpi interrupt enable (gie) ? r/w. this bit controls whethe r the change in status of any gpi causes an interrupt. 0 = bit 0 of the global status regist er is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. note: this bit is not affected by ac ?97 audio function d3 hot to d0 reset. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 603 ac ?97 audio controller registers (d30:f2) 16.2.9 glob_sta?global stat us register (audio?d30:f2) i/o address: nabmbar + 30h attribute: ro, r/w, r/wc default value: 00x0xxx01110000000000xxxxx00xxxbsize: 32 bits lockable: no power well: core bit description 31:30 reserved. 29 acz_sdin2 resume interrupt (s2ri) ? r/wc. this bit indicates a resume event occurred on acz_sdin2. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 28 acz_sdin2 codec ready (s2cr) ? ro. reflects the state of the codec ready bit on acz_sdin2. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 27 bit clock stopped (bcs) ? ro. this bit indicates that the bit clock is not running. 0 = transition is found on bit_clk. 1 = ich6 detected that there has been no transition on bit_clk for four consecutive pci clocks. 26 s/pdif interrupt (spint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = s/pdif out channel interrupt status bits have been set. 25 pcm in 2 interrupt (p2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in 2 channel status bits have been set. 24 microphone 2 in interrupt (m2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 23:22 sample capabilities ? ro. this field indicates the capabilit y to support more greater than 16-bit audio. 00 = reserved 01 = 16 and 20-bit audio supported (ich6 value) 10 = reserved 11 = reserved 21:20 multichannel capabilities ? ro. this field indicates the cap ability to support more 4 and 6 channels on pcm out. 19:18 reserved. 17 md3 ? r/w. power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. 16 ad3 ? r/w. power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset.
604 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2) note: reads across dword boundaries are not supported. 15 read completion status (rcs) ? r/wc. this bit indicates the status of codec read completions. 0 = a codec read completes normally. 1 = a codec read results in a time-out. the bit remains set until being cleared by software writing a 1 to the bit location. this bit is not affected by d3 hot to d0 reset. 14 bit 3 of slot 12 ? ro. display bit 3 of the most recent slot 12. 13 bit 2 of slot 12 ? ro. display bit 2 of the most recent slot 12. 12 bit 1 of slot 12 ? ro. display bit 1 of the most recent slot 12. 11 acz_sdin1 resume interrupt (s1r1) ? r/wc. this bit indicates that a resume event occurred on acz_sdin1. software clears this bit by writing a 1 to it. 0 = resume event did not occur 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 10 acz_sdin0 resume interrupt (s0r1) ? r/wc. this bit indicates that a resume event occurred on acz_sdin0. software clears this bit by writing a 1 to it. 0 = resume event did not occur 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 9 acz_sdin1 codec ready (s1cr) ? ro. reflects the state of the codec ready bit in acz_sdin1. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?r eady?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 8 acz_sdin0 codec ready (s0cr) ? ro. reflects the state of the codec ready bit in acz_sdin0. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?r eady?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 7 microphone in interrupt (mint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel inte rrupts status bits has been set. 6 pcm out interrupt (point) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm out channel interrupts status bits has been set. 5 pcm in interrupt (piint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in channel interrupts status bits has been set. 4:3 reserved 2 modem out interrupt (moint ) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem out channel interrupts status bits has been set. 1 modem in interrupt (miint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem in channel interrupts status bits has been set. 0 gpi status change interrupt (gsci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit reflects the state of bit 0 in slot 12, a nd is set when bit 0 of slot 12 is set. this indicates that one of the gpi?s changed state, and that th e new values are available in slot 12. this bit is not affected by ac ?97 audio function d3 hot to d0 reset. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 605 ac ?97 audio controller registers (d30:f2) 16.2.10 cas?codec access sema phore register (audio?d30:f2) i/o address: nabmbar + 34h attribute: r/w (special) default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. 16.2.11 sdm?sdata_in map register (audio?d30:f2) i/o address: nabmbar + 80h attribute: r/w, ro default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 7:1 reserved. 0 codec access semaphore (cas) ? r/w (special). this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit can then perform an i/o access. once the access is complet ed, hardware automatically clears this bit. bit description 7:6 pcm in 2, microphone in 2 data in line (di2l) ? r/w. when the se bit is se t, these bits indicates which acz_sdin line should be used by the hardwar e for decoding the input slots for pcm in 2 and microphone in 2. when the se bit is cleared, the va lue of these bits are irrelevant, and pcm in 2 and mic in 2 dma engines are not available. 00 = acz_sdin0 01 = acz_sdin1 10 = acz_sdin2 11 = reserved 5:4 pcm in 1, microphone in 1 data in line (di1l) ? r/w. when the se bit is se t, these bits indicates which acz_sdin line should be used by the hardwar e for decoding the input slots for pcm in 1 and microphone in 1. when the se bit is cleared, the val ue of these bits are irrelevant, and the pcm in 1 and mic in 1 engines use the or?d acz_sdin lines. 00 = acz_sdin0 01 = acz_sdin1 10 = acz_sdin2 11 = reserved 3 steer enable (se) ? r/w. when set, the acz_sdin lines are treated separately and not or?d together before being sent to the dma engines. when cleared, the acz_sdin lines are or?d together, and the ?microphone in 2? and ?pcm in 2? dma engines are not available. 2 reserved ? ro. 1:0 last codec read data input (ldi) ? ro. when a codec register is read, this indicates which acz_sdin the read data returned on. software can use this to determine how the codecs are mapped. the values are: 00 = acz_sdin0 01 = acz_sdin1 10 = acz_sdin2 11 = reserved
606 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 audio controller registers (d30:f2)
intel ? i/o controller hub 6 (ich6) family datasheet 607 ac ?97 modem controller registers (d30:f3) 17 ac ?97 modem controller registers (d30:f3) 17.1 ac ?97 modem pci configuration space (d30:f3) note: registers that are not shown s hould be treated as reserved. note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the following bios programmed registers as bios may not be invoked following the d3-to-d0 transition. all resume well registers will not be reset by the d3 hot to d0 transition. core well registers not reset by the d3 hot to d0 transition: ? offset 2ch ? 2dh ? subsystem vendor id (svid) ? offset 2eh ? 2fh ? subsystem id (sid) resume well registers will not be reset by the d3 hot to d0 transition: ? offset 54h ? 55h ? power management control and status (pcs) table 17-1. ac ?97 modem pci register address map (modem?d30:f3) offset mnemonic register default access 00?01h vid vendor identification 8086 ro 02?03h did device identification 266dh ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0290h r/wc, ro 08h rid revision identification see register description ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 07h ro 0eh headtyp header type 00h ro 10?13h mmbar modem mixer base address 00000001h r/w, ro 14?17h mbar modem base address 00000001h r/w, ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h cap_ptr capabilities pointer 50h ro 3ch int_ln interrupt line 00h r/w 3dh int_pn interrupt pin see register description ro 50?51h pid pci power management capability id 0001h ro 52?53h pc power management capabilities c9c2h ro 54?55h pcs power management control and status 0000h r/w, r/wc
608 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.1.1 vid?vendor identificati on register (modem?d30:f3) address offset: 00 ? 01h attribute: ro default value: 8086 size: 16 bits lockable: no power well: core 17.1.2 did?device identificat ion register (modem?d30:f3) address offset: 02 ? 03h attribute: ro default value: 266dh size: 16 bits lockable: no power well: core 17.1.3 pcicmd?pci command register (modem?d30:f3) address offset: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits lockable: no power well: core pcicmd is a 16-bit control register. refer to the pci local bus specification for complete details on each bit. bit description 15:0 vendor id. bit description 15:0 device id. bit description 15:11 reserved. read 0. 10 interrupt disable (id) ? r/w. 0 = the intx# signals may be asserted and msis may be generated. 1 = the ac ?97 controller?s intx# signal wi ll be de-asserted and it may not generate msis. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? ro. not implemented. hardwired to 0. 7 wait cycle control (wcc) ? ro. not implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps) ? ro. not implemented. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce) ? ro. not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls standard pci bus mastering capabilities. 0 = disable 1 = enable 1 memory space enable (mse) ? ro. hardwired to 0, ac ?97 does not respond to memory accesses. 0 i/o space enable (iose) ? r/w. this bit controls access to the i/o space registers. 0 = disable access. (default = 0). 1 = enable access to i/o space. the native pci mode base address register should be programmed prior to setting this bit.
intel ? i/o controller hub 6 (ich6) family datasheet 609 ac ?97 modem controller registers (d30:f3) 17.1.4 pcists?pci status register (modem?d30:f3) address offset: 06 ? 07h attribute: r/wc, ro default value: 0290h size: 16 bits lockable: no power well: core pcista is a 16-bit status register. refer to the pci local bus specification for complete details on each bit. note: for the writable bits, software must write a 1 to cl ear bits that are set. writing a 0 to the bit has no effect. bit description 15 detected parity error (dpe) ? ro. not implemented. hardwired to 0. 14 signaled system error (sse) ?ro. not implemented. hardwired to 0. 13 master abort status (mas) ? r/wc. 0 = master abort not generated by bus master ac ?97 function. 1 = bus master ac ?97 interface function, as a master, generates a master abort. 12 reserved. read as 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. this 2-bit field reflects the ich6's devsel# timing parameter. these read only bits indicate the ich6's devsel# timing when performing a positive decode. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. hardwir ed to 1. this bit indicates that the ich6 as a target is capable of fast back-to-back transactions. 6 user definable features (udf) ? ro . not implemented. hardwired to 0. 5 66 mhz capable (66mhz_cap) ? ro. hardwired to 0. 4 capabilities list (cap_list) ? ro. indicates that th e controller contains a ca pabilities pointer list. the first item is pointed to by l ooking at configuration offset 34h. 3 interrupt status (ints) ? ro. 0 = this bit is 0 after the interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. 2:0 reserved
610 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.1.5 rid?revision identifi cation register (modem?d30:f3) address offset: 08h attribute: ro default value: see bit description size: 8 bits lockable: no power well: core 17.1.6 pi?programming interf ace register (modem?d30:f3) address offset: 09h attribute: ro default value: 00h size: 8 bits lockable: no power well: core 17.1.7 scc?sub class code register (modem?d30:f3) address offset: 0ah attribute: ro default value: 03h size: 8 bits lockable: no power well: core 17.1.8 bcc?base class code register (modem?d30:f3) address offset: 0bh attribute: ro default value: 07h size: 8 bits lockable: no power well: core bit description 7:0 revision id ? ro. refer to the intel ? i/o controller hub 6 (ich6) family specification update for the value of the revision id register bit description 7:0 programming interface ? ro. bit description 7:0 sub class code ? ro. 03h = generic modem. bit description 7:0 base class code ? ro. 07h = simple communications controller.
intel ? i/o controller hub 6 (ich6) family datasheet 611 ac ?97 modem controller registers (d30:f3) 17.1.9 headtyp?header type register (m odem?d30:f3) address offset: 0eh attribute: ro default value: 00h size: 8 bits lockable: no power well: core 17.1.10 mmbar?modem mixer base address register (modem?d30:f3) address offset: 10 ? 13h attribute: r/w, ro default value: 00000001h size: 32 bits the native pci mode modem uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the modem mixe r software interface. the mixer requires 256 bytes of i/o space. all accesses to the mixer registers ar e forwarded over the ac- link to the codec where the registers reside. in the case of the split codec im plementation accesses to the differ ent codecs are differentiated by the controller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. bit description 7:0 header type ? ro. bit description 31:16 hardwired to 0?s. 15:8 base address ? r/w. these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a devi ce actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to 0, while bits 15:8 are programmable. this conf iguration yields a maxi mum i/o block size of 256 bytes for this base address. 7:1 reserved. read as 0 0 resource type indicator (rte) ? ro. hardwired to 1indicating a request for i/o space.
612 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.1.11 mbar?modem base addr ess register (modem?d30:f3) address offset: 14 ? 17h attribute: r/w, ro default value: 00000001h size: 32 bits the modem function uses pci base address register #1 to request a contiguous block of i/o space that is to be used for the modem software in terface. the modem bus mastering register space requires 128 bytes of i/o space. a ll modem registers reside in the controller, therefore cycles are not forwarded over the ac -link to the codec. 17.1.12 svid?subsystem vendor identification register (modem?d30:f3) address offset: 2c ? 2dh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the svid register, in combination with the subsystem id register, enable the operating environment to distinguish one audio subsystem from the other(s). this regi ster is implemented as write-once register. once a value is written to it, the value can be read b ack. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. bit description 31:16 hardwired to 0?s. 15:7 base address ? r/w. these bits are used in the i/o space decode of the modem interface registers. the number of upper bits that a devic e actually implements depends on how much of the address space the device will respond to. for the ac ?97 modem, the upper 16 bits are hardwired to 0, while bits 15:7 are programmable. this conf iguration yields a maxi mum i/o block size of 128 bytes for this base address. 6:1 reserved. read as 0 0 resource type indicator (rte) ? ro. hardwired to 1 indicating a request for i/o space. bit description 15:0 subsystem vendor id ? r/wo.
intel ? i/o controller hub 6 (ich6) family datasheet 613 ac ?97 modem controller registers (d30:f3) 17.1.13 sid?subsystem identifica tion register (modem?d30:f3) address offset: 2e ? 2fh attribute: r/wo default value: 0000h size: 16 bits lockable: no power well: core the sid register, in combination with the subsystem vendor id register make it possible for the operating environment to distinguish one audio subsystem from another. this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 17.1.14 cap_ptr?capabilities poin ter register (modem?d30:f3) address offset: 34h attribute: ro default value: 50h size: 8 bits lockable: no power well: core this register indicates the of fset for the capability pointer. 17.1.15 int_ln?interrupt li ne register (modem?d30:f3) address offset: 3ch attribute: r/w default value: 00h size: 8 bits lockable: no power well: core this register indicates which pci interrupt li ne is used for the ac ?97 module interrupt. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro . this field indicates that the fi rst capability pointer offset is offset 50h bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich6. it is used to communicate to software the interrupt line that the interrupt pin is connected to.
614 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.1.16 int_pin?interrupt pin register (modem?d30:f3) address offset: 3dh attribute: ro default value: see description size: 8 bits lockable: no power well: core this register indicates which pci interrupt pin is used for the ac ?97 modem interrupt. the ac ?97 interrupt is internally or?d to the interrupt controller with the pirqb# signal. 17.1.17 pid?pci power manageme nt capability identification register (modem?d30:f3) address offset: 50h attribute: ro default value: 0001h size: 16 bits lockable: no power well: core 17.1.18 pc?power management capabilities register (modem?d30:f3) address offset: 52h attribute: ro default value: c9c2h size: 16 bits lockable: no power well: core bit description 7:3 reserved 2:0 interrupt pin (int_pn) ? ro. this reflects the va lue of d30ip.amip in chip set configuration space. bit description 15:8 next capability (next) ? ro. th is field indicates that this is the last item in the list. 7:0 capability id (cap) ? ro. this field indicates that this pointer is a me ssage signaled interrupt capability. bit description 15:11 pme support ? ro. this fi eld indicates pme# can be generated from all d states. 10:9 reserved. 8:6 auxiliary current ? ro. this field reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi ) ? ro. this bit indicates that no device-specific initialization is required. 4 reserved ? ro. 3 pme clock (pmec) ? ro. this bit indicates t hat pci clock is not required to generate pme#. 2:0 version (vs) ? ro. this field indicates sup port for revision 1.1 of the pci power management specification.
intel ? i/o controller hub 6 (ich6) family datasheet 615 ac ?97 modem controller registers (d30:f3) 17.1.19 pcs?power management control and status register (modem?d30:f3) address offset: 54h attribute: r/w, r/wc default value: 0000h size: 16 bits lockable: no power well: resume this register is not affected by the d3 hot to d0 transition. bit description 15 pme status (pmes) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit is set when the ac ?97 controller w ould normally assert the pme# signal independent of the state of the pme_en bit. this bit resides in the resume well. 14:9 reserved ? ro. 8 pme enable (pmee) ? r/w. 0 = disable. 1 = enable. when set, and if corresponding pmes is also set, the ac '97 controller sets the ac97_sts bit in the gpe0_sts register 7:2 reserved ? ro. 1:0 power state (ps) ? r/w. this field is used both to determ ine the current power state of the ac ?97 controller and to set a new power state. the values are: 00 = d0 state 01 = not supported 10 = not supported 11 = d3 hot state when in the d3 hot state, the ac ?97 controller?s configur ation space is available, but the i/o and memory spaces are not. additi onally, interrupts are blocked. if software attempts to write a value of 10b or 01b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs.
616 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.2 ac ?97 modem i/o space (d30:f3) in the case of the split codec implementation accesses to the mode m mixer registers in different codecs are differentiated by the c ontroller by using address offsets 00h ? 7fh for the primary codec and address offsets 80h ? feh for the secondary codec. table 17-2 shows the register addresses for the modem mixer registers. notes: 1. registers in italics are for fu nctions not supported by the ich6 2. software should not try to access reserved registers 3. the ich6 supports a modem codec connected to acz_ sdin[2:0], as long as the codec id is 00 or 01. however, the ich6 does not support more than one m odem codec. for a complete list of topologies, see your ich6 enabled platform design guide. the global control (glob_cnt) and global status (glob_sta) registers are aliased to the same global registers in the audi o and modem i/o space. therefore a r ead/write to these registers in either audio or modem i/o space affects the sa me physical register. software could access these registers as bytes, word, dword quantities, but reads must not cross dword boundaries. table 17-2. intel ? ich6 modem mixer register configuration register mmbar exposed registers (d30:f3) primary secondary name 00h:38h 80h:b8h intel reserved 3ch bch extended modem id 3eh beh extended modem stat/ctrl 40h c0h line 1 dac/adc rate 42h c2h line 2 dac/adc rate 44h c4h handset dac/adc rate 46h c6h line 1 dac/adc level mute 48h c8h line 2 dac/adc level mute 4ah cah handset dac/adc level mute 4ch cch gpio pin config 4eh ceh gpio polarity/type 50h d0h gpio pin sticky 52h d2h gpio pin wake up 54h d4h gpio pin status 56h d6h misc. modem afe stat/ctrl 58h d8h ac ?97 reserved 5ah dah vendor reserved 7ch fch vendor id1 7eh feh vendor id2
intel ? i/o controller hub 6 (ich6) family datasheet 617 ac ?97 modem controller registers (d30:f3) these registers exist in i/o space and reside in th e ac ?97 controller. the two channels, modem in and modem out, each have their own set of bus mastering registers. th e following register descriptions apply to both channels. the na ming prefix convention used is as follows: mi = modem in channel mo = modem out channel note: 1. mi = modem in channel; mo = modem out channel note: internal reset as a result of d3 hot to d0 transition will reset all the core well registers except the registers shared with the ac ?97 audio controll er (gcr, gsr, casr). a ll resume well registers will not be reset by the d3 hot to d0 transition. core well registers and bits not reset by the d3 hot to d0 transition: ? offset 3ch ? 3fh ? bits [6:0] global control (glob_cnt) ? offset 40h ? 43h ? bits [29,15,11:10] global status (glob_sta) ? offset 44h ? codec access semaphore register (cas) resume well registers and bits will not be reset by the d3 hot to d0 transition: ? offset 40h ? 43h ? bits [17:16] global status (glob_sta) table 17-3. modem registers offset mnemonic name default access 00h?03h mi_bdbar modem in buffer descriptor list base address 00000000h r/w 04h mi_civ modem in current index value 00h ro 05h mi_lvi modem in last valid index 00h r/w 06h?07h mi_sr modem in status 0001h r/wc, ro 08h?09h mi_picb modem in position in current buffer 0000h ro 0ah mi_piv modem in prefetch index value 00h ro 0bh mi_cr modem in control 00h r/w, r/w (special) 10h?13h mo_bdbar modem out buffer descriptor list base address 00000000h r/w 14h mo_civ modem out current index value 00h ro 15h mo_lvi modem out last valid 00h r/w 16h?17h mo_sr modem out status 0001h r/wc, ro 18h?19h mi_picb modem in position in current buffer 0000h ro 1ah mo_piv modem out prefetched index 00h ro 1bh mo_cr modem out control 00h r/w, r/w (special) 3ch?3fh glob_cnt global control 00000000h r/w, r/w (special) 40h?43h glob_sta global status 00300000h ro, r/w, r/wc 44h cas codec access semaphore 00h r/w (special)
618 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.2.1 x _bdbar?buffer descriptor li st base address register (modem?d30:f3) i/o address: mbar + 00h (mibdbar), attribute: r/w mbar + 10h (mobdbar) default value: 00000000h size: 32bits lockable: no power well: core software can read the register at offset 00h by pe rforming a single, 32-bit r ead from address offset 00h. reads across dword boundaries are not supported. 17.2.2 x _civ?current index value register (modem?d30:f3) i/o address: mbar + 04h (miciv), attribute: ro mbar + 14h (mociv), default value: 00h size: 8bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 04h. reads across dword boundaries are not supported. 17.2.3 x _lvi?last valid index register (modem?d30:f3) i/o address: mbar + 05h (milvi), attribute: r/w mbar + 15h (molvi) default value: 00h power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 8-bit read to offset 05h. reads across dword boundaries are not supported. bit description 31:3 buffer descriptor list base address [31:3] ? r/w. these bits represent address bits 31:3. the entries should be aligned on 8-byte boundaries. 2:0 hardwired to 0. bit description 7:5 hardwired to 0. 4:0 current index value [4:0] ? ro. these bits represent which buffer descriptor within the list of 16 descriptors is being processed currently. as eac h descriptor is processed, this value is incremented. bit description 7:5 hardwired to 0 4:0 last valid index [4:0] ? r/w. these bits indicate the last vali d descriptor in the list. this value is updated by the software as it prepares new buffers and adds to the list.
intel ? i/o controller hub 6 (ich6) family datasheet 619 ac ?97 modem controller registers (d30:f3) 17.2.4 x _sr?status register (modem?d30:f3) i/o address: mbar + 06h (mi sr), attribute: r/wc, ro mbar + 16h (mosr) default value: 0001h size: 16 bits lockable: no power well: core software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single, 32-bit read from address offset 04h. software can also read this register individually by doing a single, 16-bit read to offset 06h. reads across dword boundaries are not supported. bit description 15:5 reserved 4 fifo error (fifoe) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = fifo error occurs. modem in: fifo error indicates a fifo overrun. the fifo pointers don't increment, the incoming data is not written into the fifo, thereby being lost. modem out: fifo error indicates a fifo underrun. the sample transmitted in this case should be the last valid sample. the ich6 will set the fifoe bit if the under-run or overrun occurs when there are more valid buffers to process. 3 buffer completion interrupt status (bcis) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion (ioc) bit is set in the command byte of the buffer descriptor. remains active until software clears bit. 2 last valid buffer completion interrupt (lvbci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = set by hardware when last valid buffer has b een processed. it remains active until cleared by software. this bit indicates the occurrence of t he event signified by the last valid buffer being processed. thus, this is an event status bit that can be cleared by software once this event has been recognized. this event will cause an interrupt if the enable bit in the control register is set. the interrupt is cleared when the software clears this bit. in the case of transmits (pcm out, modem out) this bit is set, after the last valid buffer has been fetched (not after transmitting it). while in the case of receives, this bit is set after the data for the last buffer has been written to memory. 1 current equals last valid (celv) ? ro. 0 = hardware clears when controller exists state (i.e., until a new value is written to the lvi register). 1 = current index is equal to the value in the las t valid index register, and the buffer pointed to by the civ has been processed (i.e., after the last valid buffer has been processed). this bit is very similar to bit 2, except, this bit reflects the state rather t han the event. this bit reflects the state of the controller, and remains set until the controller exits this state. 0 dma controller halted (dch) ? ro. 0 = running. 1 = halted. this could happen because of the start/stop bit being cleared and the dma engines are idle, or it could happen once the controll er has processed the last valid buffer.
620 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.2.5 x _picb?position in curr ent buffer register (modem?d30:f3) i/o address: mbar + 08h (mipicb), attribute: ro mbar + 18h (mopicb), default value: 0000h size: 16 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read th is register individually by doing a single, 16-bit read to offset 08h. reads across dword boundaries are not supported. 17.2.6 x _piv?prefetch ind ex value register (modem?d30:f3) i/o address: mbar + 0ah (mipiv), attribute: ro mbar + 1ah (mopiv) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. soft ware can also read this register indi vidually by doing a single, 8-bit read to offset 0ah. reads across dword boundaries are not supported. bit description 15:0 position in current buffer[15:0] ? ro. these bits represent the number of samples left to be processed in the current buffer. bit description 7:5 hardwired to 0 4:0 prefetched index value [4:0] ? ro. these bits represent which buffer descriptor in the list has been prefetched.
intel ? i/o controller hub 6 (ich6) family datasheet 621 ac ?97 modem controller registers (d30:f3) 17.2.7 x _cr?control register (modem?d30:f3) i/o address: mbar + 0bh (micr), attribute: r/w, r/w (special) mbar + 1bh (mocr) default value: 00h size: 8 bits lockable: no power well: core software can read the registers at the offsets 08h, 0ah, and 0bh by performing a 32-bit read from the address offset 08h. software can also read this register individually by doing a single, 8-bit read to offset 0bh. reads across dword boundaries are not supported. bit description 7:5 reserved 4 interrupt on completion enable (ioce) ? r/w. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. 0 = disable 1 = enable 3 fifo error interrupt enable (feie) ? r/w. this bit controls whether the occurrence of a fifo error will cause an interrupt or not. 0 = disable. bit 4 in the status register wi ll be set, but the interrupt will not occur. 1 = enable. interrupt will occur 2 last valid buffer interrupt enable (lvbie) ? r/w. this bit controls whether the completion of the last valid buffer will cause an interrupt or not. 0 = disable. bit 2 in the status register will still be set, but the interrupt will not occur. 1 = enable 1 reset registers (rr) ? r/w (special). 0 = removes reset condition. 1 = contents of all registers to be reset, except the in terrupt enable bits (bit 4,3,2 of this register). software needs to set this bit. it must be set only when the run/pause bit is cleared. setting it when the run bit is set will cause undefined cons equences. this bit is se lf-clearing (software needs not clear it). 0 run/pause bus master (rpbm) ? r/w. 0 = pause bus master operation. this results in all state information being retained (i.e., master mode operation can be stopped and then resumed). 1 = run. bus master operation starts.
622 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) 17.2.8 glob_cnt?global contro l register (modem?d30:f3) i/o address: mbar + 3ch att ribute: r/w, r/w (special) default value: 00000000h size: 32 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 31:6 reserved. 6 acz_sdin2 interrupt enable (s2re) ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on the acz_sdin2 causes a resume event on the ac-link. 5 acz_sdin1 resume interrupt enable (s1re) ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on the acz_sdin1 causes a resume event on the ac-link. 4 acz_sdin0 resume interrupt enable (s0re) ? r/w. 0 = disable. 1 = enable an interrupt to occur when the codec on acz_sdin0 causes a resume event on the ac-link. 3 ac-link shut off (lso) ? r/w. 0 = normal operation. 1 = controller disables all outputs which will be pulled low by internal pull down resistors. 2 ac ?97 warm reset ? r/w (special). 0 = normal operation. 1 = writing a 1 to this bit causes a warm reset to occur on the ac-link. the warm reset will awaken a suspended codec without clearing its internal r egisters. if software attempts to perform a warm reset while bit_clk is running, the write will be ignored and the bit will not change. this bit is self-clearing (it remains set until the reset co mpletes and bit_clk is seen on the ac-link, after which it clears itself). 1 ac ?97 cold reset# ? r/w. 0 = writing a 0 to this bit causes a cold reset to occur throughout the ac ?97 circuitry. all data in the controller and the codec will be lost. soft ware needs to clear this bit no sooner than the minimum number of ms have elapsed. 1 = this bit defaults to 0 and hence after reset, the driv er needs to set this bit to a 1. the value of this bit is retained after suspends; hence, if this bi t is set to a 1 prior to suspending, a cold reset is not generated automat ically upon resuming. note: this bit is in the core well. 0 gpi interrupt enable (gie) ? r/w. this bit controls whether the change in status of any gpi causes an interrupt. 0 = bit 0 of the global status register is set, but no interrupt is generated. 1 = the change on value of a gpi causes an interrupt and sets bit 0 of the global status register. note: this bit is cleared by t he ac ?97 modem function d3 hot to d0 reset.
intel ? i/o controller hub 6 (ich6) family datasheet 623 ac ?97 modem controller registers (d30:f3) 17.2.9 glob_sta?global stat us register (modem?d30:f3) i/o address: mbar + 40h a ttribute: ro, r/w, r/wc default value: 00300000h size: 32 bits lockable: no power well: core bit description 31:30 reserved. 29 acz_sdin2 resume interrupt (s2ri) ? r/wc. this bit indicates a resume event occurred on acz_sdin2. 0 = software clears this bit by writing a 1 to it. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 28 acz_sdin2 codec ready (s2cr) ? ro. this bit reflects the state of the codec ready bit on acz_sdin2. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the codec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 27 bit clock stopped (bcs) ? ro. this bit indicates that the bit clock is not running. 0 = transition is found on bit_clk. 1 = intel ? ich6 detects that there has been no transit ion on bit_clk for four consecutive pci clocks. 26 s/pdif* interrupt (spint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = s/pdif out channel interrupt status bits have been set. 25 pcm in 2 interrupt (p2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in 2 channel status bits have been set. 24 microphone 2 in interrupt (m2int) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel interrupts status bits has been set. 23:22 sample capabilities ? ro. this field indicates the capability to support more greater than 16-bit audio. 00 = reserved 01 = 16 and 20-bit audio supported (ich6 value) 10 = reserved 11 = reserved 21:20 multichannel capabilities ? ro. this field indicates the cap ability to support 4 and 6 channels on pcm out. 19:18 reserved. 17 md3 ? r/w. power down semaphore for modem. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the ad3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. 16 ad3 ? r/w. power down semaphore for audio. this bit exists in the suspend well and maintains context across power states (except g3). the bit has no hardware function. it is used by software in conjunction with the md3 bit to coordinate the entry of the two codecs into d3 state. this bit is not affected by d3 hot to d0 reset. 15 read completion status (rcs) ? r/wc. this bit indicates the status of codec read completions. software clears this bit by writing a 1 to it. 0 = a codec read completes normally. 1 = a codec read results in a time-out. this bit is not affected by d3 hot to d0 reset.
624 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3) note: on reads from a codec, the controller will give the codec a maximum of four frames to respond, after which if no re sponse is received, it will return a dummy read completio n to the processor (with all f?s on the data) and also set the read completion status bi t in the global status register. note: reads across dword boundaries are not supported. 14 bit 3 of slot 12 ? ro. display bit 3 of the most recent slot 12. 13 bit 2 of slot 12 ? ro. display bit 2 of the most recent slot 12. 12 bit 1 of slot 12 ? ro. display bit 1 of the most recent slot 12. 11 acz_sdin1 resume interrupt (s1ri) ? r/wc. this bit indicates that a resume event occurred on acz_sdin1. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 10 acz_sdin0 resume interrupt (s0ri) ? r/wc. this bit indicates that a resume event occurred on acz_sdin0. software clears this bit by writing a 1 to it. 0 = resume event did not occur. 1 = resume event occurred. this bit is not affected by d3 hot to d0 reset. 9 acz_sdin1 codec ready (s1cr) ? ro. this bit reflects the state of the codec ready bit in acz_sdin1. bus masters ignore the condition of the codec ready bits, so software must check this bit before starting the bus masters. once the c odec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 8 acz_sdin0 codec ready (s0cr) ? ro. this bit reflects the state of the codec ready bit in acz_sdin 0. bus masters ignore the condition of t he codec ready bits, so so ftware must check this bit before starting the bus masters. once the c odec is ?ready?, it must never go ?not ready? spontaneously. 0 = not ready. 1 = ready. 7 microphone in interrupt (mint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the mic in channel inte rrupts status bits has been set. 6 pcm out interrupt (point) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm out channel interrupts status bits has been set. 5 pcm in interrupt (piint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the pcm in channel interrupts status bits has been set. 4:3 reserved 2 modem out interrupt (moint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem out channel interrupts status bits has been set. 1 modem in interrupt (miint) ? ro. 0 = when the specific status bit is cleared, this bit will be cleared. 1 = one of the modem in channel interrupts status bits has been set. 0 gpi status change interrupt (gsci) ? r/wc. 0 = software clears this bit by writing a 1 to it. 1 = this bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. this indicates that one of the gpi?s changed state, and that th e new values are available in slot 12. this bit is not affected by ac ?97 audio modem function d3 hot to d0 reset. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 625 ac ?97 modem controller registers (d30:f3) 17.2.10 cas?codec access semaphore register (modem?d30:f3) i/o address: nabmbar + 44h attribute: r/w (special) default value: 00h size: 8 bits lockable: no power well: core note: reads across dword boundaries are not supported. bit description 7:1 reserved 0 codec access semaphore (cas) ? r/w (special). this bit is read by software to check whether a codec access is currently in progress. 0 = no access in progress. 1 = the act of reading this register sets this bit to 1. the driver that read this bit can then perform an i/o access. once the access is complet ed, hardware automatically clears this bit.
626 intel ? i/o controller hub 6 (i ch6) family datasheet ac ?97 modem controller registers (d30:f3)
intel ? i/o controller hub 6 (ich6) family datasheet 627 intel ? high definition audio cont roller registers (d27:f0) 18 intel ? high definition audio controller registers (d27:f0) the intel high definition audio controller resides in pci device 27, function 0 on bus 0. this function contains a set of dma engines that are used to move samples of digitally encoded data between system memory and external codecs. note: all registers in this function (including memory-m apped registers) must be addressable in byte, word, and d-word quantities. the software must always make register accesses on natural boundaries (i.e. d-word accesses must be on d-word boundaries; word accesses on word boundaries, etc.) in addition, th e memory-mapped register space must not be accessed with the lock semantic exclusive-access m echanism. if software attempts exclusive-access mechanisms to the intel high definition audio me mory-mapped space, the results are undefined. note: users interested in providing feedback on the intel high definition audio specification or planning to implement the intel high definition audio specification into a future product will need to execute the intel high definition audio specification de veloper?s agreement. for more information, contact nextgenaudio@intel.com. 18.1 intel ? high definition audio pci configuration space (intel ? high definition audio? d27:f0) note: address locations that are not shown should be treated as reserved. table 18-1. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 1 of 2) offset mnemonic register name default access 00?01h vid vendor identification 8086h ro 02?03h did device identification 2668h ro 04?05h pcicmd pci command 0000h r/w, ro 06?07h pcists pci status 0010h r/wc, ro 08h rid revision identification see register description. ro 09h pi programming interface 00h ro 0ah scc sub class code 03h ro 0bh bcc base class code 04h ro 0ch cls cache line size 00h r/w 0dh lt latency timer 00h ro 0eh headtyp header type 00h ro 10?13h hdbarl intel high definition audio lower base address (memory) 00000004h r/w, ro
628 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 14?17h hdbaru intel high definition audio upper base address (memory) 00000000h r/w 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h capptr capability list pointer 50h ro 3ch intln interrupt line 00h r/w 3dh intpn interrupt pin see register description ro 40h hdctl intel high definition audio control 00h r/w, ro 44h tcsel traffic class select 00h r/w 50?51h pid pci power management capability id 6001h ro 52?53h pc power management capabilities c842 ro 54?57h pcs power management control and status 00000000h r/w, ro, r/wc 60?61h mid msi capability id 7005h ro 62?63h mmc msi message control 0080h r/w, ro 64?67h mmla msi message lower address 00000000h r/w, ro 68?6bh mmua smi message upper address 00000000h r/w 6c?6dh mmd msi message data 0000h r/w 70?71h pxid pci express* capability identifiers 0010h ro 72?73h pxc pci express capabilities 0091h ro 74?77h devcap device cap abilities 00000000h ro, r/wo 78?79h devc device control 0800h r/w, ro 7a?7bh devs device status 0010h ro 100?103h vccap virtual channel enhanced capability header 13010002h ro 104?107h pvccap1 port vc capability register 1 00000001h ro 108?10bh pvccap2 port vc capability register 2 00000000h ro 10c?10d pvcctl port vc control 0000h ro 10e?10fh pvcsts port vc status 0000h ro 110?103h vc0cap vc0 resource capability 00000000h ro 114?117h vc0ctl vc0 resource control 800000ffh r/w, ro 11a?11bh vc0sts vc0 resource status 0000h ro 11c?11fh vcicap vci resource capability 00000000h ro 120?123h vcictl vci resource control 00000000h r/w, ro 126?127h vcists vci resource status 0000h ro 130?133h rccap root complex link declaration enhanced capability header 00010005h ro 134?137h esd element self description 05000100h ro 140?143h l1desc link 1 description 00000001h ro 148?14bh l1addl link 1 lower address see register description ro 14c?14fh l1addu link 1 upper address see register description ro table 18-1. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 2 of 2) offset mnemonic register name default access
intel ? i/o controller hub 6 (ich6) family datasheet 629 intel ? high definition audio cont roller registers (d27:f0) 18.1.1 vid?vendor identification register (intel ? high definition audio controller?d27:f0) offset: 00-01h attribute: ro default value: 8086h size: 16 bits 18.1.2 did?device iden tification register (intel ? high definition audio controller?d27:f0) offset address: 02 ? 03h attribute: ro default value: 2668h size: 16 bits 18.1.3 pcicmd?pci command register (intel ? high definition audio controller?d27:f0) offset address: 04 ? 05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel. intel vid = 8086h bit description 15:0 device id ? ro. this is a 16-bit value assigned to the ich6 intel high definition audio controller. bit description 15:11 reserved 10 interrupt disable (id) ? r/w. 0= the intx# signals may be asserted. 1= the intel high definition audio controller?s intx# signal will be de-asserted note that this bit does not affect the generation of msi?s. 9 fast back to back enable (fbe) ? ro. not implemented. hardwired to 0. 8 serr# enable (serr_en) ? ro. not implemented. hardwired to 0. 7 wait cycle control (wcc) ? ro. not implemented. hardwired to 0. 6 parity error response (per) ? ro. not implemented. hardwired to 0. 5 vga palette snoop (vps). not implemented. hardwired to 0. 4 memory write and invalidate enable (mwie) ? ro. not implemented. hardwired to 0. 3 special cycle enable (sce). not implemented. hardwired to 0. 2 bus master enable (bme) ? r/w. this bit controls standard pci express* bus mastering capabilities for memory and i/o, r eads and writes. note that this bit also controls msi generation since msis are essentially memory writes. 0 = disable 1 = enable 1 memory space enable (mse) ? r/w. this bit enables memory space addresses to the intel high definition a udio controller. 0 = disable 1 = enable 0 i/o space enable (iose)?ro. hardwired to 0 since the intel high definition audio controller does not implement i/o space.
630 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.4 pcists?pci status register (intel ? high definition audi o controller?d27:f0) offset address: 06 ? 07h attribute: ro, r/wc default value: 0010h size: 16 bits 18.1.5 rid?revision id entification register (intel ? high definition audi o controller?d27:f0) offset: 08h attribute: ro default value: see bit description size: 8 bits bit description 15 detected parity error (dpe) ? ro. not implemented. hardwired to 0. 14 serr# status (serrs) ? ro. not implemented. hardwired to 0. 13 received master abort (rma) ? r/wc. software clears this bit by writing a 1 to it. 0 = no master abort received. 1 = the intel high definition audio controller sets this bit when, as a bus master, it receives a master abort. when set, the intel high definition audio controller clears the run bit for the channel that received the abort. 12 received target abort (rta) ? ro. not implemented. hardwired to 0. 11 signaled target abort (sta) ? ro. not implemented. hardwired to 0. 10:9 devsel# timing status (dev_sts) ? ro. does not apply. hardwired to 0. 8 data parity error detected (dped) ? ro. not implemented. hardwired to 0. 7 fast back to back capable (fb2bc) ? ro. does not apply. hardwired to 0. 6 reserved. 5 66 mhz capable (66mhz_cap) ? ro. does not apply. hardwired to 0. 4 capabilities list (cap_list) ? ro. hardwired to 1. indicates t hat the controller contains a capabilities pointer list. the fi rst item is pointed to by look ing at configuration offset 34h. 3 interrupt status (is) ? ro. 0 = this bit is 0 after the interrupt is cleared. 1 = this bit is 1 when the intx# is asserted. note that this bit is not set by an msi. 2:0 reserved. bit description 7:0 revision id ? ro. refer to the intel ? ich6 family datasheet specification update for the value of the revision id register
intel ? i/o controller hub 6 (ich6) family datasheet 631 intel ? high definition audio cont roller registers (d27:f0) 18.1.6 pi?programming interface register (intel ? high definition audio controller?d27:f0) offset: 09h attribute: ro default value: 00h size: 8 bits 18.1.7 scc?sub class code register (intel ? high definition audio controller?d27:f0) address offset: 0ah attribute: ro default value: 03h size: 8 bits 18.1.8 bcc?base class code register (intel ? high definition audio controller?d27:f0) address offset: 0bh attribute: ro default value: 04h size: 8 bits 18.1.9 cls?cache line size register (intel ? high definition audio controller?d27:f0) address offset: 0ch attribute: r/w default value: 00h size: 8 bits bit description 7:0 programming interface ? ro. bit description 7:0 sub class code (scc) ? ro. 03h = audio device bit description 7:0 base class code (bcc) ? ro. 04h = multimedia device bit description 7:0 cache line size ? r/w. implemented as r/w r egister, but has no functional impact to the ich6
632 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.10 lt?latency timer register (intel ? high definition audi o controller?d27:f0) address offset: 0dh attribute: ro default value: 00h size: 8 bits 18.1.11 headtyp?header type register (intel ? high definition audi o controller?d27:f0) address offset: 0eh attribute: ro default value: 00h size: 8 bits 18.1.12 hdbarl?intel ? high definition audio lower base address register (intel ? high definition audi o controller?d27:f0) address offset: 10h attribute: r/w, ro default value: 00000004h size: 32 bits 18.1.13 hdbaru?intel ? high definition audio upper base address register (intel ? high definition audi o controller?d27:f0) address offset: 14h attribute: r/w default value: 00000000h size: 32 bits bit description 7:0 latency timer ? ro. hardwired to 00 bit description 7:0 header type ? ro. hardwired to 00. bit description 31:14 lower base address (lba) ? r/w. base address for the intel high definition audi o controller?s memory mapped configuration registers. 16 kb are requested by hardwiring bits 13:4 to 0s. 13:4 ro. hardwired to 0s 3 prefetchable (pref) ? ro. hardwired to 0 to indicate that this bar is not prefetchable 2:1 address range (addrng) ? ro. hardwired to 10b, indicating that this bar can be located anywhere in 64-bit address space. 0 space type (sptyp) ? ro. hardwired to 0. indi cates this bar is located in memory space. bit description 31:0 upper base address (uba) ? r/w. upper 32 bits of the base address for the intel high definition audio controller?s memory mapped configuration registers.
intel ? i/o controller hub 6 (ich6) family datasheet 633 intel ? high definition audio cont roller registers (d27:f0) 18.1.14 svid?subsystem vendor identification register (intel ? high definition audio controller?d27:f0) address offset: 2c?2dh attribute: r/wo default value: 0000h size: 16 bits the svid register, in combination with the subsystem id register (d27:f0:2eh), enable the operating environment to distinguish on e audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. 18.1.15 sid?subsystem iden tification register (intel ? high definition audio controller?d27:f0) address offset: 2e ? 2fh attribute: r/wo default value: 0000h size: 16 bits the sid register, in combination with the subsystem vendor id register (d27:f0:2ch) make it possible for the operating environment to distinguish one audio subsystem from the other(s). this register is implemented as write-once register. once a value is written to it, the value can be read back. any subsequent writes will have no effect. this register is not affected by the d3 hot to d0 transition. t 18.1.16 capptr?capabilities po inter register (audio?d30:f2) address offset: 34h attribute: ro default value: 50h size: 8 bits this register indicates the of fset for the capability pointer. bit description 15:0 subsystem vendor id ? r/wo. bit description 15:0 subsystem id ? r/wo. bit description 7:0 capabilities pointer (cap_ptr) ? ro . this field indicates that the fi rst capability pointer offset is offset 50h (power management capability)
634 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.17 intln?interrupt line register (intel ? high definition audi o controller?d27:f0) address offset: 3ch attribute: r/w default value: 00h size: 8 bits 18.1.18 intpn?interrupt pin register (intel ? high definition audi o controller?d27:f0) address offset: 3dh attribute: ro default value: see description size: 8 bits bit description 7:0 interrupt line (int_ln) ? r/w. this data is not used by the intel ? ich6. it is used to communicate to software the interrupt line that the interrupt pin is connected to. bit description 7:4 reserved. 3:0 interrupt pin ? ro. this field reflects the value of d27ip.zip (chipset configuration registers:offset 3110h:bits 3:0).
intel ? i/o controller hub 6 (ich6) family datasheet 635 intel ? high definition audio cont roller registers (d27:f0) 18.1.19 hdctl?intel ? high definition au dio control register (intel ? high definition audio controller?d27:f0) address offset: 40h attribute: r/w, ro default value: 00h size: 8 bits bit description 7:4 reserved. 3 bitclk detect clear (clkdetclr) ? r/w. 0 = when a 0 is written to this bit, the clock detect circuit is operational and maybe enabled. 1 = writing a 1 to this bit clear s bit 1 (clkdet#) in this register. clkdet# bit remains clear when this bit is set to 1. note: this bit is not affected by the d3 hot to d0 transition. 2 bitclk detect enable (clkdeten) ? r/w. 0 = latches the current state of bit 1 (clkdet#) in this register 1 = enables the clock detection circuit note: this bit is not affected by the d3 hot to d0 transition. 1 bitclk detected inverted (clkdet#) ? ro . this bit is modified by hardware. it is set to 0 when the intel ? ich6 detects that the bitclk is toggling, indicating the presence of an ac ?97 codec on the link. notes: 1. bit 2 (clkdeten) and bit 3 (clkdetclr) in this register control the operation of this bit and must be manipulated correctly in order to get a valid clkdet# indicator. 2. this bit is not affected by the d3 hot to d0 transition. 0 intel high definition audio/ac ?97 signal mode ? r/w. this bit selects the shared intel high definition audio/ac ?97 signals. 0 = ac ?97 mode is selected (default) 1 = intel high definition audio mode is selected notes: 1. this bit has no affect on the visibility of the intel high definition audio and ac ?97 function configuration space. 2. this bit is in the resume well and only clear on a power-on reset. software must not makes assumptions about the reset state of this bit and must set it appropriately.
636 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.20 tcsel?traffic class select register (intel ? high definition audi o controller?d27:f0) address offset: 44h attribute: r/w default value: 00h size: 8 bits this register assigned the value to be placed in the tc field. corb and rirb data will always be assigned tc0. bit description 7:3 reserved. 2:0 intel high definition audio traffic class assignment (tcsel) ? r/w. this register assigns the value to be placed in the traffi c class field for input data, output data, and buffer descriptor transactions. 000 = tc0 001 = tc1 010 = tc2 011 = tc3 100 = tc4 101 = tc5 110 = tc6 111 = tc7 note: these bits are not reset on d3 hot to d0 transition; however, they are reset by pltrst#.
intel ? i/o controller hub 6 (ich6) family datasheet 637 intel ? high definition audio cont roller registers (d27:f0) 18.1.21 pid?pci power manage ment capability id register (intel ? high definition audio controller?d27:f0) address offset: 50h attribute: ro default value: 6001h size: 16 bits 18.1.22 pc?power management capabilities register (intel ? high definition audio controller?d27:f0) address offset: 52h attribute: ro default value: c842h size: 16 bits bit description 15:8 next capability (next) ? ro. hardwired to 60h. th is field points to the next capability structure (msi) 7:0 cap id (cap) ? ro. hardwired to 01h. this fiel d indicates that this pointer is a pci power management capability. bit description 15:11 pme support ? ro. hardwired to 11001b. this field indicates pme# can be generated from d3 and d0 states. 10 d2 support ? ro. hardwired to 0. this bi t indicates that d2 state is not supported. 9 d1 support ?ro. hardwired to 0. this bit indicates that d1 state is not supported. 8:6 aux current ? ro. hardwired to 001b. reports 55 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. hard wired to 0. indicates that no device specific initialization is required. 4 reserved 3 pme clock (pmec) ? ro. does not apply. hardwired to 0. 2:0 version ? ro. hardwired to 010b. this field indi cates support for version 1.1 of the pci power management specification.
638 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.23 pcs?power management control and status register (intel ? high definition audio controller?d27:f0) address offset: 54h attr ibute: ro, r/w, r/wc default value: 00000000h size: 32 bits 18.1.24 mid?msi capa bility id register (intel ? high definition audi o controller?d27:f0) address offset: 60h attribute: ro default value: 7005h size: 16 bits bit description 31:24 data ? ro. does not apply. hardwired to 0. 23 bus power/clock control enable ? ro. does not apply. hardwired to 0. 22 b2/b3 support ? ro. does not apply. hardwired to 0. 21:16 reserved. 15 pme status (pmes) ? r/wc. 0 = software clears the bit by writing a 1 to it. 1 = this bit is set when the intel high definition audio c ontroller would normally assert the pme# signal independent of the state of the pme_en bit (bit 8 in this register) this bit in the resume well and only cleared on a power-on reset. software must not make assumptions about the reset state of th is bit and must set it appropriately 14:9 reserved 8 pme enable (pmee) ? r/w. 0 = disable 1 = when set and if corresponding pmes also set, the intel high definition audio controller sets the ac97_sts bit in the gpe0_sts register (pm base +28h). the ac97_sts bit is shared by ac ?97 and intel high definition audio functions si nce they are mut ually exclusive. this bit in the resume well and only cleared on a power-on reset. software must not make assumptions about the reset state of th is bit and must set it appropriately 7:2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the intel high definition audio controller and to set a new power state. 00 = d0 state 11 = d3 hot state others = reserved notes: 1. if software attempts to write a value of 01b or 10b in to this field, the write operation must complete normally; however, the data is discarded and no state change occurs. 2. when in the d3 hot states, the intel high definition audio controll er?s configuration space is available, but the i/o and memory space ar e not. additionally, interrupts are blocked. 3. when software changes this value from d3 hot state to the d0 state, an internal warm (soft) reset is generated, and software must re-initialize the function. bit description 15:8 next capability (next) ? ro. hardwired to 70h. po ints to the pci express* capability structure. 7:0 cap id (cap) ? ro. hardwired to 05h. indica tes that this pointer is a msi capability
intel ? i/o controller hub 6 (ich6) family datasheet 639 intel ? high definition audio cont roller registers (d27:f0) 18.1.25 mmc?msi message control register (intel ? high definition audio controller?d27:f0) address offset: 62h attribute: ro, r/w default value: 0080h size: 16 bits 18.1.26 mmla?msi message lower address register (intel ? high definition audio controller?d27:f0) address offset: 64h attribute: ro, r/w default value: 00000000h size: 32 bits 18.1.27 mmua?msi message upper address register (intel ? high definition audio controller?d27:f0) address offset: 68h attribute: r/w default value: 00000000h size: 32 bits 18.1.28 mmd?msi message data register (intel ? high definition audio controller?d27:f0) address offset: 6ch attribute: r/w default value: 0000h size: 16 bits bit description 15:8 reserved 7 64b address capability (64add) ? ro. hardwired to 1. indicates the ability to generate a 64-bit message address 6:4 multiple message enable (mme) ? ro. normally this is a r/w register. however since only 1 message is supported, these bits are hardwired to 000 = 1 message. 3:1 multiple message capable (mmc) ? ro. ha rdwired to 0 indicating request for 1 message. 0 msi enable (me) ? r/w. 0 = an msi may not be generated 1 = an msi will be generated instead of an intx signal. bit description 31:2 message lower address (mla) ? r/w. lower address used for msi message. 1:0 reserved. bit description 31:0 message upper address (mua) ? r/w. upper 32-bits of address used for msi message. bit description 15:0 message data (md) ? r/w. data used for msi message.
640 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.29 pxid?pci express* capability id register (intel ? high definition audi o controller?d27:f0) address offset: 70h attribute: ro default value: 0010h size: 16 bits 18.1.30 pxc?pci express* capabilities register (intel ? high definition audi o controller?d27:f0) address offset: 72h attribute: ro default value: 0091h size: 16 bits bit description 15:8 next capability (next) ? ro. hardwired to 0. this field indicates that this is the last capability structure in the list. 7:0 cap id (cap) ? ro. hardwired to 10h. this field indicates that this point er is a pci express* capability structure bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. hardwired to 0. 8 slot implemented (si) ? ro. hardwired to 0. 7:4 device/port type (dpt) ? ro. hardwired to 1001b. indicates that this is a root complex integrated endpoint device. 3:0 capability version (cv) ? ro. hardwired to 0001b. indicates version #1 pci express capability
intel ? i/o controller hub 6 (ich6) family datasheet 641 intel ? high definition audio cont roller registers (d27:f0) 18.1.31 devcap?device capabilities register (intel ? high definition audio controller?d27:f0) address offset: 74h attribute: ro, r/wo default value: 00000000h size: 32 bits bit description 31:28 reserved 27:26 captured slot power limit scal e (spls) ? ro. hardwired to 0. 25:18 captured slot power limit value (splv) ? ro. hardwired to 0. 17:15 reserved 14 power indicator present ? ro. hardwired to 0. 13 attention indicator present ? ro. hardwired to 0. 12 attention button present ? ro. hardwired to 0. 11:9 endpoint l1 acce ptable latency ? r/wo. 8:6 endpoint l0s acceptable latency ? r/wo. 5 extended tag field support ? ro. hardwired to 0. indicates 5-bit tag field support 4:3 phantom functions supported ? ro. hardwired to 0. this field indicates that phantom functions not supported 2:0 max payload size supported ? ro. hardwired to 0. this field indicates 128-b maximum payload size capability
642 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.32 devc?device control register (intel ? high definition audi o controller?d27:f0) address offset: 78h attribute: r/w, ro default value: 0800h size: 16 bits bit description 15 reserved 14:12 max read request size ? ro. hardwired to 0 enabling 128b maximum read request size. 11 no snoop enable (nsnpen) ? r/w. 0 = the intel high definition audio controller will not se t the no snoop bit. in this case, isochronous transfers will not use vc1 (vci) even if it is enabled since vc1 is never snooped. isochronous transfers will use vc0. 1 = the intel high definition audio controll er is permitted to set the no snoop bit in the requester attributes of a bus master transaction. in th is case, vc0 or vc1 may be used for isochronous transfers. note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. 10 auxiliary power enable ? ro. hardwi red to 0, indicating that intel high definition audio device does not draw aux power 9 phantom function enable ? ro. hardwi red to 0 disabling phantom functions. 8 extended tag field enable ? ro. hardwired to 0 enabling 5-bit tag. 7:5 max payload size ? ro. hardwired to 0 indicating 128b. 4 enable relaxed ordering ? ro. hardwi red to 0 disabling relaxed ordering. 3 unsupported request reporting enable ? ro. not implemented. hardwired to 0. 2 fatal error reporting enable ? ro . not implemented. hardwired to 0. 1 non-fatal error reporting enable ? ro. not implemented. hardwired to 0. 0 correctable error reporting enable ? ro. not implemented. hardwired to 0.
intel ? i/o controller hub 6 (ich6) family datasheet 643 intel ? high definition audio cont roller registers (d27:f0) 18.1.33 devs?device status register (intel ? high definition audio controller?d27:f0) address offset: 7ah attribute: ro default value: 0010h size: 16 bits 18.1.34 vccap?virtual channe l enhanced capability header (intel ? high definition audio controller?d27:f0) address offset: 100h attribute: ro default value: 13010002h size: 32 bits bit description 15:6 reserved 5 transactions pending ? ro. 0 = indicates that completions for all non-posted requests have been received 1 = indicates that intel high definition audio controller has issued non-posted requests which have not been completed. 4 aux power detected ? ro. hardwired to 1 indicating the device is connected to resume power 3 unsupported request detected ? ro. not implemented. hardwired to 0. 2 fatal error detected ? ro. not implemented. hardwired to 0. 1 non-fatal error detected ? ro. not implemented. hardwired to 0. 0 correctable error detected ? ro. not implemented. hardwired to 0. bit description 31:20 next capability offset ? ro. hardwired to 130h. po ints to the next capability header, which is the root complex link declaration enhanced capability header. 19:16 capability version ? ro. hardwired to 1h. 15:0 pci express* extended capabi lity ? ro. hardwired to 0002h.
644 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.35 pvccap1?port vc capability register 1 (intel ? high definition audi o controller?d27:f0) address offset: 104h attribute: ro default value: 00000001h size: 32 bits 18.1.36 pvccap2?port vc capability register 2 (intel ? high definition audi o controller?d27:f0) address offset: 108h attribute: ro default value: 00000000h size: 32 bits 18.1.37 pvcctl?port vc control register (intel ? high definition audi o controller?d27:f0) address offset: 10ch attribute: ro default value: 0000h size: 16 bits bit description 31:12 reserved. 11:10 port arbitration table entry size ? ro. ha rdwired to 0 since this is an endpoint device. 9:8 reference clock ? ro. hardwired to 0 since this is an endpoint device. 7 reserved. 6:4 low priority extended vc count ? ro. hardwired to 0. indicates that only vc0 belongs to the low priority vc group 3 reserved. 2:0 extended vc count ? ro. hardwired to 001b. indi cates that 1 extended vc (in addition to vc0) is supported by the intel high definition audio controller. bit description 31:24 vc arbitration table offset ? ro . hardwired to 0 indicating that a vc arbitration table is not present. 23:8 reserved. 7:0 vc arbitration capability ? ro. hardwired to 0. these bits are not applicable since the intel high definition audio controller reports a 0 in the low priority extended vc count bits in the pvccap1 register. bit description 15:4 reserved. 3:1 vc arbitration select ? ro. hardwired to 0. normal ly these bits are r/w. however, these bits are not applicable since the intel high definition audio controller repor ts a 0 in the low priority extended vc count bits in the pvccap1 register 0 load vc arbitration table ? ro. hardwired to 0 since an arbitration table is not present.
intel ? i/o controller hub 6 (ich6) family datasheet 645 intel ? high definition audio cont roller registers (d27:f0) 18.1.38 pvcsts?port vc status register (intel ? high definition audio controller?d27:f0) address offset: 10eh attribute: ro default value: 0000h size: 16 bits 18.1.39 vc0cap?vc0 resource capability register (intel ? high definition audio controller?d27:f0) address offset: 110h attribute: ro default value: 00000000h size: 32 bits 18.1.40 vc0ctl?vc0 reso urce control register (intel ? high definition audio controller?d27:f0) address offset: 114h attribute: r/w, ro default value: 800000ffh size: 32 bits bit description 15:1 reserved. 0 vc arbitration table status ? ro. hardwired to 0 since an arbitration table is not present. bit description 31:24 port arbitration table offset ? ro. hardwired to 0 since this field is not valid for endpoint devices 23 reserved. 22:16 maximum time slots ? ro. hardwired to 0 sinc e this field is not valid for endpoint devices 15 reject snoop transactions ? ro. hardwired to 0 si nce this field is not va lid for endpoint devices. 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices 13:8 reserved. 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices bit description 31 vc0 enable ? ro. hardwired to 1 for vc0. 30:27 reserved. 26:24 vc0 id ? ro. hardwired to 0 since the first vc is always assigned as vc0 23:20 reserved. 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices 15:8 reserved. 7:0 tc/vc0 map ? r/w, ro. bit 0 is hardwired to 1 since tc0 is always mapped vc0. bits [7:1] are implemented as r/w bits.
646 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.41 vc0sts?vc0 resource status register (intel ? high definition audi o controller?d27:f0) address offset: 11ah attribute: ro default value: 0000h size: 16 bits 18.1.42 vcicap?vci resource capability register (intel ? high definition audi o controller?d27:f0) address offset: 11ch attribute: ro default value: 00000000h size: 32 bits bit description 15:2 reserved. 1 vc0 negotiation pending ? ro. hardwi red to 0 since this bit does not apply to the integrated intel high definition audio device 0 port arbitration table status ? ro. hardwired to 0 since this field is not valid for endpoint devices bit description 31:24 port arbitration table offset ? ro. hardwired to 0 since this field is not valid for endpoint devices. 23 reserved. 22:16 maximum time slots ? ro. hardwired to 0 si nce this field is not valid for endpoint devices 15 reject snoop transactions ? ro. hardwired to 0 since this field is not valid for endpoint devices 14 advanced packet switching ? ro. hardwired to 0 since this field is not valid for endpoint devices 13:8 reserved 7:0 port arbitration capability ? ro. hardwired to 0 since this field is not valid for endpoint devices
intel ? i/o controller hub 6 (ich6) family datasheet 647 intel ? high definition audio cont roller registers (d27:f0) 18.1.43 vcictl?vci reso urce control register (intel ? high definition audio controller?d27:f0) address offset: 120h attribute: r/w, ro default value: 00000000h size: 32 bits 18.1.44 vcists?vci reso urce status register (intel ? high definition audio controller?d27:f0) address offset: 126h attribute: ro default value: 0000h size: 16 bits 18.1.45 rccap?root complex link declaration enhanced capability header register (intel ? high definition audio controller?d27:f0) address offset: 130h attribute: ro default value: 00010005h size: 32 bits bit description 31 vci enable ? r/w. 0 = vci is disabled 1 = vci is enabled note: this bit is not reset on d3 hot to d0 transition; however, it is reset by pltrst#. 30:27 reserved. 26:24 vci id ? r/w. this field assigns a vc id to the vci resource. this field is not used by the ich6 hardware, but it is r/w to avoid confusing software. 23:20 reserved. 19:17 port arbitration select ? ro. hardwired to 0 since this field is not valid for endpoint devices 16 load port arbitration table ? ro. hardwired to 0 since this field is not valid for endpoint devices 15:8 reserved. 7:0 tc/vci map ? r/w, ro. this field indicates the tcs that are mapped to the vci resource. bit 0 is hardwired to 0 indicating that it cannot be mapped to vci. bits [7:1] are implemented as r/w bits. this field is not used by the ich6 hardware , but it is r/w to avoid confusing software. bit description 15:2 reserved. 1 vci negotiation pending ? ro. does not apply. hardwired to 0. 0 port arbitration table status ? ro. hardwired to 0 since this field is not valid for endpoint devices. bit description 31:20 next capability offset ? ro. hardwired to 0 indicating this is the last capability. 19:16 capability version ? ro. hardwired to 1h. 15:0 pci express* extended capabili ty id ? ro. hardwired to 0005h.
648 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.1.46 esd?element self description register (intel ? high definition audi o controller?d27:f0) address offset: 134h attribute: ro default value: 05000100h size: 32 bits 18.1.47 l1desc?link 1 description register (intel ? high definition audi o controller?d27:f0) address offset: 140h attribute: ro default value: 00000001h size: 32 bits 18.1.48 l1addl?link 1 lower address register (intel ? high definition audi o controller?d27:f0) address offset: 148h attribute: ro default value: see register description size: 32 bits bit description 31:24 port number ? ro. hardwired to 05h indicating that the intel high definition audi o controller is assigned as port #5. 23:16 component id ? ro. this field returns the value of the esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:8 number of link entries ? ro. the intel high definition audi o only connects to one device, the ich6 egress port. therefore this field reports a value of 1h. 7:4 reserved. 3:0 element type (eltyp) ? ro. the intel high definition audio controll er is an integrated root complex device. therefore, the field reports a value of 0h. bit description 31:24 target port number ? ro. the intel high definition audio contro ller targets the intel ? ich6?s rcrb egress port, which is port #0. 23:16 target component id ? ro. this field returns the value of the esd.cid field of the chip configuration section. esd.cid is programmed by bios. 15:2 reserved. 1 link type ? ro. hardwired to 0 indicating type 0. 0 link valid ? ro. hardwired to 1. bit description 31:14 link 1 lower address ? ro. hardwired to match the rcba register value in the pci-lpc bridge (d31:f0:f0h). 13:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 649 intel ? high definition audio cont roller registers (d27:f0) 18.1.49 l1addu?link 1 upper address register (intel ? high definition audio controller?d27:f0) address offset: 14ch attribute: ro default value: see register description size: 32 bits 18.2 intel ? high definition audio memory mapped configuration registers (intel ? high definition audio? d27:f0) the base memory location for these memory mapped configuration register s is specified in the hdbar register (d27:f0:offset 10h and d27:f0:o ffset 14h). the individu al registers are then accessible at hdbar + offset as indicated in the following table. these memory mapped registers must be accessed in byte, word, or dword quantities. bit description 31:0 link 1 upper address ? ro. hardwired to match the rcba register value in the pci-lpc bridge (d31:f0:f0h). table 18-2. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 1 of 4) hdbar + offset mnemonic register name default access 00?01h gcap global capabilities 4401h ro 02h vmin minor version 00h ro 03h vmaj major version 01h ro 04?05h outpay output payload capability 003ch ro 06?07h inpay input payload capability 001dh ro 08?0bh gctl global control 00000000h r/w 0c?0dh wakeen wake enable 0000h r/w 0e?0fh statests state change status 0000h r/wc 10?11h gsts global status 0000h r/wc 20?23h intctl interrupt control 00000000h r/w 24?27h intsts interrupt status 00000000h ro 30?33h walclk wall clock counter 00000000h ro 34?37h ssync stream synchronization 00000000h r/w 40?43h corblbase corb lower base address 00000000h r/w, ro 44?47h corbubase corb upper base address 00000000h r/w 48?49h corbwp corb write pointer 0000h r/w 4a?4bh corbrp corb read pointer 0000h r/w 4ch corbctl corb control 00h r/w
650 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 4dh corbst corb status 00h r/wc 4eh corbsize corb size 42h ro 50?53h rirblbase rirb lower base address 00000000h r/w, ro 54?57h rirbubase rirb upper base address 00000000h r/w 58?59h rirbwp rirb write pointer 0000h r/w, ro 5a?5bh rintcnt response interrupt count 0000h r/w 5ch rirbctl rirb control 00h r/w 5dh rirbsts rirb status 00h r/wc 5eh rirbsize rirb size 42h ro 60?63h ic immediate command 00000000h r/w 64?67h ir immediate response 00000000h ro 68?69h irs immediate command status 0000h r/w, r/wc 70?73h dplbase dma position lower base address 00000000h r/w, ro 74?77h dpubase dma position upper base address 00000000h r/w 80?82h isd0ctl input stream descriptor 0 (isd0) control 040000h r/w, ro 83h isd0sts isd0 status 00h r/wc, ro 84?87h isd0lpib isd0 link position in buffer 00000000h ro 88?8bh isd0cbl isd0 cyclic buffer length 00000000h r/w 8c?8dh isd0lvi isd0 last valid index 0000h r/w 8e?8f isd0fifow isd0 fifo watermark 0004h r/w 90?91h isd0fifos isd0 fifo size 0077h ro 92?93h isd0fmt isd0 format 0000h r/w 98?9bh isd0bdpl isd0 buffer descriptor list pointer-lower base address 00000000h r/w, ro 9c?9fh isd0bdpu isd0 buffer description list pointer-upper base address 00000000h r/w a0?a2h isd1ctl input stream descriptor 1(isd01) control 040000h r/w, ro a3h isd1sts isd1 status 00h r/wc, ro a4?a7h isd1lpib isd1 link position in buffer 00000000h ro a8?abh isd1cbl isd1 cyclic buffer length 00000000h r/w ac?adh isd1lvi isd1 last valid index 0000h r/w ae?afh isd1fifow isd1 fifo watermark 0004h r/w b0?b1h isd1fifos isd1 fifo size 0077h ro b2?b3h isd1fmt isd1 format 0000h r/w b8?bbh isd1bdpl isd1 buffer descriptor list pointer-lower base address 00000000h r/w, ro table 18-2. intel ? high definition audio pc i register address map (intel ? high definition audio d27:f0) (sheet 2 of 4) hdbar + offset mnemonic register name default access
intel ? i/o controller hub 6 (ich6) family datasheet 651 intel ? high definition audio cont roller registers (d27:f0) bc?bfh isd1bdpu isd1 buffer description list pointer-upper base address 00000000h r/w c0?c2h isd2ctl input stream descriptor 2 (isd2) control 040000h r/w, ro c3h isd2sts isd2 status 00h r/wc, ro c4?c7h isd2lpib isd2 link position in buffer 00000000h ro c8?cbh isd2cbl isd2 cyclic buffer length 00000000h r/w cc?cdh isd2lvi isd2 last valid index 0000h r/w ce?cfh isd1fifow isd1 fifo watermark 0004h r/w d0?d1h isd2fifos isd2 fifo size 0077h ro d2?d3h isd2fmt isd2 format 0000h r/w d8?dbh isd2bdpl isd2 buffer descriptor list pointer-lower base address 00000000h r/w, ro dc?dfh isd2bdpu isd2 buffer description list pointer-upper base address 00000000h r/w e0?e2h isd3ctl input stream descriptor 3 (isd3) control 040000h r/w, ro e3h isd3sts isd3 status 00h r/wc, ro e4?e7h isd3lpib isd3 link position in buffer 00000000h ro e8?ebh isd3cbl isd3 cyclic buffer length 00000000h r/w ec?edh isd3lvi isd3 last valid index 0000h r/w ee?efh isd3fifow isd3 fifo watermark 0004h r/w f0?f1h isd3fifos isd3 fifo size 0077h ro f2?f3h isd3fmt isd3 format 0000h r/w f8?fbh isd3bdpl isd3 buffer descriptor list pointer-lower base address 00000000h r/w, ro fc?ffh isd3bdpu isd3 buffer description list pointer-upper base address 00000000h r/w 100?102h osd0ctl output stream descriptor 0 (osd0) control 040000h r/w, ro 103h osd0sts osd0 status 00h r/wc, ro 104?107h osd0lpib osd0 link position in buffer 00000000h ro 108?10bh osd0cbl osd0 cyclic buffer length 00000000h r/w 10c?10dh osd0lvi osd0 last valid index 0000h r/w 10e?10fh osd0fifow osd0 fifo watermark 0004h r/w 110?111h osd0fifos osd0 fifo size 00bfh r/w 112?113h osd0fmt osd0 format 0000h r/w 118?11bh osd0bdpl osd0 buffer descriptor list pointer-lower base address 00000000h r/w, ro 11c?11fh osd0bdpu osd0 buffer description list pointer-upper base address 00000000h r/w table 18-2. intel ? high definition audio pci register address map (intel ? high definition audio d27:f0) (sheet 3 of 4) hdbar + offset mnemonic register name default access
652 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 120?122h osd1ctl output stream descript or 1 (osd1) control 040000h r/w, ro 123h osd1sts osd1 status 00h r/wc, ro 124?127h osd1lpib osd1 link position in buffer 00000000h ro 128?12bh osd1cbl osd1 cyclic buffer length 00000000h r/w 12c?12dh osd1lvi osd1 last valid index 0000h r/w 12e?12fh osd1fifow osd1 fifo watermark 0004h r/w 130?131h osd1fifos osd1 fifo size 00bfh r/w 132?133h osd1fmt osd1 format 0000h r/w 138?13bh osd1bdpl osd1 buffer descriptor list pointer-lower base address 00000000h r/w, ro 13c?13fh osd1bdpu osd1 buffer description list pointer-upper base address 00000000h r/w 140?142h osd2ctl output stream descript or 2 (osd2) control 040000h r/w, ro 143h osd2sts osd2 status 00h r/wc, ro 144?147h osd2lpib osd2 link position in buffer 00000000h ro 148?14bh osd2cbl osd2 cyclic buffer length 00000000h r/w 14c?14dh osd2lvi osd2 last valid index 0000h r/w 14e?14fh osd2fifow osd2 fifo watermark 0004h r/w 150?151h osd2fifos osd2 fifo size 00bfh r/w 152?153h osd2fmt osd2 format 0000h r/w 158?15bh osd2bdpl osd2 buffer descriptor list pointer-lower base address 00000000h r/w, ro 15c?15fh osd2bdpu osd2 buffer description list pointer-upper base address 00000000h r/w 160?162h osd3ctl output stream descript or 3 (osd3) control 040000h r/w, ro 163h osd3sts osd3 status 00h r/wc, ro 164?167h osd3lpib osd3 link position in buffer 00000000h ro 168?16bh osd3cbl osd3 cyclic buffer length 00000000h r/w 16c?16dh osd3lvi osd3 last valid index 0000h r/w 16e?16fh osd3fifow osd3 fifo watermark 0004h r/w 170?171h osd3fifos osd3 fifo size 00bfh r/w 172?173h osd3fmt osd3 format 0000h r/w 178?17bh osd3bdpl osd3 buffer descriptor list pointer-lower base address 00000000h r/w, ro 17c?17fh osd3bdpu osd3 buffer description list pointer-upper base address 00000000h r/w table 18-2. intel ? high definition audio pc i register address map (intel ? high definition audio d27:f0) (sheet 4 of 4) hdbar + offset mnemonic register name default access
intel ? i/o controller hub 6 (ich6) family datasheet 653 intel ? high definition audio cont roller registers (d27:f0) 18.2.1 gcap?global ca pabilities register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 00h attribute: ro default value: 4401h size: 16 bits 18.2.2 vmin?minor version register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 02h attribute: ro default value: 00h size: 8 bits 18.2.3 vmaj?major version register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 03h attribute: ro default value: 01h size: 8 bits bit description 15:12 number of output stream supported ? ro. hardwired to 0100b indicating that the ich6 intel high definition audio c ontroller supports 4 output streams. 11:8 number of input stream supported ? ro. hardwired to 0100b indicating that the ich6 intel high definition audio c ontroller supports 4 input streams. 7:3 number of bidirectional stream supported ? ro. hardwired to 0 indicating that the ich6 intel high definition audio controller s upports 0 bidirectional stream. 2 reserved. 1 number of serial data out signals ? ro. hardwired to 0 indicating that the ich6 intel high definition audio contro ller supports 1 serial data output signal. 0 64-bit address supported ? ro. hardwired to 1b indicating that the ich6 intel high definition audio controller supports 64-bit addressing for bdl addresses, data buffer addressees, and command buffer addresses. bit description 7:0 minor version ? ro. hardwired to 0 indicating that the intel ? ich6 supports minor revision number 00h of the intel high definition audi o specification. bit description 7:0 major version ? ro. hardwired to 01h indicating that the intel ? ich6 supports major revision number 1 of the intel high definition audi o specification.
654 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.4 outpay?output payload capability register (intel ? high definition audi o controller?d27:f0) memory address: hdar + 04h attribute: ro default value: 003ch size: 16 bits 18.2.5 inpay?input payloa d capability register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 06h attribute: ro default value: 001dh size: 16 bits bit description 15:7 reserved. 6:0 output payload capability ? ro. hardwired to 3ch indicating 60 word payload. this field indicates the total output payload avai lable on the link. this does not include bandwidth used for command and control. this measurement is in 16-bit word quantities per 48 mhz frame. the default link clock of 24.000 mhz (the data is double pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for command and control, leaving 60 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload. bit description 15:7 reserved. 6:0 input payload capability ? ro. hardwired to 1dh indicating 29 word payload. this field indicates the total output payload avai lable on the link. this does not include bandwidth used for response. this measurement is in 16-bit word quantities per 48 mhz frame. the default link clock of 24.000 mhz provides 500 bits per frame, or 31.25 words in total. 36 bits are used for response, leaving 29 words available for data payload. 00h = 0 word 01h = 1 word payload. ..... ffh = 256 word payload.
intel ? i/o controller hub 6 (ich6) family datasheet 655 intel ? high definition audio cont roller registers (d27:f0) 18.2.6 gctl?global control register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 08h attribute: r/w default value: 00000000h size: 32 bits bit description 31:9 reserved. 8 accept unsolicited response enable ? r/w. 0 = unsolicited respons es from the codecs are not accepted. 1 = unsolicited response from the codecs are acc epted by the controller and placed into the response input ring buffer. 7:2 reserved. 1 flush control ? r/w. writing a 1 to this bit initiates a flush. when the flush completion is received by the controller, hardware sets the flush status bi t and clears this flush control bit. before a flush cycle is initiated, the dma position buffer must be programmed with a valid memory address by software, but the dma position buffer bit 0 needs not be set to enable the position reporting mechanism. also, all streams must be stopped (the associated run bit must be 0). when the flush is initiated, the controller will fl ush the pipelines to memory to guarantee that the hardware is ready to transition to a d3 state. setti ng this bit is not a critical step in the power state transition if the content of the fifios is not critical. 0 controller reset # (crst#) ? r/w. 0 = writing a 0 to this bit causes the intel high definition audio controll er to be reset. all state machines, fifos and non-resume well memory mapped configuration registers (not pci configuration registers) in the c ontroller will be reset. the intel high definition audio link reset# signal will be asserted, and all other link signals will be driven to their default values. after the hardware has completed sequencing into the reset state, it will report a 0 in this bit. software must read a 0 from this bit to verify the controller is in reset. 1 = writing a 1 to this bit causes the controller to exit its reset state and de-assert the intel high definition audio link reset# signal. software is responsible for setting/cl earing this bit such that the minimum intel high definition audio link reset # signal assertion pulse width specification is met. when the cont roller hardware is ready to begin operation, it will report a 1 in this bit. software must read a 1 from this bit before accessing any controll er registers. this bit defaults to a 0 after hardware reset, therefore, so ftware needs to write a 1 to this bit to begin operation. notes: 1. the corb/rirb run bits and all stream run bits must be verified cleared to 0 before writing a 0 to this bit in order to assure a clean re-start. 2. when setting or clearing this bit, software must ensure that minimum link timing requirements (minimum reset# assertion time, etc.) are met. 3. when this bit is 0 indicating that the c ontroller is in reset, writes to all intel high definition audio memory mapped registers are ignored as if the devi ce is not present. the only exception is this register itself. the global control register is write-able as a dword, word, or byte even when crst# (this bit) is 0 if the by te enable for the byte containing the crst# bit (byte enable 0) is active. if byte enable 0 is not active, writes to the global cont rol register will be ignored when crst# is 0. when crst# is 0, reads to intel high definition audio memory mapped registers will return their default value except for registers that are not reset with pltrst# or on a d3 hot to d0 transition.
656 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.7 wakeen?wake enable register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 0ch attribute: r/w default value: 0000h size: 16 bits 18.2.8 statests?state change status register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 0eh attribute: r/wc default value: 0000h size: 16 bits 18.2.9 gsts?global status register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 10h attribute: r/wc default value: 0000h size: 16 bits bit description 15:3 reserved. 2:0 sdin wake enable flags ? r/w. these bits control which sdi signal(s) may generate a wake event. a 1b in the bit mask indicates that the asso ciated sdin signal is enabled to generate a wake. bit 0 is used for sdi[0] bit 1 is used for sdi[1] bit 2 is used for sdi[2] note: these bits are in the resume well and only cleared on a power on reset. software must not make assumptions about the reset state of t hese bits and must set them appropriately. bit description 15:3 reserved. 2:0 sdin state change status flags ? r/wc. flag bits that indicate which sdi signal(s) received a state change event. the bits are cl eared by writing 1s to them. bit 0 = sdi[0] bit 1 = sdi[1] bit 2 = sdi[2] note: these bits are in the resume well and only cleared on a power on reset. software must not make assumptions about the reset state of t hese bits and must set them appropriately. bit description 15:2 reserved. 1 flush status ? r/wc. this bit is set to 1 by hardware to indicate that the flush cycle initiated when the flush control bit (hdbar + 08h, bit 1) was set has completed. software must write a 1 to clear this bit before the next time the flush control bit is set to clear the bit. 0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 657 intel ? high definition audio cont roller registers (d27:f0) 18.2.10 intctl?interrupt control register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 20h attribute: r/w default value: 00000000h size: 32 bits bit description 31 global interrupt enable (gie) ? r/w. global bit to enable device interrupt generation. when set to 1, the intel high definition audio f unction is enabled to generate an interrupt. this control is in addition to any bits in the bus s pecific address space, such as t he interrupt enable bit in the pci configuration space. note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt enable (cie) ? r/w. enables the general interr upt for controller functions. when set to 1, the controller generates an interr upt when the corresponding status bit gets set due to a response interrupt, a response buffer overrun, and state change events. note: this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrupt enable (sie) ? r/w. when set to 1, the individual streams are enabled to generate an interrupt when the corresponding status bits get set. a stream interrupt will be caused as a result of a buffer with ioc = 1in the bdl entry being completed, or as a result of a fifo error ( underrun or overrun) occurring. control over the generation of each of these sources is in the associated stream descriptor. the streams are numbered and the sie bits assigned sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 bit 5: output stream 2 bit 6: output stream 3 bit 7: output stream 4
658 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.11 intsts?interrupt status register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 24h attribute: ro default value: 00000000h size: 32 bits 18.2.12 walclk?wall clo ck counter register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 30h attribute: ro default value: 00000000h size: 32 bits bit description 31 global interrupt status (gis) ? ro. th is bit is an or of all the interrupt status bits in this register. note: this bit is not affected by the d3 hot to d0 transition. 30 controller interrupt status (cis) ? ro. status of general controller interrupt. 1 = indicates that an interrupt co ndition occurred due to a respons e interrupt, a response buffer overrun interrupt, or a sdin state change event. the exact cause can be determined by interrogating other registers. this bit is an or of all of the stated interrupt status bits for this register. notes: 1. this bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware interrupt will not be generated unles s the corresponding enable bit is set. 2. this bit is not affected by the d3 hot to d0 transition. 29:8 reserved 7:0 stream interrupt status (sis) ? ro. 1 = indicates that an interrupt condition occurred on th e corresponding stream. this bit is an or of all of the stream?s interrupt status bits. note: these bits are set regardless of the state of the corresponding interrupt enable bits. the streams are numbered and the sie bits assi gned sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 bit 5: output stream 2 bit 6: output stream 3 bit 7: output stream 4 bit description 31:0 wall clock counter ? ro. 32 bit counter that is incremented on each link bclk period and rolls over from ffff ffffh to 0000 0000h. this counter will roll over to 0 with a period of approximately 179 seconds. this counter is enabled while the bclk bit is set to 1. software uses this counter to synchronize between multiple controllers. will be reset on controller reset.
intel ? i/o controller hub 6 (ich6) family datasheet 659 intel ? high definition audio cont roller registers (d27:f0) 18.2.13 ssync?stream synchronization register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 34h attribute: r/w default value: 00000000h size: 32 bits bit description 31:8 reserved 7:0 stream synchronization (ssync) ? r/w. when set to 1, these bits block data from being sent on or received from the link. each bit controls the as sociated stream descriptor (i.e. bit 0 corresponds to the first stream descriptor, etc.) to synchronously start a set of dma engines, these bi ts are first set to 1. the run bits for the associated stream descriptors are then set to 1 to start the dma engines. when all streams are ready (fifordy =1), the associated ssync bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame. to synchronously stop the streams, fist these bits are set, and then the individual run bits in the stream descriptor are cleared by software. if synchronization is not desired, these bits may be left as 0, and the stream will simply begin running normally when the stream?s run bit is set. the streams are numbered and the sie bits assigned sequentially, based on their order in the register set. bit 0: input stream 1 bit 1: input stream 2 bit 2: input stream 3 bit 3: input stream 4 bit 4: output stream 1 bit 5: output stream 2
660 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.14 corblbase?corb lowe r base address register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 40h attribute: r/w, ro default value: 00000000h size: 32 bits 18.2.15 corbubase?corb upper base address register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 44h attribute: r/w default value: 00000000h dword size: 32 bits 18.2.16 corbrp?corb writ e pointer register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 48h attribute: r/w default value: 0000h size: 16 bits bit description 31:7 corb lower base address ? r/w. lower address of the command output ring buffer, allowing the corb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 corb lower base unimplemented bits ? ro. hard wired to 0. this required the corb to be allocated with 128b granularity to allow for cache line fetch optimizations. bit description 31:0 corb upper base address ? r/w. upper 32 bits of the address of the command output ring buffer. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. bit description 15:8 reserved. 7:0 corb write pointer ? r/w. software writes the last valid corb entry offset into this field in dword granularity. the dma engine fetches commands from the corb until the read pointer matches the write pointer. supports 256 corb entri es (256x4b = 1kb). this register field may be written while the dma engine is running.
intel ? i/o controller hub 6 (ich6) family datasheet 661 intel ? high definition audio cont roller registers (d27:f0) 18.2.17 corbrp?corb read pointer register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 4ah attribute: r/w default value: 0000h size: 16 bits 18.2.18 corbctl?corb control register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 4ch attribute: r/w default value: 00h size: 8 bits bit description 15 corb read pointer reset ? r/w. software writes a 1 to this bit to reset the corb read pointer to 0 and clear any residual prefetched commands in the corb hardware buffer within the intel high definition audio cont roller. the hardware will physically update this bit to 1 when the corb pointer reset is complete. software must read a 1 to verify that the reset completed correctly. software must clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. the corb dma engine must be stopped prior to resetting the read pointer or else dma transfer may be corrupted. 14:8 reserved. 7:0 corb read pointer ? r/w. software reads this field to determine how many commands it can write to the corb without over-running. the value read indicates the corb read pointer offset in dword granularity. the offset entry read from th is field has been successf ully fetched by the dma controller and may be over-written by software. s upports 256 corb entries (256x4b = 1kb). this register field may be ready while the dma engine is running. bit description 7:2 reserved. 1 enable corb dma engine ? r/w. 0 = dma stop 1 = dma run after software writes a 0 to this bit, the hardw are may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from this bit to verify that the dma engine is truly stopped. 0 corb memory error interrupt enable ? r/w. if this bit is set the controller will generate an interrupt if the cmei status bit (hdbar + 4dh: bit 0) is set.
662 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.19 corbst?corb status register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 4dh attribute: r/wc default value: 00h size: 8 bits 18.2.20 corbsize?corb size register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 4eh attribute: ro default value: 42h size: 8 bits 18.2.21 rirblbase?rirb lo wer base addr ess register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 50h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 7:1 reserved. 0 corb memory error indication (cmei) ? r/wc. if this bit is set, the controller has detected an error in the path way between the controller and memory. this may be an ecc bit error or any other type of detectable data error which renders the command data fetched invalid. software can clear this bit by writi ng a 1 to it. however, this type of error leaves the audio subsystem in an unviable state and typically requi red a controller reset by writing a 0 to the controller reset # bit (hdbar + 08h: bit 0). bit description 7:4 corb size capability ? ro. hardwired to 0100b i ndicating that the ich6 only supports a corb size of 256 corb entries (1024b) 3:2 reserved. 1:0 corb size ? ro. hardwired to 10b which sets the corb size to 256 entries (1024b) bit description 31:7 corb lower base address ? r/w. lower address of the response input ring buffer, allowing the rirb base address to be assigned on any 128-b boundary. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. 6:0 rirb lower base unimplemented bits ? ro. ha rdwired to 0. this required the rirb to be allocated with 128-b granularity to allo w for cache line fetch optimizations.
intel ? i/o controller hub 6 (ich6) family datasheet 663 intel ? high definition audio cont roller registers (d27:f0) 18.2.22 rirbubase?rirb uppe r base address register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 54h attribute: r/w default value: 00000000h size: 32 bits 18.2.23 rirbwp?rirb writ e pointer register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 58h attribute: r/w, ro default value: 0000h size: 16 bits 18.2.24 rintcnt?response in terrupt count register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 5ah attribute: r/w default value: 0000h size: 16 bits bit description 31:0 rirb upper base address ? r/w. upper 32 bits of the address of the response input ring buffer. this register field must not be written when the dma engine is running or the dma transfer may be corrupted. bit description 15 rirb write pointer reset ? r/w. software writes a 1 to this bit to reset the rirb write pointer to 0. the rirb dma engine must be stopped prior to resetting the write pointer or else dma transfer may be corrupted. this bit is always read as 0. 14:8 reserved. 7:0 rirb write pointer (rirbwp) ? ro. indicates t he last valid rirb entry written by the dma controller. software reads this field to determine how many responses it can read from the rirb. the value read indicates the rirb write pointer offset in 2 dword rirb entry units (since each rirb entry is 2 dwords long). supports up to 256 ri rb entries (256 x 8 b = 2 kb). this register field may be written when the dma engine is running. bit description 15:8 reserved. 31:0 n response interrupt count ? r/w. 0000 0001b = 1 response sent to rirb ........... 1111 1111b = 255 responses sent to rirb 0000 0000b = 256 responses sent to rirb the dma engine should be stopped when changing this field or else an interrupt may be lost. note that each response occupi es 2 dwords in the rirb. this is compared to the total number of res ponses that have been returned, as opposed to the number of frames in which there were response s. if more than one codecs responds in one frame, then the count is increased by the number of responses received in the frame.
664 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.25 rirbctl?rirb control register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 5ch attribute: r/w default value: 00h size: 8 bits 18.2.26 rirbsts?rirb status register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 5dh attribute: r/wc default value: 00h size: 8 bits bit description 7:3 reserved. 2 response overrun interrupt control ? r/w. if this bit is set, the hardware will generate an interrupt when the response overrun interrupt status bit (hdbar + 5dh: bit 2) is set. 1 enable rirb dma engine ? r/w. 0 = dma stop 1 = dma run after software writes a 0 to this bit, the har dware may not stop immediately. the hardware will physically update the bit to 0 when the dma engine is truly stopped. software must read a 0 from this bit to verify that the dma engine is truly stopped. 0 response interrupt control ? r/w. 0 = disable interrupt 1 = generate an interrupt after n number of responses are sent to the rirb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs first). the n counter is reset when the interrupt is generated. bit description 7:3 reserved. 2 response overrun interrupt status ? r/wc. software sets this bit to 1 when the rirb dma engine is not able to write the incoming responses to memory before additional incoming responses overrun the internal fifo. when the overrun occurs , the hardware will drop the responses which overrun the buffer. an interrupt may be generated if the response overrun interrupt control bit is set. note that this status bit is set even if an interrupt is not enabled for this event. software clears this bit by writing a 1 to it. 1 reserved. 0 response interrupt ? r/wc. hardware sets this bit to 1 when an interrupt has been generated after n number of responses are sent to the ri rb buffer or when an empty response slot is encountered on all sdi[x] inputs (whichever occurs firs t). note that this status bit is set even if an interrupt is not enabled for this event. software clears this bit by writing a 1 to it.
intel ? i/o controller hub 6 (ich6) family datasheet 665 intel ? high definition audio cont roller registers (d27:f0) 18.2.27 rirbsize?rirb size register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 5eh attribute: ro default value: 42h size: 8 bits 18.2.28 ic?immediate command register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 60h attribute: r/w default value: 00000000h size: 32 bits 18.2.29 ir?immediate response register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 64h attribute: ro default value: 00000000h size: 32 bits bit description 7:4 rirb size capability ? ro. hardwired to 0100b i ndicating that the ich6 only supports a rirb size of 256 rirb entries (2048b) 3:2 reserved. 1:0 rirb size ? ro. hardwired to 10b which sets the corb size to 256 entries (2048b) bit description 31:0 immediate command write ? r/w . the command to be sent to the codec via the immediate command mechanism is written to this register. the command stored in this register is sent out over the link during the next available frame after a 1 is written to the icb bit (hdbar + 68h: bit 0) bit description 31:0 immediate response read (irr) ? ro. this register contains the response received from a codec resulting from a command sent via the immediate command mechanism. if multiple codecs responded in the same time, t here is no guarantee as to which response will be latched. therefore, broadcast-type commands mu st not be issued via the immediate command mechanism.
666 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.30 irs?immediate command status register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 68h attribute: r/w, r/wc default value: 0000h size: 16 bits 18.2.31 dplbase?dma position lo wer base addr ess register (intel ? high definition audi o controller?d27:f0) memory address: hdbar + 70h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 15:2 reserved. 1 immediate result valid (irv) ? r/wc. this bit is set to 1 by hardware when a new response is latched into the immediate response register (hdbar + 64). this is a status flag indicating that software may read the response from the immediate response register. software must clear this bit by writing a 1 to it before issuing a new command so that the software may determine when a new response has arrived. 0 immediate command busy (icb) ? r/w. when this bit is read as 0, it indicates that a new command may be issued using the immediate command mechanism. when this bit transitions from a 0 to a 1 (via software writing a 1), the contro ller issues the command currently stored in the immediate command register to the codec over the link. when the corresponding response is latched into the immediate response register, the controller hardware sets the irv flag and clears the icb bit back to 0. note: an immediate command must not be iss ued while the corb/rirb mechanism is operating, otherwise the responses conflic t. this must be enforced by software. bit description 31:7 dma position lower base address ? r/w. lower 32 bits of the dma position buffer base address. this register field must not be wri tten when any dma engine is running or the dma transfer may be corrupted. this same address is used by the flush control and must be programmed with a valid value before the fl ush control bit (hdbar+08h:bit 1) is set. 6:1 dma position lower base unimplemented bits ? ro. hardwired to 0 to force the 128-byte buffer alignment for cache li ne write optimizations. 0 dma position buffer enable ? r/w. when this bit is set to 1, the controller will write the dma positions of each of the dma engines to the buffer in the main memory periodi cally (typically once per frame). software can use this value to know what data in memory is valid data.
intel ? i/o controller hub 6 (ich6) family datasheet 667 intel ? high definition audio cont roller registers (d27:f0) 18.2.32 dpubase?dma position upper base addr ess register (intel ? high definition audio controller?d27:f0) memory address: hdbar + 74h attribute: r/w default value: 00000000h size: 32 bits 18.2.33 sdctl?stream descri ptor control register (intel ? high definition audio controller?d27:f0) memory address: input stream[0]: hdbar + 80h attribute:r/w, ro input stream[1]: hdbar + a0h input stream[2]: hdbar + c0h input stream[3]: hdbar + e0h output stream[0]: hdbar + 100h output stream[1]: hdbar + 120h output stream[2]: hdbar + 140h output stream[3]: hdbar + 160h default value: 040000h size:24 bits bit description 31:0 dma position upper base address ? r/w. upper 32 bits of the dma position buffer base address. this register field must not be wri tten when any dma engine is running or the dma transfer may be corrupted. bit description 23:20 stream number ? r/w. this value reflect the tag associ ated with the data being transferred on the link. when data controlled by this descri ptor is sent out over the link, it will have its stream number encoded on the sync signal. when an input stream is detected on any of the sdi signals that match this value, the data samples are loaded into fifo associ ated with this descriptor. note that while a single sdi input may contain data from more than one stream number, two different sdi inputs may not be configured with the same stream number. 0000 = reserved 0001 = stream 1 ........ 1110 = stream 14 1111 = stream 15 19 bidirectional directi on control ? ro. this bit is only meaningful for bidirectional streams; therefore, this bit is hardwired to 0. 18 traffic priority ? ro. hardwired to 1 indicating that all streams will use vc1 if it is enabled through the pci express* registers. 17:16 stripe control ? ro. this bit is only meaningful for input streams; therefore, this bit is hardwired to 0. 15:5 reserved 4 descriptor error interrupt enable ? r/w. 0 = disable 1 = an interrupt is generated when the descriptor error status bit is set.
668 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 3 fifo error interrupt enable ? r/w. this bit controls whether the occurrence of a fifo error (overrun for input or underrun for output) will cause an interrupt or not. if this bit is not set, bit 3in the status register will be set, but the interrupt will not occur. either way, the samples will be dropped. 2 interrupt on completion enable ? r/w. this bit controls whether or not an interrupt occurs when a buffer completes with the ioc bit set in its descriptor. if this bit is not set, bit 2 in the status register will be set, but the interrupt will not occur. 1 stream run (run) ? r/w. 0 = when cleared to 0, the dma engine associated with this input stream will be disabled. the hardware will report a 0 in this bit when the dma engine is actually stopped. software must read a 0 from this bit before modifying relat ed control registers or restarting the dma engine. 1 = when set to 1, the dma engine associated with this input stream will be enabled to transfer data from the fifo to the main memory. the ssync bit must also be cleared in order for the dma engine to run. for output streams, the cadence generator is reset whenever the run bit is set. 0 stream reset (srst) ? r/w. 0 = writing a 0 causes the corresponding stream to exit reset. when the stream hardware is ready to begin operation, it will report a 0 in this bit. software must read a 0 from this bit before accessing any of the stream registers. 1 = writing a 1 causes the corresponding stream to be reset. the stream descriptor registers (except the srst bit itself) and fifo?s for the corresponding stream are reset. after the stream hardware has completed sequencing into the reset state, it will report a 1 in this bit. software must read a 1 from this bit to verify that the stream is in reset. the run bit must be cleared before srst is asserted. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 669 intel ? high definition audio cont roller registers (d27:f0) 18.2.34 sdsts?stream descriptor status register (intel ? high definition audio controller?d27:f0) memory address: input stream[0]: hdbar + 83h attribute:r/wc, ro input stream[1]: hdbar + a3h input stream[2]: hdbar + c3h input stream[3]: hdbar + e3h output stream[0]: hdbar + 103h output stream[1]: hdbar + 123h output stream[2]: hdbar + 143h output stream[3]: hdbar + 163h default value: 00h size: 8 bits bit description 7:6 reserved. 5 fifo ready (fifordy) ? ro. for output streams, the controller hardware will set th is bit to 1 while the ou tput dma fifo contains enough data to maintain the stream on the link. this bit defaults to 0 on reset because the fifo is cleared on a reset. for input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and the engine is ready for the run bit to be set. 4 descriptor error ? r/wc. when set, this bit indicates that a serious error occurred during the fetch of a descriptor. this could be a result of a master abort, a parity or ecc error on the bus, or any other error which renders the current buffer descriptor or buffer descriptor list useless. this error is treated as a fatal stream error, as the stream cannot continue running. th e run bit will be cleared and the stream will stopped. software may attempt to restart the stream engine after addressing the cause of the error and writing a 1 to this bit to clear it. 3 fifo error ? r/wc. this bit is set when a fifo error occu rs. this bit is set even if an interrupt is not enabled. the bit is cleared by writing a 1 to it. for an input stream, this indicates a fifo overr un occurring while the run bit is set. when this happens, the fifo pointers do not increment and the incoming data is not written into the fifo, thereby being lost. for an output stream, this indicates a fifo under run when there are still buffers to send. the hardware should not transmit anythi ng on the link for the associated stream if there is not valid data to send. 2 buffer completion interrupt status ? r/wc. this bit is set to 1 by the hardware after the last sample of a buffer has been processed, and if the interrupt on completion bit is set in the command by te of the buffer descriptor. it remains active until software clears it by writing a 1 to it. 1:0 reserved.
670 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.35 sdlpib?stream descript or link position in buffer register (intel ? high definition audio controller?d27:f0) memory address: input stream [0]: hdbar + 84h attribute:ro input stream[1]: hdbar + a4h input stream[2]: hdbar + c4h input stream[3]: hdbar + e4h output stream[0]: hdbar + 104h output stream[1]: hdbar + 124h output stream[2]: hdbar + 144h output stream[3]: hdbar + 164h default value: 00000000h size: 32 bits 18.2.36 sdcbl?stream descriptor cy clic buffer length register (intel ? high definition audi o controller?d27:f0) memory address: input stream [0]: hdbar + 88h attribute:r/w input stream[1]: hdbar + a8h input stream[2]: hdbar + c8h input stream[3]: hdbar + e8h output stream[0]: hdbar + 108h output stream[1]: hdbar + 128h output stream[2]: hdbar + 148h output stream[3]: hdbar + 168h default value: 00000000h size: 32 bits bit description 31:0 link position in buffer ? ro. indicates the num ber of bytes that have been received off the link. this register will count from 0 to the value in the cyclic buffer length register and then wrap to 0. bit description 31:0 cyclic buffer length ? r/w. indicates the number of bytes in the complete cyclic buffer. this register represents an integer number of samples. link position in buffer will be reset when it reaches this value. software may only write to this register after global reset, controller reset, or stream reset has occurred. this value should be only modified when the run bit is 0. once the run bit has been set to enable the engine, software must not write to this register until after the next reset is asserted, or transfer may be corrupted.
intel ? i/o controller hub 6 (ich6) family datasheet 671 intel ? high definition audio cont roller registers (d27:f0) 18.2.37 sdlvi?stream descriptor last valid index register (intel ? high definition audio controller?d27:f0) memory address: input stream[0]: hdbar + 8ch attribute:r/w input stream[1]: hdbar + ach input stream[2]: hdbar + cch input stream[3]: hdbar + ech output stream[0]: hdbar + 10ch output stream[1]: hdbar + 12ch output stream[2]: hdbar + 14ch output stream[3]: hdbar + 16ch default value: 0000h size: 16 bits 18.2.38 sdfifow?stream descript or fifo watermark register (intel ? high definition audio controller?d27:f0) memory address: input stream[0]: hdbar + 8eh attribute:r/w input stream[1]: hdbar + aeh input stream[2]: hdbar + ceh input stream[3]: hdbar + eeh output stream[0]: hdbar + 10eh output stream[1]: hdbar + 12eh output stream[2]: hdbar + 14eh output stream[3]: hdbar + 16eh default value: 0004h size: 16 bits bit description 15:8 reserved. 7:0 last valid index ? r/w. the value written to this register in dicates the index for the last valid buffer descriptor in bdl. after the controller has process ed this descriptor, it will wrap back to the first descriptor in the list and continue processing. this field must be at least 1, i.e. there must be at least 2 valid entries in the buffer descriptor list before dma operations can begin. this value should only modi fied when the run bit is 0. bit description 15:3 reserved. 2:0 fifo watermark (fifow) ? r/w. indicates the minimum number of bytes accumulated/free in the fifo before the controller will start a fetch/eviction of data. 010 = 8b 011 = 16b 100 = 32b (default) others = unsupported notes: 1. when the bit field is programmed to an unsupport ed size, the hardware sets itself to the default value. 2. software must read the bit field to test if the value is supported after setting the bit field.
672 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.39 sdfifos?stream descri ptor fifo size register (intel ? high definition audi o controller?d27:f0) memory address: input stream[0]: hdbar + 90h attribute:input: ro input stream[1]: hdbar + b0h output: r/w input stream[2]: hdbar + d0h input stream[3]: hdbar + f0h output stream[0]: hdbar + 110h output stream[1]: hdbar + 130h output stream[2]: hdbar + 150h output stream[3]: hdbar + 170h default value: input stream: 0077h size: 16 bits output stream: 00bfh bit description 15:8 reserved. 7:0 fifo size ? ro (input stream), r/w (output stream). indicates the maximum number of bytes that could be fetched by the controller at one time. this is the maximum number of bytes that may have been dma?d into memory but not yet transmitted on th e link, and is also the maximum possible value that the picb count will increase by at one time. the value in this field is different for input and output streams. it is also dependent on the bits per samples setting for the corresponding stream. foll owing are the values read/written from/to this register for input and output streams, and for non-padded and padded bit formats: output stream r/w value : notes: 1. all other values not listed are not supported. 2. when the output stream is programmed to an unsupported size, the hardware sets itself to the default value (bfh). 3. software must read the bit field to test if the value is supported after setting the bit field. input stream ro value : note: the default value is different for input and out put streams, and reflects the default state of the bits fields (in stream descriptor form at registers) for the corresponding stream. value output streams 0fh = 16b 8, 16, 20, 24, or 32 bit output streams 1fh = 32b 8, 16, 20, 24, or 32 bit output streams 3fh = 64b 8, 16, 20, 24, or 32 bit output streams 7fh = 128b 8, 16, 20, 24, or 32 bit output streams bfh = 192b 8, 16, or 32 bit output streams ffh = 256b 20, 24 bit output streams value input streams 77h = 120b 8, 16, 32 bit input streams 9fh = 160b 20, 24 bit input streams
intel ? i/o controller hub 6 (ich6) family datasheet 673 intel ? high definition audio cont roller registers (d27:f0) 18.2.40 sdfmt?stream descr iptor format register (intel ? high definition audio controller?d27:f0) memory address: input stream[0 ]: hdbar + 92h attribute: r/w input stream[1]: hdbar + b2h input stream[2]: hdbar + d2h input stream[3]: hdbar + f2h output stream[0]: hdbar + 112h output stream[1]: hdbar + 132h output stream[2]: hdbar + 152h output stream[3]: hdbar + 172h default value: 0000h size: 16 bits bit description 15 reserved. 14 sample base rate ? r/w 0 = 48 khz 1 = 44.1 khz 13:11 sample base rate multiple ? r/w 000 = 48 khz, 44.1 khz or less 001 = x2 (96 khz, 88.2 khz, 32 khz) 010 = x3 (144 khz) 011 = x4 (192 khz, 176.4 khz) others = reserved. 10:8 sample base rate devisor ? r/w. 000 = divide by 1(48 khz, 44.1 khz) 001 = divide by 2 (24 khz, 22.05 khz) 010 = divide by 3 (16 khz, 32 khz) 011 = divide by 4 (11.025 khz) 100 = divide by 5 (9.6 khz) 101 = divide by 6 (8 khz) 110 = divide by 7 111 = divide by 8 (6 khz) 7 reserved. 6:4 bits per sample (bits) ? r/w. 000 = 8 bits. the data will be packed in me mory in 8-bit containers on 16-bit boundaries 001 = 16 bits. the data will be packed in memo ry in 16-bit containers on 16-bit boundaries 010 = 20 bits. the data will be packed in memo ry in 32-bit containers on 32-bit boundaries 011 = 24 bits. the data will be packed in memory in 32-bit containers on 32-bit boundaries 100 = 32 bits. the data will be packed in memo ry in 32-bit containers on 32-bit boundaries others = reserved. 3:0 number of channels (chan) ? r/w. indicates number of channels in each frame of the stream. 0000 =1 0001 =2 ........ 1111 =16
674 intel ? i/o controller hub 6 (i ch6) family datasheet intel ? high definition audio c ontroller registers (d27:f0) 18.2.41 sdbdpl?stream descriptor buffer descript or list pointer lower base address register (intel ? high definition audi o controller?d27:f0) memory address: input stream[0 ]: hdbar + 98h attribute: r/w,ro input stream[1]: hdbar + b8h input stream[2]: hdbar + d8h input stream[3]: hdbar + f8h output stream[0]: hdbar + 118h output stream[1]: hdbar + 138h output stream[2]: hdbar + 158h output stream[3]: hdbar + 178h default value: 00000000h size: 32 bits 18.2.42 sdbdpu?stream descriptor bu ffer descriptor list pointer upper base address register (intel ? high definition audio controller ?d27:f0) memory address: input stream [0]: hdbar + 9ch attribute: r/w input stream[1]: hdbar + bch input stream[2]: hdbar + dch input stream[3]: hdbar + fch output stream[0]: hdbar + 11ch output stream[1]: hdbar + 13ch output stream[2]: hdbar + 15ch output stream[3]: hdbar + 17ch default value: 00000000h size: 32 bits bit description 31:7 buffer descriptor list pointer lower base address ? r/w. lower address of the buffer descriptor list. this value shoul d only be modified when the run bit is 0, or dma transfer may be corrupted. 6:0 hardwired to 0 forcing alignment on 128-b boundaries. bit description 31:0 buffer descriptor list pointer upper base address ? r/w. upper 32-bit address of the buffer descriptor list. this value shoul d only be modified when the run bit is 0, or dma transfer may be corrupted.
intel ? i/o controller hub 6 (ich6) family datasheet 675 pci express* configuration registers 19 pci express* configuration registers 19.1 pci express* configuration registers (pci express?d28:f0/f1/f2/f3) note: register address locations that are not shown in table 19-1 and should be treated as reserved. table 19-1. pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3) (sheet 1 of 3) offset mnemonic register name function 0 default function 1 default function 2 default function 3 default type 00?01h vid vendor identification 8086h 8086h 8086h 8086h ro 02?03h did device identification 2660h 2662h 2664h 2666h ro 04?05h pcicmd pci command 0000h 0000h 0000h 0000h r/w, ro 06?07h pcists pci status 0010h 0010h 0010h 0010h r/wc, ro 08h rid revision identification see register description. see register description. see register description. see register description. ro 09h pi programming interface 00h 00h 00h 00h ro 0ah scc sub class code 04h 04h 04h 04h ro 0bh bcc base class code 06h 06h 06h 06h ro 0ch cls cache line size 00h 00h 00h 00h r/w 0dh plt primary latency timer 00h 00h 00h 00h ro 0eh headtyp header type 81h 81h 81h 81h ro 18?1ah bnum bus number 000000h 000000h 000000h 000000h r/w 1c?1dh iobl i/o base and limit 0000h 0000h 0000h 0000h r/w, ro 1e?1fh ssts secondary status register 0000h 0000h 0000h 0000h r/wc 20?23h mbl memory base and limit 00000000h 00000000h 00000000h 00000000h r/w 24?27h pmbl prefetchable memory base and limit 00010001h 00010001h 00010001h 00010001h r/w, ro 28?2bh pmbu32 prefetchable memory base upper 32 bits 00000000h 00000000h 00000000h 00000000h r/w 2c?2fh pmlu32 prefetchable memory limit upper 32 bits 00000000h 00000000h 00000000h 00000000h r/w 34h capp capabilities list pointer 40h 40h 40h 40h ro 3c?3dh intr interrupt information see bit description see bit description see bit description see bit description r/w, ro 3e?3fh bctrl bridge control register 0000h 0000h 0000h 0000h r/w
676 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 40?41h clist capabilities list 8010 8010 8010 8010 ro 42?43h xcap pci express* capabilities 0041 0041 0041 0041 r/wo, ro 44?47h dcap device capabilities 00000fe0h 00000fe0h 00000fe0h 00000fe0h ro 48?49h dctl device control 0000h 0000h 0000h 0000h r/w, ro 4a?4bh dsts device status 0010h 0010h 0010h 0010h r/wc, ro 4c?4fh lcap link capabilities see bit description see bit description see bit description see bit description r/w, ro, r/wo 50?51h lctl link control 0000h 0000h 0000h 0000h r/w, r/w (special), ro 52?53h lsts link status see bit description see bit description see bit description see bit description ro 54?57h slcap slot capabilities register 00000060h 00000060h 00000060h 00000060h r/wo, ro 58?59h slctl slot control 0000h 0000h 0000h 0000h r/w, ro 5a?5bh slsts slot status 0000h 0000h 0000h 0000h r/wc, ro 5c?5dh rctl root control 0000h 0000h 0000h 0000h r/w 60?63h rsts root status 00000000h 00000000h 00000000h 00000000h r/wc, ro 80?81h mid message signaled interrupt identifiers 9005h 9005h 9005h 9005h ro 82?83h mc message signaled interrupt message control 0000h 0000h 0000h 0000h r/w, ro 84?87h ma message signaled interrupt message address 00000000h 00000000h 00000000h 00000000h r/w 88?89h md message signaled interrupt message data 0000h 0000h 0000h 0000h r/w 90?91h svcap subsystem vendor capability a00dh a00dh a00dh a00dh ro 94?97h svid subsystem vendor identification 00000000h 00000000h 00000000h 00000000h r/wo a0?a1h pmcap power management capability 0001h 0001h 0001h 0001h ro a2?a3h pmc pci power management capability c802h c802h c802h c802h ro a4?a7h pmcs pci power management control and status 00000000h 00000000h 00000000h 00000000h r/w, ro d8?dbh mpc miscellaneous port configuration 00110000h 00110000h 00110000h 00110000h r/w dc?dfh smscs smi/sci status register 00000000h 00000000h 00000000h 00000000h r/wc 100?103h vch virtual channel capability header 18010002h 18010002h 18010002h 18010002h ro 108?10bh vcap2 virtual channel capability 2 00000001h 00000001h 00000001h 00000001h ro table 19-1. pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3) (sheet 2 of 3) offset mnemonic register name function 0 default function 1 default function 2 default function 3 default type
intel ? i/o controller hub 6 (ich6) family datasheet 677 pci express* configuration registers 10c? 10dh pvc port virtual channel control 0000h 0000h 0000h 0000h r/w 10e? 10fh pvs port virtual channel status 0000h 0000h 0000h 0000h ro 110?113h v0cap virtual channel 0 resource capability 00000001h 00000001h 00000001h 00000001h ro 114?117h v0ctl virtual channel 0 resource control 800000ffh 800000ffh 800000ffh 800000ffh r/w, ro 11a?11bh v0sts virtual channel 0 resource status 0000h 0000h 0000h 0000h ro 144?147h ues uncorrectable error status see bit description see bit description see bit description see bit description r/wc, ro 148?14bh uem uncorrectable error mask 00000000h 00000000h 00000000h 00000000h r/wo, ro 14c? 14fh uev uncorrectable error severity 00060011h 00060011h 00060011h 00060011h ro 150?153h ces correctable error status 00000000h 00000000h 00000000h 00000000h r/wc 154?157h cem correctable error mask 00000000h 00000000h 00000000h 00000000h r/wo 158?15bh aecc advanced error capabilities and control 00000000h 00000000h 00000000h 00000000h ro 170?173h res root error status 00000000h 00000000h 00000000h 00000000h r/wc, ro 180?183h rctcl root complex topology capability list 00010005h 00010005h 00010005h 00010005h ro 184?187h esd element self description see bit description see bit description see bit description see bit description ro 190?193h uld upstream link description 00000001h 00000001h 00000001h 00000001h ro 198?19fh ulba upstream link base address see bit description see bit description see bit description see bit description ro 314h pciecr1 pci express configuration register 1 00c4b0dbh 00c4b0dbh 00c4b0dbh 00c4b0dbh r/w 318h pciecr2 pci express configuration register 2 0a200000h 0a200000h 0a200000h 0a200000h r/w table 19-1. pci express* configuration registers address map (pci express?d28:f0/f1/f2/f3) (sheet 3 of 3) offset mnemonic register name function 0 default function 1 default function 2 default function 3 default type
678 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.1 vid?vendor identification register (pci express?d28:f0/f1/f2/f3) address offset: 00 ? 01h attribute: ro default value: 8086h size: 16 bits 19.1.2 did?device identification register (pci express?d28:f0/f1/f2/f3) address offset: 02?03h attribute: ro default value: port 1= 2660h size: 16 bits port 2= 2662h port 3= 2664h port 4= 2666h bit description 15:0 vendor id ? ro. this is a 16-bit value assigned to intel bit description 15:0 device id ? ro.
intel ? i/o controller hub 6 (ich6) family datasheet 679 pci express* configuration registers 19.1.3 pcicmd?pci command register (pci express?d28:f0/f1/f2/f3) address offset: 04?05h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 interrupt disable ? r/w. this disables pin-based intx # interrupts on enabled hot-plug and power management events. this bit has no effect on msi operation. 0 = internal intx# messages are generated if t here is an interrupt for hot-plug or power management and msi is not enabled. 1 = internal intx# messages will not be generated. this bit does not affect interrupt forwarding from devices connected to the root port. assert_intx and de-assert_intx messages will stil l be forwarded to the internal interrupt controllers if this bit is set. 9 fast back to back enable (fbe) ? reserved per the pci express* base specification . 8 serr# enable (see) ? r/w. 0 = disable. 1 = enables the root port to generate an serr# message when psts.sse is set. 7 wait cycle control (wcc) ? reserved per the pci express base specification . 6 parity error response (per) ? r/w. 0 = disable. 1 = indicates that the device is capable of reporti ng parity errors as a master on the backbone. 5 vga palette snoop (vps) ? reserved per the pci express* base specification . 4 postable memory write enable (pmwe) ? reserved per the pci express* base specification . 3 special cycle enable (sce) ? reserved per the pci express* base specification . 2 bus master enable (bme) ? r/w. 0 = disable. all cycles from the device are master aborted 1 = enable. allows the root port to forward cycle s onto the backbone from a pci express* device. 1 memory space enable (mse) ? r/w. 0 = disable. memory cycles within the range spec ified by the memory base and limit registers are master aborted on the backbone. 1 = enable. allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the pci express device. 0 i/o space enable (iose) ? r/w. this bit controls acce ss to the i/o space registers. 0 = disable. i/o cycles within th e range specified by the i/o base and limit registers are master aborted on the backbone. 1 = enable. allows i/o cycles within the range s pecified by the i/o base and limit registers can be forwarded to the pci express device.
680 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.4 pcists?pci status register (pci express?d28:f0/f1/f2/f3) address offset: 06 ? 07h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no parity error detected. 1 = set when the root port receives a command or data from the backbone with a parity error. this is set even if pcimd.per (d28:f0/f1/f2/f3:04, bit 6) is not set. 14 signaled system error (sse) ? r/wc. 0 = no system error signaled. 1 = set when the root port signals a system error to the internal serr# logic. 13 received master abort (rma) ? r/wc. 0 = root port has not received a completion with unsupported request status from the backbone. 1 = set when the root port receives a comple tion with unsupported request status from the backbone. 12 received target abort (rta) ? r/wc. 0 = root port has not received a completion with completer abort from the backbone. 1 = set when the root port receives a comple tion with completer abort from the backbone. 11 signaled target abort (sta) ? r/wc. 0 = no target abort received. 1 = set whenever the root port forwards a target abort received from the downstream device onto the backbone. 10:9 devsel# timing status (dev_sts) ? reserved per the pci express* base specification . 8 master data parity error detected (dped) ? r/wc. 0 = no data parity error received. 1 = set when the root port receives a completion with a data parity error on the backbone and pcimd.per (d28:f0/f1/f2/f 3:04, bit 6) is set. 7 fast back to back capable (fb2bc) ? reserved per the pci express* base specification . 6 reserved 5 66 mhz capable ? reserved per the pci express* base specification . 4 capabilities list ? ro. hardwi red to 1. indicates the presence of a capabilities list. 3 interrupt status ? ro. indicates status of hot-plug and power management interrupts on the root port that result in intx# message generation. 0 = interrupt is de-asserted. 1 = interrupt is asserted. this bit is not set if msi is enabled. if msi is not enabled, this bit is set regardless of the state of pcicmd.interrupt disable bit (d28:f0/f1/f2/f3:04h:bit 10). 2:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 681 pci express* configuration registers 19.1.5 rid?revision id entification register (pci express?d28:f0/f1/f2/f3) offset address: 08h attribute: ro default value: see bit description size: 8 bits 19.1.6 pi?programming interface register (pci express?d28:f0/f1/f2/f3) address offset: 09h attribute: ro default value: 00h size: 8 bits 19.1.7 scc?sub class code register (pci express?d28:f0/f1/f2/f3) address offset: 0ah attribute: ro default value: 04h size: 8 bits 19.1.8 bcc?base class code register (pci express?d28:f0/f1/f2/f3) address offset: 0bh attribute: ro default value: 06h size: 8 bits bit description 7:0 revision id ? ro. refer to the intel? ich6 family datasheet specification update for the value of the revision id register bit description 7:0 programming interface ? ro. 00h = no specific register le vel programming interface defined. bit description 7:0 sub class code (scc) ? ro. 04h = pci-to-pci bridge. bit description 7:0 base class code (bcc) ? ro. 06h = indicates the device is a bridge device.
682 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.9 cls?cache line size register (pci express?d28:f0/f1/f2/f3) address offset: 0ch attribute: r/w default value: 00h size: 8 bits 19.1.10 plt?primary latency timer register (pci express?d28:f0/f1/f2/f3) address offset: 0dh attribute: ro default value: 00h size: 8 bits 19.1.11 headtyp?header type register (pci express?d28:f0/f1/f2/f3) address offset: 0eh attribute: ro default value: 81h size: 8 bits 19.1.12 bnum?bus number register (pci express?d28:f0/f1/f2/f3) address offset: 18?1ah attribute: r/w default value: 000000h size: 24 bits bit description 7:0 base class code (bcc) ? r/w. this is read/ write but contains no functionality, per the pci* express base specification . bit description 7:3 latency count. reserved per the pci express* base specification. 2:0 reserved bit description 7 multi-function device ? ro. 0 = single-function device. 1 = multi-function device. 6:0 configuration layout. hardwired to 01h, which indicates a pci-to-pci bridge. bit description 23:16 subordinate bus number (sbbn) ? r/w. indicates the highest pci bus number below the bridge. 15:8 secondary bus number (scbn) ? r/w. indicates the bus number the port. 7:0 primary bus number (pbn) ? r/w. indicates the bus number of the backbone.
intel ? i/o controller hub 6 (ich6) family datasheet 683 pci express* configuration registers 19.1.13 iobl?i/o base and limit register (pci express?d28:f0/f1/f2/f3) address offset: 1c?1dh attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:12 i/o limit address (iola) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to fffh. 11:8 i/o limit address capability (i olc) ? r/o. indicates that the bridge does not support 32-bit i/o addressing. 7:4 i/o base address (ioba) ? r/w. i/o base bits corresponding to address lines 15:12 for 4-kb alignment. bits 11:0 are assumed to be padded to 000h. 3:0 i/o base address capability (iobc) ? r/o. indi cates that the bridge does not support 32-bit i/o addressing.
684 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.14 ssts?secondar y status register (pci express?d28:f0/f1/f2/f3) address offset: 1e? 1fh attribute: r/wc default value: 0000h size: 16 bits bit description 15 detected parity error (dpe) ? r/wc. 0 = no error. 1 = the port received a poisoned tlp. 14 received system error (rse) ? r/wc. 0 = no error. 1 = the port received an err_fatal or err_nonfatal message from the device. 13 received master abort (rma) ? r/wc. 0 = unsupported request not received. 1 = the port received a completion with ?unsup ported request? status from the device. 12 received target abort (rta) ? r/wc. 0 = completion abort not received. 1 = the port received a completion with ?com pletion abort? status from the device. 11 signaled target abort (sta) ? r/wc. 0 = completion abort not sent. 1 = the port generated a completion with ?completion abort? status to the device. 10:9 secondary devsel# timing stat us (sdts): reserved per pci express* base specification . 8 data parity error detected (dpd) ? r/wc. 0 = conditions below did not occur. 1 = set when the bctrl.pere (d28:fo/f1/f2/f3:3e: bi t 0) is set, and either of the following two conditions occurs: ? port receives completion marked poisoned. ? port poisons a write request to the secondary side. 7 secondary fast back to back capable (sfbc): reserved per pci express* base specification . 6reserved 5 secondary 66 mhz capable (sc66): reserved per pci express* base specification . 4:0 reserved
intel ? i/o controller hub 6 (ich6) family datasheet 685 pci express* configuration registers 19.1.15 mbl?memory base and limit register (pci express?d28:f0/f1/f2/f3) address offset: 20?23h attribute: r/w default value: 00000000h size: 32 bits accesses that are within the ranges specified in this register will be sent to the attached device if cmd.mse (d28:f0/f1/f2/f3:04:bit 1) is set. acce sses from the attached device that are outside the ranges specified will be forwarded to the backbone if cmd.bme (d28:f0/f1/f2/f3:04:bit 2) is set. the comparison performed is mb ad[31:20] ml. 19.1.16 pmbl?prefetchable memo ry base and limit register (pci express?d28:f0/f1/f2/f3) address offset: 24?27h attribute: r/w, ro default value: 00010001h size: 32 bits accesses that are within th e ranges specified in this register wi ll be sent to the device if cmd.mse (d28:f0/f1/f2/f3;04, bit 1) is set. accesses from the device that are outside the ranges specified will be forwarded to the backbone if cmd. bme (d28:f0/f1/f2/f3;04, bit 2) is set. the comparison performed is pmbu32:pmb ad[63:32]:ad[31:20] pmlu32:pml. bit description 31:20 memory limit (ml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb aligned value of the range. 19:16 reserved 15:4 memory base (mb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb aligned value of the range. 3:0 reserved bit description 31:20 prefetchable memory limit (pml) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the upper 1-mb aligned value of the range. 19:16 64-bit indicator (i64l) ? ro. this field indicates support for 64-bit addressing 15:4 prefetchable memory base (pmb) ? r/w. these bits are compared with bits 31:20 of the incoming address to determine the lower 1-mb aligned value of the range. 3:0 64-bit indicator (i64b) ? ro. this fi eld indicates support for 64-bit addressing
686 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.17 pmbu32?prefetchable memory base upper 32 bits register (pci expr ess?d28:f0/f1/f2/f3) address offset: 28?2bh attribute: r/w default value: 00000000h size: 32 bits 19.1.18 pmlu32?prefetchable memory limit upper 32 bits register (pci expr ess?d28:f0/f1/f2/f3) address offset: 2c?2fh attribute: r/w default value: 00000000h size: 32 bits 19.1.19 capp?capabilities list pointer register (pci express?d28:f0/f1/f2/f3) address offset: 34h attribute: r0 default value: 40h size: 8 bits 19.1.20 intr?interrupt information register (pci express?d28:f0/f1/f2/f3) address offset: 3c?3d h attribute: r/w, ro default value: see bit description size: 16 bits bit description 31:0 prefetchable memory base upper portion (pmbu) ? r/w. upper 32-bits of the prefetchable address base. bit description 31:0 prefetchable memory limit upper portion (pmlu) ? r/w. upper 32-bits of the prefetchable address limit. bit description 7:0 capabilities pointer (ptr) ? ro. this field indicates that the pointer for the first entry in the capabilities list is at 40h in configuration space. bit description 15:8 interrupt pin (ipin) ? ro. this field indicates the interrupt pi n driven by the root port. at reset, this register takes on the following val ues, which reflect the reset state of the d28ip register in chipset configuration space: note: the value that is programmed into d28ip is always reflected in this register. 7:0 interrupt line (iline) ? r/w. default = 00h. software written va lue to indicate which interrupt line (vector) the interrupt is connected to. no hardware action is taken on this register. port reset value 1 d28ip.p1ip 2 d28ip.p2ip 3 d28ip.p3ip 4 d28ip.p4ip
intel ? i/o controller hub 6 (ich6) family datasheet 687 pci express* configuration registers 19.1.21 bctrl?bridge control register (pci express?d28:f0/f1/f2/f3) address offset: 3e?3fh attribute: r/w default value: 0000h size: 16 bits bit description 15:12 reserved 11 discard timer serr# enable (dtse): reserved per pci express* base specification, revision 1.0a 10 discard timer status (dts): reserved per pci express* base specification, revision 1.0a . 9 secondary discard timer (sdt): reserved per pci express* base specification, revision 1.0a . 8 primary discard timer (pdt): reserved per pci express* base specification, revision 1.0a . 7 fast back to back enable (fbe): reserved per pci express* base specification, revision 1.0a . 6 secondary bus reset (sbr) ? r/w. triggers a hot reset on the pci express* port. 5 master abort mode (mam): rese rved per express specification. 4 vga 16-bit decode (v16) ? r/w. 0 = vga range is enabled. 1 = the i/o aliases of the vga range (see bctr l:ve definition below), are not enabled, and only the base i/o ranges can be decoded 3 vga enable (ve) ? r/w. 0 = the ranges below will not be clai med off the backbone by the root port. 1 = the following ranges will be cl aimed off the backbone by the root port: ? memory ranges a0000h?bffffh ? i/o ranges 3b0h ? 3bbh and 3c0h ? 3dfh, and all al iases of bits 15:10 in any combination of 1s 2 isa enable (ie) ? r/w. this bit only applies to i/o addr esses that are enabled by the i/o base and i/o limit registers and are in the first 64 kb of pci i/o space. 0 = the root port will not block any forw arding from the backbone as described below. 1 = the root port will block any forwarding from the backbone to the device of i/o transactions addressing the last 768 bytes in each 1-kb block (offsets 100h to 3ffh). 1 serr# enable (se) ? r/w. 0 = the messages described below are not forwarded to the backbone. 1 = err_cor, err_nonfatal, and err_fatal messages received are forwarded to the backbone. 0 parity error response enable (pere) ? r/w. when set, 0 = poisoned write tlps and completions indicati ng poisoned tlps will not set the ssts.dpd (d28:f0/f1/f2/f3:1e, bit 8). 1 = poisoned write tlps and completions indi cating poisoned tlps will set the ssts.dpd (d28:f0/f1/f2/f3:1e, bit 8).
688 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.22 clist?capabilities list register (pci express?d28:f0/f1/f2/f3) address offset: 40?41h attribute: ro default value: 8010h size: 16 bits 19.1.23 xcap?pci express* capabilities register (pci express?d28:f0/f1/f2/f3) address offset: 42?43h attribute: r/wo, ro default value: 0041h size: 16 bits bit description 15:8 next capability (next) ? ro. value of 80h indicates the location of the next pointer. 7:0 capability id (cid) ? ro. this field indicates this is a pci express* capability. bit description 15:14 reserved 13:9 interrupt message number (imn) ? ro. the intel ? ich6 does not have multiple msi interrupt numbers. 8 slot implemented (si) ? r/wo. this field indicates whether the root port is connected to a slot. slot support is platform specific. bios programs this field, and it is maintained until a platform reset. 7:4 device / port type (dt) ? ro. this field indicates this is a pci express* root port. 3:0 capability version (cv) ? ro. this field indicates pci express 1.0.
intel ? i/o controller hub 6 (ich6) family datasheet 689 pci express* configuration registers 19.1.24 dcap?device ca pabilities register (pci express?d28:f0/f1/f2/f3) address offset: 44?47h attribute: ro default value: 00000fe0h size: 32 bits bit description 31:28 reserved 27:26 captured slot power limit scale (csps) ? ro. not supported. 25:18 captured slot power limit value (cspv) ? ro. not supported. 17:15 reserved 14 power indicator present (pip) ? ro. this bit indicates no power indicator is present on the root port. 13 attention indicator present (aip) ? ro. this bit indicates no att ention indicator is present on the root port. 12 attention button present (abp) ? ro. this bit indicates no attent ion button is present on the root port. 11:9 endpoint l1 acceptable latency (e1al) ? ro. this field indicates more than 4 s. this field essentially has no meaning for root ports since root ports are not endpoints. 8:6 endpoint l0 acceptable latency (e0al) ? ro. this field indicates more than 64 s. this field essentially has no meaning for root ports since root ports are not endpoints. 5 extended tag field supported (etfs) ? ro. this bit indicates that 8-bit tag fields are supported. 4:3 phantom functions supported (pfs) ? ro. no phantom functions supported. 2:0 max payload size supported (mps) ? ro. this field indicate s the maximum payload size supported is 128b.
690 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.25 dctl?device control register (pci express?d28:f0/f1/f2/f3) address offset: 48?49h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15 reserved 14:12 max read request size (mrrs) ? ro. hardwired to 0. 11 enable no snoop (ens) ? ro. not supported. the root port will never issue non-snoop requests. 10 aux power pm enable (apme) ? r/w. the os will set this bit to 1 if the device connected has detected aux power. it has no effect on the root port otherwise. 9 phantom functions enable (pfe) ? ro. not supported. 8 extended tag field enable (etfe) ? ro. not supported. 7:5 max payload size (mps) ? r/w. the root port only supports 128-b payloads, regardless of the programming of this field. 4 enable relaxed ordering (ero) ? ro. not supported. 3 unsupported request reporting enable (ure) ? r/w. 0 = the root port will ignore unsupported request errors. 1 = the root port will generate errors when detecting an unsupported request. 2 fatal error reporting enable (fee) ? r/w. 0 = the root port will ignore fatal errors. 1 = the root port will generate errors when detecting a fatal error. 1 non-fatal error reporting enable (nfe) ? r/w. 0 = the root port will ignore non-fatal errors. 1 = the root port will generate errors when detecting a non-fatal error. 0 correctable error reporting enable (cee) ? r/w. 0 = the root port will ignore correctable errors. 1 = the root port will generate errors when detecting a correctable error.
intel ? i/o controller hub 6 (ich6) family datasheet 691 pci express* configuration registers 19.1.26 dsts?device status register (pci express?d28:f0/f1/f2/f3) address offset: 4a?4b h attribute: r/wc, ro default value: 0010h size: 16 bits bit description 15:6 reserved 5 transactions pending (tdp) ? ro. this bit has no meaning fo r the root port since only one transaction may be pending to the intel ? ich6, so a read of this bit cannot occur until it has already returned to 0. 4 aux power detected (apd) ? ro. the root port contains aux power for wakeup. 3 unsupported request detected (urd) ? r/wc. indicates an unsupported request was detected. 2 fatal error detected (fed) ? r/wc. this bit indicates a fatal error was detected. 0 = fatal has not occurred. 1 = a fatal error occurred from a data link protocol error, link training error, buffer overflow, or malformed tlp. 1 non-fatal error detected (nfed) ? r/wc. this bit indicates a non-fatal error was detected. 0 = non-fatal has not occurred. 1 = a non-fatal error occurred from a poisoned tlp, unexpected completions, unsupported requests, completer abort, or completer timeout. 0 correctable error detected (ced) ? r/wc. this bit indicates a correctable error was detected. 0 = correctable has not occurred. 1 = the port received an internal correctable error from receiver errors / framing errors, tlp crc error, dllp crc error, replay num rollover, replay timeout.
692 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.27 lcap?link capabilities register (pci express?d28:f0/f1/f2/f3) address offset: 4c ? 4fh attribute: r/w, ro default value: see bit description size: 32 bits bit description 31:24 port number (pn) ? ro. this field indicates the port num ber for the root port. this value is different for each implemented port: 23:18 reserved 17:15 l1 exit latency (el1) ? ro. set to 010b to indicate an exit latency of 2 s to 4 s. 14:12 l0s exit latency (el0) ? ro. this field indicates as exit latency based upon common-clock configuration. note: lclt.ccc is at d28:f0/f1/f2/f3:50h:bit 6 11:10 active state link pm support (apms) ? r/wo. this field indicates w hat level of active state link power management is supported on the root port. value fixed at 11b. 9:4 maximum link width (mlw) ? ro. for the root ports, several values can be taken, based upon the value of the chipset configuration register fiel d rpc.pc (chipset configuration registers:offset 0224h:bits1:0): 3:0 maximum link speed (mls) ? ro. set to 1h to indicate the link speed is 2.5 gb/s. function port # value of pn field d28:f0 1 01h d28:f1 2 02h d28:f2 3 03h d28:f3 4 04h lclt.ccc value of el0 (these bits) 0 mpc.ucel (d28:f0/f1/f2/f3:d8h:bits20:18) 1 mpc.ccel (d28:f0/f1/f2/f3:d8h:bits17:15) bits definition 00b neither l0s nor l1 are supported 01b l0s entry supported 10b l1 entry supported 11b both l0s and l1 entry supported value of mlw field port # rpc.pc=00b rpc.pc=11b 1 01h 04h 2 01h 01h 3 01h 01h 4 01h 01h
intel ? i/o controller hub 6 (ich6) family datasheet 693 pci express* configuration registers 19.1.28 lctl?link control register (pci express?d28:f0/f1/f2/f3) address offset: 50?51h attribute: r/w, wo, ro default value: 0000h size: 16 bits bit description 15:8 reserved 7 extended synch (es) ? r/w. 0 = extended synch disabled. 1 = forces extended transmission of fts ordered sets in fts and extra ts2 at exit from l1 prior to entering l0. 6 common clock configuration (ccc) ? r/w. 0 = the ich6 and device are not using a common reference clock. 1 = the ich6 and device are operating with a distributed common reference clock. 5 retrain link (rl) ? wo. 0 = this bit always returns 0 when read. 1 = the root port will train its downstream link. note: software uses lsts.lt (d28:f0/f1/f2/f3:52, bit 11) to check the status of training. 4 link disable (ld) ? r/w. 0 = link enabled. 1 = the root port will disable the link. 3 read completion boundary control (rcbc) ? ro. this bit indicates the read completion boundary is 64 bytes. 2reserved 1:0 active state link pm control (apmc) ? r/w. this field indicates whether the root port should enter l0s or l1 or both. bits definition 00b disabled 01b l0s entry is enabled 10b l1 entry is enabled 11b l0s and l1 entry enabled
694 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.29 lsts?link status register (pci express?d28:f0/f1/f2/f3) address offset: 52?53h attribute: ro default value: see bit description size: 16 bits bit description 15:13 reserved 12 slot clock configuration (scc) ? ro. set to 1b to indicate that the intel ? ich6 uses the same reference clock as on the platform and does not generate its own clock. 11 link training (lt) ? ro. default value is 0b. 0 = link training completed. 1 = link training is occurring. 10 link training error (lte ) ? ro. not supported. set value is 0b. 9:4 negotiated link width (nlw) ? ro. this field indicates the negotiated width of the given pci express* link. the contents of this nlw field is undefined if the link has not successfully trained. note: 000001b = x1 link width, 0001000 = x4 link width (enterprise applications only) 3:0 link speed (ls) ? ro. this field indicates the negotiated link speed of the given pci express* link. 01h = link is 2.5 gb/s. port # possible values 1 000001b, 000010b, 000100b 2 000001b 3 000001b 4 000001b
intel ? i/o controller hub 6 (ich6) family datasheet 695 pci express* configuration registers 19.1.30 slcap?slot capabilities register (pci express?d28:f0/f1/f2/f3) address offset: 54 ? 57h attribute: r/wo, ro default value: 00000060h size: 32 bits bit description 31:19 physical slot number (psn) ? r/wo. this is a value that is un ique to the slot number. bios sets this field and it remains set until a platform reset. 18:17 reserved 16:15 slot power limit scale (sls) ? r/wo. this field specifies the sc ale used for the slot power limit value. bios sets this field and it remains set until a platform reset. 14:7 slot power limit value (slv) ? r/wo. this field specifies the upper limit (in conjunction with sls value), on the upper limit on power supplied by the slot. the two val ues together indicate the amount of power in watts allowed for the slot. bios sets this field and it remains set until a platform reset. 6 hot plug capable (hpc) ? ro. 1b = indicates that hot-plug is supported. 5 hot plug surprise (hps) ? ro. 1b = indicates the device may be removed fr om the slot without prior notification. 4 power indicator present (pip) ? ro. 0b = indicates that a power indicator led is not present for this slot. 3 attention indicator present (aip) ? ro. 0b = indicates that an attention indica tor led is not present for this slot. 2 mrl sensor present (msp) ? ro. 0b = indicates that an mrl sensor is not present. 1 power controller present (pcp) ? ro. 0b = indicates that a power controller is not implemented for this slot. 0 attention button present (abp) ? ro. 0b = indicates that an attention button is not implemented for this slot.
696 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.31 slctl?slot control register (pci express?d28:f0/f1/f2/f3) address offset: 58 ? 59h attribute: r/w, ro default value: 0000h size: 16 bits bit description 15:11 reserved 10 power controller control (pcc) ? ro.this bit has no meaning for module based hot-plug. 9:8 power indicator control (pic) ? r/w. when read, the current state of the power indicator is returned. when written, the appropriate power_indicator_* messages are sent. defined encodings are: 7:6 attention indicator control (aic) ? r/w. when read, the current state of the attention indicator is returned. when written, the appropriate attention_indicator_* messages are sent. defined encodings are: 5 hot plug interrupt enable (hpe) ? r/w. 0 = hot plug interrupts based on hot-plug events is disabled. 1 = enables generation of a hot-plug interrupt on enabled hot-plug events. 4 command completed interrupt enable (cce) ? r/w. 0 = hot plug interrupts based on command completions is disabled. 1 = enables the generation of a hot-plug interru pt when a command is completed by the hot-plug controller. 3 presence detect changed enable (pde) ? r/w. 0 = hot plug interrupts based on pres ence detect logic c hanges is disabled. 1 = enables the generation of a hot-plug interru pt or wake message when the presence detect logic changes state. 2 mrl sensor changed enable (mse) ? r/w. mse not supported. 1 power fault detected enable (pfe) ? r/w. pfe not supported. 0 attention button pressed enable (abe) ? r/w. when set, enables the generation of a hot-plug interrupt when the attention button is pressed. 0 = hot plug interrupts based on the att ention button being pressed is disabled. 1 = enables the generation of a hot-plug inte rrupt when the attention button is pressed. bits definition 00b reserved 01b on 10b blink 11b off bits definition 00b reserved 01b on 10b blink 11b off
intel ? i/o controller hub 6 (ich6) family datasheet 697 pci express* configuration registers 19.1.32 slsts?slot status register (pci express?d28:f0/f1/f2/f3) address offset: 5a ? 5bh attribute: r/wc, ro default value: 0000h size: 16 bits bit description 15:7 reserved 6 presence detect state (pds) ? ro. if xcap.si (d28:f0/f1/f2/f3:42 h:bit 8) is set (indicating that this root port spawns a slot), then this bit: 0 = indicates the slot is empty. 1 = indicates the slot has a device connected. otherwise, if xcap.si is cleared, this bit is always set (1). 5 mrl sensor state (ms) ? reserved as the mrl sensor is not implemented. 4 command completed (cc) ? r/wc. 0 = issued command not completed. 1 = the hot-plug controller completed an issued command. this is set when the last message of a command is sent and indicates that software c an write a new command to the slot controller. 3 presence detect changed (pdc) ? r/wc. 0 = no change in the pds bit. 1 = the pds bit changed states. 2 mrl sensor changed (msc) ? reserved as the mrl sensor is not implemented. 1 power fault detected (pfd) ? reserved as a power controller is not implemented. 0 attention button pressed (abp) ? r/wc. 0 = the attention button has not been pressed. 1 = the attention button is pressed.
698 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.33 rctl?root control register (pci express?d28:f0/f1/f2/f3) address offset: 5c ? 5dh attribute: r/w default value: 0000h size: 16 bits 19.1.34 rsts?root status register (pci express?d28:f0/f1/f2/f3) address offset: 60 ? 63h attribute: r/wc, ro default value: 00000000h size: 32 bits bit description 15:4 reserved 3 pme interrupt enable (pie) ? r/w. 0 = interrupt generation disabled. 1 = interrupt generation enabled when pcists.inerrupt status (d28:f0/f1/f2/f3:60h, bit-16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set with rsts.is already set). 2 system error on fatal error enable (sfe) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d2 8:f0/f1/f2/f3:04, bit 8) is set, if a fatal error is reported by any of the devices in the hier archy of this root port, including fatal errors in this root port. 1 system error on non-fa tal error enable (sne) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d28:f0/f1/f2/f3:04, bi t 8) is set, if a non- fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. 0 system error on correctable error enable (sce) ? r/w. 0 = an serr# will not be generated. 1 = an serr# will be generated, assuming cmd.see (d28:f0/f1/f2/f3:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. bit description 31:18 reserved 17 pme pending (pp) ? ro. 0 = when the original pme is cleared by softwa re, it will be set again, the requestor id will be updated, and this bit will be cleared. 1 = indicates another pme is pending when the pme status bit is set. 16 pme status (ps) ? r/wc. 0 = pme was not asserted. 1 = indicates that pme was asserted by the r equestor id in rid. subsequent pmes are kept pending until this bit is cleared. 15:0 pme requestor id (rid) ? ro. indicates the pci requestor id of the last pme requestor. valid only when ps is set.
intel ? i/o controller hub 6 (ich6) family datasheet 699 pci express* configuration registers 19.1.35 mid?message signaled in terrupt identifiers register (pci express?d28:f0/f1/f2/f3) address offset: 80?81h attribute: ro default value: 9005h size: 16 bits 19.1.36 mc?message signaled inte rrupt message control register (pci express?d28:f0/f1/f2/f3) address offset: 82?83h attribute: r/w, ro default value: 0000h size: 16 bits 19.1.37 ma?message signaled interrupt message address register (pci express?d28:f0/f1/f2/f3) address offset: 84 ? 87h attribute: r/w default value: 00000000h size: 32 bits bit description 15:8 next pointer (next) ? ro. this field indicates the loca tion of the next pointer in the list. 7:0 capability id (cid) ? ro. capabilities id indicates msi. bit description 15:8 reserved 7 64 bit address capable (c64) ? ro. capable of generating a 32-bit message only. 6:4 multiple message enable (mme) ? r/w. these bits are r/w for software compatibility, but only one message is ever sent by the root port. 3:1 multiple message capable (mmc) ? ro. only one message is required. 0 msi enable (msie) ? r/w. 0 = msi is disabled. 1 = msi is enabled and traditional interrupt pins are not used to generate interrupts. note: cmd.bme (d28:f0/f1/f2/f3:04h:bit 2) must be set for an msi to be generated. if cmd.bme is cleared, and this bit is set, no interrupts (not even pin based) are generated. bit description 31:2 address (addr) ? r/w. lower 32 bits of the system specified message address, always dw aligned. 1:0 reserved
700 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.38 md?message signaled in terrupt message data register (pci express?d28:f0/f1/f2/f3) address offset: 88 ? 89h attribute: r/w default value: 0000h size: 16 bits 19.1.39 svcap?subsystem ve ndor capability register (pci express?d28:f0/f1/f2/f3) address offset: 90 ? 91h attribute: ro default value: a00dh size: 16 bits 19.1.40 svid?subsystem vendor identification register (pci express?d28:f0/f1/f2/f3) address offset: 94 ? 97h attribute: r/wo default value: 00000000h size: 32 bits 19.1.41 pmcap?power management capability register (pci express?d28:f0/f1/f2/f3) address offset: a0 ? a1h attribute: ro default value: 0001h size: 16 bits bit description 15:0 data (data) ? r/w. this 16-bit field is programmed by system software if msi is enabled. its content is driven onto the lower word (pci ad[15: 0]) during the data phase of the msi memory write transaction. bit description 15:8 next capability (next) ? ro. this field indicates the loca tion of the next pointer in the list. 7:0 capability identifier (cid) ? ro. value of 0dh indicates this is a pci bridge subsystem vendor capability. bit description 31:16 subsystem identifier (sid) ? r/wo. this field indicates the s ubsystem as identified by the vendor. this field is write once and is locked down until a bridge reset occurs (not the pci bus reset). 15:0 subsystem vendor identifier (svid) ? r/wo. this field indicates the manufacturer of the subsystem. this field is write once and is locked down until a br idge reset occurs (not the pci bus reset). bit description 15:8 next capability (next) ? ro. this field indicates this is the last item in the list. 7:0 capability identifier (cid) ? ro. value of 01h indicates th is is a pci power management capability.
intel ? i/o controller hub 6 (ich6) family datasheet 701 pci express* configuration registers 19.1.42 pmc?pci power manage ment capabilities register (pci express?d28:f0/f1/f2/f3) address offset: a2 ? a3h attribute: ro default value: c802h size: 16 bits bit description 15:11 pme_support (pmes) ? ro. this field indi cates pme# is supported for states d0, d3 hot and d3 cold . the root port does not generate pme#, but reporting that it does is necessary for some legacy operating systems to enable pme# in devices connected behind this root port. 10 d2_support (d2s) ? ro. the d2 state is not supported. 9 d1_support (d1s) ? ro the d1 state is not supported. 8:6 aux_current (ac) ? ro. reports 375 ma maximum suspend well current required when in the d3 cold state. 5 device specific initialization (dsi) ? ro. this bit indicates that no device-s pecific initialization is required. 4reserved 3 pme clock (pmec) ? ro. this bit indicates t hat pci clock is not required to generate pme#. 2:0 version (vs) ? ro. this field indicates support for revision 1.1 of the pci power management specification .
702 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.43 pmcs?pci power mana gement control and status register (pci expr ess?d28:f0/f1/f2/f3) address offset: a4 ? a7h attribute: r/w, ro default value: 00000000h size: 32 bits bit description 31:24 reserved 23 bus power / clock control enable (bpce) ? reserved per pci express* base specification, revision 1.0a . 22 b2/b3 support (b23s) ? reserved per pci express* base specification, revision 1.0a . 21:16 reserved 15 pme status (pmes) ? ro. this bit indicates a pme wa s received on the downstream link. 14:9 reserved 8 pme enable (pmee) ? r/w. this bit indicates pme is enabled. the root port takes no action on this bit, but it must be r/w for some legac y operating systems to enable pme# on devices connected to this root port. this bit is sticky and resides in the resume well . the reset for this bit is rsmrst# which is not asserted during a warm reset. 7:2 reserved 1:0 power state (ps) ? r/w. this field is used both to determine the current power state of the root port and to set a new power state. the values are: 00 = d0 state 11 = d3 hot state note: when in the d3 hot state, the controller?s configuration space is available, but the i/o and memory spaces are not. type 1 configuration cy cles are also not accepted. interrupts are not required to be blocked as software will dis able interrupts prior to placing the port into d3 hot . if software attempts to write a ?10? or ?01? to these bits, the write will be ignored.
intel ? i/o controller hub 6 (ich6) family datasheet 703 pci express* configuration registers 19.1.44 mpc?miscellaneous po rt configuration register (pci express?d28:f0/f1/f2/f3) address offset: d8 ? dbh attribute: r/w default value: 00110000h size: 32 bits bit description 31 power management sci enable (pmce) ? r/w. 0 = sci generation based on a power management event is disabled. 1 = enables the root port to generate sci whenev er a power management event is detected. 30 hot plug sci enable (hpce) ? r/w. 0 = sci generation based on a hot-plug event is disabled. 1 = enables the root port to generate sci whenever a hot-plug event is detected. 29:21 reserved 20:18 unique clock exit latency (ucel) ? r/w. this value represents th e l0s exit latency for unique- clock configurations (lctl.ccc = 0) (d28:f0/f1/f2/f3: offset 50h:bit 6). it defaults to 512 ns to less than 1 s, but may be overridden by bios. 17:15 common clock exit latency (ccel) ? r/w. this value represents the l0s exit latency for common-clock configurati ons (lctl.ccc = 1) (d28:f0/f1/f2/f3:offset 50h:bit 6). it defaults to 128 ns to less than 256 ns, but may be overridden by bios. 14:8 reserved 7 port i/oxapic enable (pae) ? r/w. 0 = hole is disabled. 1 = a range is opened through the bridge fo r the following memory addresses: 6:2 reserved 1 hot plug smi enable (hpme) ? r/w. 0 = smi generation based on a hot-plug event is disabled. 1 = enables the root port to generate smi whenever a hot-plug event is detected. 0 power management smi enable (pmme) ? r/w. 0 = smi generation based on a power management event is disabled. 1 = enables the root port to generate smi whenever a power management event is detected. port # address 1 fec1_0000h ? fec1_7fffh 2 fec1_8000h ? fec1_ffffh 3 fec2_0000h ? fec2_7fffh 4 fec2_8000h ? fec2_ffffh
704 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.45 smscs?smi/sci status register (pci express?d28:f0/f1/f2/f3) address offset: dc ? dfh attribute: r/wc default value: 00000000h size: 32 bits 19.1.46 vch?virtual channel ca pability header register (pci express?d28:f0/f1/f2/f3) address offset: 100 ? 103h attribute: ro default value: 18010002h size: 32 bits 19.1.47 vcap2?virtual channel capability 2 register (pci express?d28:f0/f1/f2/f3) address offset: 108 ? 10bh attribute: ro default value: 00000001h size: 32 bits bit description 31 power management sci status (pmcs) ? r/wc. this bit is set if the hot-plug controller needs to generate an interrupt, and this interrupt has been routed to generate an sci. 30 hot plug sci status (hpcs) ? r/wc. this bit is set if the hot-plug controller needs to generate an interrupt, and has this interrupt been routed to generate an sci. 29:4 reserved 3 hot plug command completed smi status (hpccm) ? r/wc. this bit is set when slsts.cc (d28:f0/f1/f2/f3:5a, bit 4) transitions from 0 to 1, and mpc.hpme (d28:f0/f1/f2/f3:d8, bit 1) is set. when this bit is set, an smi# will be generated. 2 hot plug attention button smi status (hpabm) ? r/wc. this bit is set when slsts.abp (d28:f0/f1/f2/f3:5a, bit 0) transitions from 0 to 1, and mpc.hpme (d28:f0/f1/f2/f3:d8, bit 1) is set. when this bit is set, an smi# will be generated. 1 hot plug presence detect smi status (hppdm) ? r/wc. this bit is set when slsts.pdc (d28:f0/f1/f2/f3:5a, bit 3) transitions from 0 to 1, and mpc.hpme (d28:f0/f1/f2/f3:d8, bit 1) is set. when this bit is set, an smi# will be generated. 0 power management smi status (pmms) ? r/wc. this bit is set when rsts.ps (d28:f0/f1/f2/ f3:60, bit 16) transitions from 0 to ?, and mpc.pmme (d28:f0/f1/f2/f3:d8, bit 1) is set. bit description 31:20 next capability offset (nco) ? ro. this field indicates the next item in the list. 19:16 capability version (cv) ? ro. this field indicates this is version 1 of the cap ability structure by the pci sig. 15:0 capability id (cid) ? ro. this field indicates this is the virtual channel capability item. bit description 31:24 vc arbitration table offset (ato) ? ro. this fi eld indicates that no table is present for vc arbitration since it is fixed. 23:0 reserved.
intel ? i/o controller hub 6 (ich6) family datasheet 705 pci express* configuration registers 19.1.48 pvc?port virtual ch annel control register (pci express?d28:f0/f1/f2/f3) address offset: 10c ? 10dh attribute: r/w default value: 0000h size: 16 bits 19.1.49 pvs ? port virtual channel status register (pci express?d28:f0/f1/f2/f3) address offset: 10e ? 10fh attribute: ro default value: 0000h size: 16 bits 19.1.50 v0cap ? virtual channel 0 resource capability register (pci express?d28:f0/f1/f2/f3) address offset: 110 ? 113h attribute: ro default value: 00000001h size: 32 bits bit description 15:4 reserved. 3:1 vc arbitration select (as) ? r/w. this field indicates which vc should be programmed in the vc arbitration table. the root port takes no action on the setting of this field sinc e there is no arbitration table. 0 load vc arbitration table (lat) ? r/w. this bit indicates that the table programmed should be loaded into the vc arbitration table. this bit always returns 0 when read. bit description 15:1 reserved. 0 vc arbitration table status (vas) ? ro. this bit indicates the coherency status of the vc arbitration table when it is being updated. this field is always 0 in the root port since there is no vc arbitration table. bit description 31:24 port arbitration table offset (at) ? ro. this vc implements no port arbitration table since the arbitration is fixed. 23 reserved. 22:16 maximum time slots (mts) ? ro. this vc implements fixed arbitration, and t herefore this field is not used. 15 reject snoop transactions (rts) ? ro. this vc must be able to take snoopable transactions. 14 advanced packet switching (aps) ? ro. this vc is capable of all transactions, not just advanced packet switching transactions. 13:8 reserved. 7:0 port arbitration capability (pac) ? ro. this field indicates that th is vc uses fixed port arbitration.
706 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.51 v0ctl ? virtual channe l 0 resource control register (pci express?d28:f0/f1/f2/f3) address offset: 114 ? 117h attribute: r/w, ro default value: 800000ffh size: 32 bits 19.1.52 v0sts ? virtual channel 0 resource status register (pci express?d28:f0/f1/f2/f3) address offset: 11a ? 11bh attribute: ro default value: 0000h size: 16 bits bit description 31 virtual channel enable (en) ? ro. always set to 1. virtual channel 0 cannot be disabled. 30:27 reserved. 26:24 virtual channel identifier (vcid) ? ro. indi cates the id to use fo r this virtual channel. 23:20 reserved. 19:17 port arbitration select (pas) ? r/w. this field indicates which port table is being programmed. the root complex takes no action on this setting since t he arbitration is fixed and there is no arbitration table. 16 load port arbitration table (lat) ? ro. the root port does not implement an arbitration table for this virtual channel. 15:8 reserved. 7:1 transaction class / virtual channel map (tvm) ? r/w. this field indicates which transaction classes are mapped to this virtual channel. when a bit is set, this tr ansaction class is mapped to the virtual channel. 0 reserved. transacti on class 0 must always mapped to vc0. bit transaction class 7 transaction class 7 6 transaction class 6 5 transaction class 5 4 transaction class 4 3 transaction class 3 2 transaction class 2 1 transaction class 1 0 transaction class 0 bit description 15:2 reserved. 1 vc negotiation pending (np) ? ro. 0 = negotiation is not pending. 1 = indicates the virtual channel is still being negot iated with ingress ports. 0 port arbitration tables status (ats). there is no po rt arbitration table for th is vc, so this bit is reserved as 0.
intel ? i/o controller hub 6 (ich6) family datasheet 707 pci express* configuration registers 19.1.53 ues ? uncorrectable error status register (pci express?d28:f0/f1/f2/f3) address offset: 144 ? 147h attribute: r/wc, ro default value: 00000000000x0xxx0x0x0000000x0000bsize:32 bits this register maintains its state through a platform reset. it loses its state upon suspend. bit description 31:21 reserved 20 unsupported request error status (ure) ? r/wc. this bit indicates an unsupported request was received. 19 ecrc error status (ee) ? ro. ecrc is not supported. 18 malformed tlp status (mt) ? r/wc. this bit indicates a malformed tlp was received. 17 receiver overflow status (ro) ? r/wc. this bit indicates a receiver overflow occurred. 16 unexpected completion status (uc) ? r/wc. this bit indicate s an unexpected completion was received. 15 completion abort status (ca) ? r/wc. this bit indicates a completer abort was received. 14 completion timeout status (ct) ? r/wc. this bit indicates a completion timed out. 13 flow control protocol error status (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp status (pt) ? r/wc. this bit indicates a poisoned tlp was received. 11:5 reserved 4 data link protocol error status (dlpe) ? r/wc. this bit indicates a data link protocol error occurred. 3:1 reserved 0 training error status (te) ? ro. training errors not supported.
708 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.54 uem ? uncorrectable error mask (pci express?d28:f0/f1/f2/f3) address offset: 148 ? 14bh attribute: r/wo, ro default value: 00000000h size: 32 bits when set, the corresponding error in the ues register is masked, a nd the logged error will cause no action. when cleared, the corr esponding error is enabled. bit description 31:21 reserved 20 unsupported request error mask (ure) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 19 ecrc error mask (ee) ? ro. ecrc is not supported. 18 malformed tlp mask (mt) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 17 receiver overflow mask (ro) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 16 unexpected completion mask (uc) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 15 completion abort mask (ca) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 14 completion timeout mask (ct) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 13 flow control protocol error mask (fcpe) ? ro . flow control protocol errors not supported. 12 poisoned tlp mask (pt) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 11:5 reserved 4 data link protocol error mask (dlpe) ? r/wo. 0 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is enabled. 1 = the corresponding error in the ues register (d28:f0/f1/f2/f3:144) is masked. 3:1 reserved 0 training error mask (te) ? ro . training errors not supported
intel ? i/o controller hub 6 (ich6) family datasheet 709 pci express* configuration registers 19.1.55 uev ? uncorrectable error severity (pci express?d28:f0/f1/f2/f3) address offset: 14c ? 14fh attribute: ro default value: 00060011h size: 32 bits bit description 31:21 reserved 20 unsupported request error severity (ure) ? ro. 0 = error considered non-fatal. (default) 1 = error is fatal. 19 ecrc error severity (ee) ? ro. ecrc is not supported. 18 malformed tlp severity (mt) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 17 receiver overflow severity (ro) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 16 unexpected completion severity (uc) ? ro. 0 = error considered non-fatal. (default) 1 = error is fatal. 15 completion abort severity (ca) ? ro. 0 = error considered non-fatal. (default) 1 = error is fatal. 14 completion timeout severity (ct) ? ro. 0 = error considered non-fatal. (default) 1 = error is fatal. 13 flow control protocol error severity (fcpe) ? ro. flow control protocol errors not supported. 12 poisoned tlp severity (pt) ? ro. 0 = error considered non-fatal. (default) 1 = error is fatal. 11:5 reserved 4 data link protocol error severity (dlpe) ? ro. 0 = error considered non-fatal. 1 = error is fatal. (default) 3:1 reserved 0 training error severity (te) ? ro. te is not supported.
710 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.56 ces ? correctable error status register (pci express?d28:f0/f1/f2/f3) address offset: 150 ? 153h attribute: r/wc default value: 00000000h size: 32 bits 19.1.57 cem ? correctable error mask register (pci express?d28:f0/f1/f2/f3) address offset: 154 ? 157h attribute: r/wo default value: 00000000h size: 32 bits when set, the corresponding error in the ces register is masked, and the logged error will cause no action. when cleared, the corr esponding error is enabled. bit description 31:13 reserved 12 replay timer timeout status (rtt) ? r/wc. this bit indicates the replay timer timed out. 11:9 reserved 8 replay number rollover status (rnr) ? r/wc. this bit indicates the replay number rolled over. 7 bad dllp status (bd) ? r/wc. this bit indicates a bad dllp was received. 6 bad tlp status (bt) ? r/wc. this bit indicates a bad tlp was received. 5:1 reserved 0 receiver error status (re) ? r/wc. this bit indicates a receiver error occurred. bit description 31:13 reserved 12 replay timer timeout mask (rtt) ? r/wo. mask for replay timer timeout. 11:9 reserved 8 replay number rollover mask (rnr) ? r/wo. mask for repl ay number rollover. 7 bad dllp mask (bd) ? r/wo. mask for bad dllp reception. 6 bad tlp mask (bt) ? r/wo. mask for bad tlp reception. 5:1 reserved 0 receiver error mask (re) ? r/wo. mask for receiver errors.
intel ? i/o controller hub 6 (ich6) family datasheet 711 pci express* configuration registers 19.1.58 aecc ? advanced error ca pabilities and control register (pci express?d28:f0/f1/f2/f3) address offset: 158 ? 15bh attribute: ro default value: 00000000h size: 32 bits 19.1.59 res ? root error status register (pci express?d28:f0/f1/f2/f3) address offset: 170 ? 173h attribute: r/wc, ro default value: 00000000h size: 32 bits 19.1.60 rctcl ? root complex to pology capability list register (pci express?d28:f0/f1/f2/f3) address offset: 180 ? 183h attribute: ro default value: 00010005h size: 32 bits bit description 31:9 reserved 8 ecrc check enable (ece) ? ro. ecrc is not supported. 7 ecrc check capable (ecc) ? ro. ecrc is not supported. 6 ecrc generation enable (ege) ? ro. ecrc is not supported. 5 ecrc generation capable (egc) ? ro. ecrc is not supported. 4:0 first error pointer (fep) ? ro. bit description 31:27 advanced error interrupt message number (aemn) ? ro. there is only one error interrupt allocated. 26:4 reserved 3 multiple err_fatal/nonfatal received (menr) ? ro. for intel ? ich6, only one error will be captured. 2 err_fatal/nonfatal received (enr) ? r/wc. 0 = no error message received. 1 = either a fatal or a non-fatal error message is received. 1 multiple err_cor received (mcr) ? ro. for ich6, only one error will be captured. 0 err_cor received (cr) ? r/wc. 0 = no error message received. 1 = a correctable error message is received. bit description 31:20 next capability (next) ? ro. this field indicates the next item in the list, in this case, end of list. 19:16 capability version (cv) ? ro. this field indicates the ve rsion of the capability structure. 15:0 capability id (cid) ? ro. this field indicates is a root complex topology capability.
712 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers 19.1.61 esd ? element se lf description register (pci express?d28:f0/f1/f2/f3) address offset: 184 ? 187h attribute: ro default value: see description size: 32 bits 19.1.62 uld ? upstream link description register (pci express?d28:f0/f1/f2/f3) address offset: 190 ? 193h attribute: ro default value: 00000001h size: 32 bits bit description 31:24 port number (pn) ? ro. this field indicate s the ingress port number for the root port. there is a different value per port: 23:16 component id (cid) ? ro. this field returns the value of the esd.cid field (chipset configuration space:offset 0104h:bits 23:16) of the chip configur ation section, that is programmed by platform bios, since the root port is in the same component as the rcrb. 15:8 number of link entries (nle) ? ro. (default value is 01h) indicates one link entry (corresponding to the rcrb). 7:4 reserved. 3:0 element type (et) ? ro. (default value is 0h) indicates that the element type is a root port. port # value 1 01h 2 02h 3 03h 4 04h bit description 31:24 target port number (pn) ? ro. indicates the port number of the rcrb. 23:16 target component id (tcid) ? ro. this field returns the val ue of the esd.cid field (chipset configuration space:offset 0104h:bits 23:16) of th e chip configuration section, that is programmed by platform bios, since the root port is in the same component as the rcrb. 15:2 reserved. 1 link type (lt) ? ro. indicates that the link points to the ich6 rcrb. 0 link valid (lv) ? ro. indicates that this link entry is valid.
intel ? i/o controller hub 6 (ich6) family datasheet 713 pci express* configuration registers 19.1.63 ulba ? upstream link base addre ss register (pci express?d28:f0/f1/f2/f3) address offset: 198 ? 19fh attribute: ro default value: see description size: 64 bits 19.1.64 pciecr1 ? pci express configuration register 1 (pci express?d28:f0/f1/f2/f3) address offset: 314h attribute: r/w default value: 0a200000h size: 32 bits 19.1.65 pciecr2 ? pci express configuration register 2 (pci express?d28:f0/f1/f2/f3) address offset: 318h attribute: r/w default value: 0a200000h size: 32 bits bit description 63:32 base address upper (bau) ? ro. the rcrb of the ich6 lives in 32-bit space. 31:0 base address lower (bal) ? ro. this field matches the rcba register (d31:f0:offset f0h) value in the lpc bridge. bit description 31:28 pci express configuration bits [31:28] (pciecb:31:28]) ? r/w. refer to the ich6 bios specification for programming of this field. 23:0 reserved bit description 31:24 pci express configuration bits [31:24] (pciecb:31:24]) ? r/w. refer to the ich6 bios specification for programming of this field. 23:0 reserved
714 intel ? i/o controller hub 6 (i ch6) family datasheet pci express* configuration registers
intel ? i/o controller hub 6 (ich6) family datasheet 715 high precision event timer registers 20 high precision event timer registers the timer registers are memory-m apped in a non-indexed scheme. this allows the processor to directly access each register without having to use an index register. the timer register space is 1024 bytes. the registers are generally aligned on 64-bit boundaries to simplify implementation with ia64 processors. there ar e four possible memory address ranges beginning at 1) fed0_0000h, 2) fed0_1000h, 3) fed0_2000h., 4) fed0_4000h. the choice of address range will be selected by configuration bits in the hi gh precision timer configuration register (chipset configuration registers:offset 3404h). behavioral rules: 1. software must not attempt to read or write across register boundaries. for example, a 32-bit access should be to offset x0h, x4h, x8h, or xch. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0ah, 0bh, 0dh, 0eh, or 0fh. any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. however, these accesses should not result in system hangs. 64-bit accesses can only be to x0h and mu st not cross 64-bit boundaries. 2. software should not write to read-only registers. 3. software should not expect any particular or consistent value when reading reserved registers or bits.
716 intel ? i/o controller hub 6 (i ch6) family datasheet high precision event timer registers 20.1 memory mapped registers notes: 1. reads to reserved registers or bits will return a value of 0. 2. software must not attempt locks to the memory -mapped i/o ranges for high precision event timers. if attempted, the lock is not honored, which me ans potential deadlock conditions may occur. table 20-1. memory-mapped registers offset mnemonic register default type 000?007h gcap_id general capabi lities and identification 0429b17f80 86a201h ro 008?00fh ? reserved ? ? 010?017h gen_conf general configuration 0000h r/w 018?01fh ? reserved ? ? 020?027h gintr_sta general interrupt status 00000000 00000000h r/wc, r/w 028?0efh ? reserved ? ? 0f0?0f7h main_cnt main counter value n/a r/w 0f8?0ffh ? reserved ? ? 100?107h tim0_conf timer 0 configuration and capabilities n/a r/w, ro 108?10fh tim0_comp timer 0 comparator value n/a r/w 110?11fh ? reserved ? ? 120?127h tim1_conf timer 1 configuration and capabilities n/a r/w, ro 128?12fh tim1_comp timer 1 comparator value n/a r/w 130?13fh ? reserved ? ? 140?147h tim2_conf timer 2 configuration and capabilities n/a r/w, ro 148?14fh tim2_comp timer 2 comparator value n/a r/w 150?15fh ? reserved ? ? 160?3ffh ? reserved ? ?
intel ? i/o controller hub 6 (ich6) family datasheet 717 high precision event timer registers 20.1.1 gcap_id?general capabilities and identification register address offset: 00h attribute: ro default value: 0429b17f8086a201h size: 64 bits 20.1.2 gen_conf?general configuration register address offset: 010h attribute: r/w default value: 0000000000000000h size: 64 bits bit description 63:32 main counter tick period (counter_clk_per_cap) ? ro. this field indicates the period at which the counter increments in femptoseconds (10^-15 seconds). this will return 0429b17f when read. this indicates a per iod of 69841279 fs (69.841279 ns). 31:16 vendor id capability (vendor_id_cap) ? ro . this is a 16-bit value assigned to intel. 15 legacy replacement rout capable (leg_rt_cap) ? ro. hardwired to 1. legacy replacement interrupt rout option is supported. 14 reserved. this bit returns 0 when read. 13 counter size capability (count_size_cap) ? ro. hardwired to 1. counter is 64-bit wide. 12:8 number of timer capability (num_tim_cap) ? ro. this field indicates the number of timers in this block. 02h = three timers. 7:0 revision identification (rev_id) ? ro. this i ndicates which revision of the function is implemented. default value will be 01h. bit description 63:2 reserved. these bits return 0 when read. 1 legacy replacement rout (leg_rt_cnf) ? r/w. if the enable_cnf bit and the leg_rt_cnf bit are both set, then the interrupts will be routed as follows: ? timer 0 is routed to irq0 in 8259 or irq2 in the i/o apic ? timer 1 is routed to irq8 in 8259 or irq8 in the i/o apic ? timer 2-n is routed as per the routing in the timer n configuration registers. ? if the legacy replacement rout bit is set, the i ndividual routing bits for timers 0 and 1 (apic) will have no impact. ? if the legacy replacement rout bit is not set, the individual routing bits for each of the timers are used. ? this bit will default to 0. bios can set it to 1 to enable the legacy replacement routing, or 0 to disable the legacy r eplacement routing. 0 overall enable (enable_cnf) ? r/w. this bit must be set to enable any of the timers to generate interrupts. if this bit is 0, then the main counter will halt (will not increment) and no interrupts will be caused by any of these timers. for level-triggered interrupts, if an interrupt is pending when the enable_cnf bit is changed from 1 to 0, the interrupt status indications (in the various txx_int_sts bits) will not be cleared. softwa re must write to the txx_int_sts bits to clear the interrupts. note: this bit will default to 0. bios can set it to 1 or 0.
718 intel ? i/o controller hub 6 (i ch6) family datasheet high precision event timer registers 20.1.3 gintr_sta?general interrupt status register address offset: 020h attribute: r/w, r/wc default value: 0000000000000000h size: 64 bits . 20.1.4 main_cnt?main counter value register address offset: 0f0h attribute: r/w default value: n/a size: 64 bits . bit description 63:3 reserved. these bits will return 0 when read. 2 timer 2 interrupt active (t02_int_sts) ? r/w. same functionality as timer 0. 1 timer 1 interrupt active (t01_int_sts) ? r/w. same functionality as timer 0. 0 timer 0 interrupt active (t00_int_sts) ? r/wc. the functionality of this bit depends on whether the edge or level-triggered mode is used for this timer. (default = 0) if set to level-triggered mode: this bit will be set by hardware if the corresponding ti mer interrupt is active. once the bit is set, it can be cleared by software writing a 1 to the same bit posit ion. writes of 0 to this bit will have no effect. if set to edge-triggered mode: this bit should be ignored by software. soft ware should always write 0 to this bit. note: defaults to 0. in edge triggered mode, this bit will always read as 0 and writes will have no effect. bit description 63:0 counter value (counter_val[63:0]) ? r/w. reads return the current value of the counter. writes load the new value to the counter. notes: 1. writes to this register should only be done while the counter is halted. 2. reads to this register return the current value of the main counter. 3. 32-bit counters will always return 0 for the upper 32-bits of this register. 4. if 32-bit software attempts to read a 64-bit c ounter, it should first halt the counter. since this delays the interrupts for all of the timers, this should be done only if the consequences are understood. it is strongly recommended that 32-bit software only operate the timer in 32-bit mode. 5. reads to this register are monotonic. no two consecutive reads return the same value. the second of two reads always returns a larger va lue (unless the timer has rolled over to 0).
intel ? i/o controller hub 6 (ich6) family datasheet 719 high precision event timer registers 20.1.5 timn_conf?timer n conf iguration and capabilities register address offset: timer 0: 100?107h, attribute: ro, r/w timer 1: 120?127h, timer 2: 140?147h default value: n/a size: 64 bits note: the letter n can be 0, 1, or 2, referring to timer 0, 1 or 2. bit description 63:56 reserved. these bits will return 0 when read. 55:52, 43 timer interrupt rout capability (timern_int_rout_cap) ? ro. timer 0, 1:bits 52, 53, 54, and 55 in this fi eld (corresponding to irq 20, 21, 22, and 23) have a value of 1. writes will have no effect. timer 2:bits 43, 52, 53, 54, and 55 in this fiel d (corresponding to irq 11, 20, 21, 22, and 23) have a value of 1. writes will have no effect. note: if irq 11 is used for hpet #2, software should ensure irq 11 is not shared with any other devices to guarantee the proper operation of hpet #2. 51:44, 42:14 reserved . these bits return 0 when read. 13:9 interrupt rout (timern_int_rout_cnf) ? r/w. this 5-bit field indicates the routing for the interrupt to the i/o (x) apic. software writes to this field to select which interrupt in the i/o (x) will be used for this timer?s interrupt. if the value is not supported by this particular timer, then the value read back will not match what is written. the software must only write valid values. notes: 1. if the legacy replacement rout bit is set, t hen timers 0 and 1 will have a different routing, and this bit field has no effect for those two timers. 2. timer 0,1: software is responsible to make sure it programs a valid value (20, 21, 22, or 23) for this field. the ich6 logic does not check the va lidity of the value written. 3. timer 2: software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23) for this field. the ich6 logic does not check the validity of the value written. 8 timer n 32-bit mode (timern_32mode_cnf) ? r/w or ro. software can set this bit to force a 64-bit timer to behave as a 32-bit timer. timer 0:bit is read/write (default to 0). 1 = 64 bit; 0 = 32 bit timers 1, 2:hardwired to 0. writes have no ef fect (since these two timers are 32-bits). 7 reserved . this bit returns 0 when read. 6 timer n value set (timern_val_set_cnf) ? r/w. software uses this bit only for timer 0 if it has been set to periodic mode. by writing this bit to a 1, the software is then allowed to directly set the timer?s accumulator. software does not have to write this bit back to 1 (it automatically clears). software should not write a 1 to this bit posit ion if the timer is set to non-periodic mode. note: this bit will return 0 when read. writes will only have an effect for timer 0 if it is set to periodic mode. writes will have no effect for timers 1 and 2. 5 timer n size (timern_size_cap) ? ro. this read only field indicates the size of the timer. timer 0:value is 1 (64-bits). timers 1, 2:value is 0 (32-bits). 4 periodic interrupt capable (timern_per_int_cap) ? ro. if this bit is 1, the hardware supports a periodic mode for this timer?s interrupt. timer 0: hardwired to 1 (supports the periodic interrupt). timers 1, 2: hardwired to 0 (does not support periodic interrupt).
720 intel ? i/o controller hub 6 (i ch6) family datasheet high precision event timer registers note: reads or writes to unimplemented timers shoul d not be attempted. read from any unimplemented registers will return an undetermined value. 3 timer n type (timern_type_cnf) ? r/w or ro. timer 0:bit is read/write. 0 = disable timer to generate periodic interrupt; 1 = enable timer to generate a periodic interrupt. timers 1, 2: hardwired to 0. writes have no affect. 2 timer n interrupt enable (timern_int_enb_cnf) ? r/w. this bit must be set to enable timer n to cause an interrupt when it times out. 1 = enable. 0 = disable (default). the timer can still count and generate appropriate status bits, but will not cause an interrupt. 1 timer interrupt type (timern_int_type_cnf) ? r/w. 0 =the timer interrupt is edge triggered. this m eans that an edge-type interrupt is generated. if another interrupt occurs, another edge will be generated. 1 =the timer interrupt is level triggered. this m eans that a level-triggered interrupt is generated. the interrupt will be held active until it is cleared by writing to the bit in the general interrupt status register. if another interrupt occurs befor e the interrupt is cleared, the interrupt will remain active. 0reserved . these bits will return 0 when read. bit description
intel ? i/o controller hub 6 (ich6) family datasheet 721 high precision event timer registers 20.1.6 timn_comp?timer n comparator value register address offset: timer 0: 108h?10fh, timer 1: 128h?12fh, timer 2: 148h?14fh attribute: r/w default value: n/a size: 64 bit bit description 63:0 timer compare value ? r/w. reads to this register return the current value of the comparator timers 0, 1, or 2 are configured to non-periodic mode: writes to this register load the value against which the main counter should be compared for this timer. ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? the value in this register does not change based on the interrupt being generated. timer 0 is configured to periodic mode: ? when the main counter equals the value last written to this register, the corresponding interrupt can be generated (if so enabled). ? after the main counter equals the value in this r egister, the value in this register is increased by the value last written to the register. for example, if the value written to the register is 00000123h, then 1. an interrupt will be generated when the main counter reaches 00000123h. 2. the value in this register will then be adjusted by the hardware to 00000246h. 3. another interrupt will be generated when the main counter reaches 00000246h 4. the value in this register will then be adjusted by the hardware to 00000369h ? as each periodic interrupt occurs, the value in this register will increment. when the incremented value is greater than the maximum value possible for this register (ffffffffh for a 32-bit timer or ffffffffffffffffh fo r a 64-bit timer), the value will wrap around through 0. for example, if the current value in a 32-bit timer is ffff0000h and the last value written to this register is 20000, then after the next interrupt the value will change to 00010000h default value for each timer is all 1s for the bits that are implemented. for example, a 32-bit timer has a default value of 00000000ffffffffh. a 64-bit timer has a default value of ffffffffffffffffh.
722 intel ? i/o controller hub 6 (i ch6) family datasheet high precision event timer registers
intel ? i/o controller hub 6 (ich6) family datasheet 723 ballout definition 21 ballout definition this section contains the intel ? ich6 ballout information. the ballout is preliminary and subject to change. figure 21-1 and figure 21-2 are the ballout map of the 609 bga package. table 21-1 is a bga ball list, sorted alphabetically by signal name. note: ? throughout this chapter, this symbol indicates a mobile only signal ? throughout this chapter, this symbol indicates a desktop only signal
724 intel ? i/o controller hub 6 (ich6) family datasheet ballout definition figure 21-1. intel ? ich6 preliminary ball out (topview?left side) 1234 5 67 8 9101112 a b c d e f g void void void void void void h void void void void void void j void void void void void void k void void void vcc1_5_a vcc1_5_a vss l void void void vcc1_5_a vss vss m void void void vss vss vss n void void void vcc1_5_a vss vss p void void void vss vss vss r void void void vcc1_5_a vss vss t void void void vcc1_5_a vcc1_5_a vss u void void void void void void v void void void void void void w void void void void void void y aa ab ac ad 1 23 456 7 89101112 ae af ag 13 14 13 14 vss void void void vcc3_3 gnt[0]# vss par gnt[2]# vss vcc3_3 stop# vss ad[30] pirq[c]# vss vcc3_3 gpi[8] vss pwrbtn# vccsus3_3 vss rtcx1 pwrok vss sata_clkp vss vccsatapll vss vss ad[10] ad[26] ad[2] ad[11] ad[0] ad[6] c/be[3]# ad[22] trdy# ad[16] pirq[b]# gpi[12] pirq[a]# lad[0]/ fwh[0] pcirst# ri# sys_reset# batlow# ? / tp[0] ? vccsus3_3 rtcx2 rtcrst# vss sata_clkn vss vss sata[0]txp sata[0]txn irdy# ad[24] devsel# ad[9] perr# ad[4] ad[20] ad[13] frame# ad[28] pirq[d]# pirq[h]#/ gpi[5] lad[1]/ fwh[1] lframe#/ fwh[4] gpio[27] gpio[28] tp[3] gpio[24] sus_stat#/ lpcpd# rsmrst# intruder# vccrtc vss sata[0]rxp sata[0]rxn vss vss vss ad[14] vss ad[18] vcc3_3 vss c/be[2]# ad[21] vss ad[31] vcc3_3 vss lad[3]/ fwh[3] ldrq[1]#/ gpi[41] vss slp_s3# vccsus3_3 vss smlink[0] smbclk vss vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a sata[1]txn ? / reserved ? sata[1]txp ? / reserved ? ad[29] req[1]# plock# ad[12] ad[1] ad[3] serr# ad[23] ad[15] ad[17] req[0]# req[2]# lad[2]/ fwh[2] gpio[25] pltrst# slp_s4# wake# lan_rst# smbdata linkalert# intvrmen vcc1_5_a sata[1]rxn ? / reserved ? sata[1]rxp ? / reserved ? vcc1_5_a vcc1_5_a vcc1_5_a vcc3_3 gnt[1]# pirq[g]#/ gpi[4] ad[7] ad[8] gnt[5]#/ gpo[17] pciclk c/be[1]# c/be[0]# ad[27] ad[19] ad[25] ldrq[0]# pme# gpi[13] slp_s5# smlink[1] susclk smbalert# /gpi[11] vss vcc1_5_a vcc1_5_a vss vss vss sata[2]txn sata[2]txp vss req[6]#/ gpi[0] pirq[f]#/ gpi[3] vss gnt[4]#/ gpo[48] req[4]#/ gpi[40] vss vcc3_3 vcc3_3 vss vcc3_3 vcc3_3 vss vcc2_5 vccsus1_5 vss vccsus1_5 vccsus3_3 vss vccsus3_3 vcc1_5_a vss sata[2]rxp sata[2]rxn vss vss vss vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a vcc1_5_a sata[3]txn ? / reserved ? sata[3]txp ? / reserved ? vcc1_5_a vss sata[3]rxn ? / reserved ? sata[3]rxp ? / reserved ? vcc1_5_a vcc1_5_a vcc1_5_a vcc3_3 vss vss vss vss vss vcc3_3 vss dd[7] dd[5] dd[6] vss satarbias satarbias# vcc3_3 dd[10] vss dd[3] vss vss vss vss dd[11] dd[12] dd[15] dd[8] dd[9] vcc3_3 vcc3_3 ddreq diow# dd[0] dd[4] dd[2] vss v5ref req[3]# gnt[3]# gnt[6]#/ gpo[16] req[5]#/ gpi[1] spkr vcc1_5_a vss acz_sync acz_sdout pirq[e]#/ gpio[2] ad[5] vcc1_5_a vss acz_rst# acz_sdin[2] acz_bit_clk vss clk14 acz_sdin[1] vcclan1_5 ? / vccsus1_5 ? vccsus3_3 lan_rstsync lan_txd[1] ee_dout lan_rxd[1] acz_sdin[0] vcclan1_5 ? / vccsus1_5 ? vss ee_shclk lan_txd[0] ee_cs lan_rxd[0] lan_clk vss vcclan3_3 ? / vccsus3_3 ? vss lan_rxd[2] vss lan_txd[2] ee_din vcclan3_3 ? / vccsus3_3 ? usbp[7]n usbp[7]p vss vss vss vcclan3_3 ? / vccsus3_3 ? vcclan3_3 ? / vccsus3_3 ? vcc1_5_a vss vss vss vss vss vcc1_5_a void void void
intel ? i/o controller hub 6 (ich6) family datasheet 725 ballout definition figure 21-2. intel ? ich6 preliminary ballout (topview?right side) 15 void void void void void void void void void void void void void void void void void void vss vcc1_5_a vcc1_5_a void void void vss vss vcc1_5_a void void void vss vss vss void void void vss vss vcc1_5_a void void void vss vss vss void void void vss vss vcc1_5_a void void void vss vcc1_5_a vcc1_5_a void void void void void void void void void void void void void void void void void void void void void 15 16 17 18 19 20 21 22 23 24 25 26 27 ag a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 16 17 18 19 20 21 22 23 24 25 26 27 vss vss usbp[6]n usbp[6]p vss vccsus3_3 vccsus3_3 usbp[5]p usbp[5]n vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 vccsus3_3 usbp[4]p usbp[4]n vss vccsus3_3 usbp[3]n usbp[3]p vss vss vss vccsus3_3 vccsus3_3 vss vss usbp[2]p usbp[2]n vss vss vccsus1_5 usbp[1]n usbp[1]p vss vss vcc1_5_a vcc1_5_a vcc1_5_a vss vss usbp[0]n usbp[0]p vcc1_5_a v5ref_sus vss vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_a gpo[19] stp_pci# ? / gpo[18] ? gpo[23] vss vrmpwrgd mch_sync# vcc3_3 ddack# vcc3_3 vss dd[13] dd[1] dd[14] vss ideirq da[0] dcs1# dior# iordy vcc3_3 vcc3_3 da[1] da[2] vcc3_3 dcs3# sata[0]gp/ gpi[26] vss v5ref vcc2_5 gpio[34] vss sata[1]gp ? / gpi[29] sata[2]gp/ gpi[30] sata[3]gp ? / gpi[31] vcc1_5_a vss sataled# bmbusy# ? / gpi[6] ? gpi[7] clkrun# ? / gpio[32] ? vcc3_3 vcc1_5_a serirq thrm# gpo[21] dprslpvr ? / tp[1] ? gpio[33] vss usbrbias# usbrbias vss vss vcc1_5_a vss vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vss vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b vcc1_5_b v_cpu_io vss stp_cpu# ? / gpo[20] ? init3_3v# a20gate vss vss vss oc[4]#/gpi[9] oc[5]#/ gpi[10] vcc1_5_a dmi_ircomp vcc1_5_b vss vss vss vss vss vcc1_5_b perp[4] vss vss vss vss vss vss vcc1_5_b dmi[3]rxp vss rcin# thrmtrip# a20m# v_cpu_io vccsus3_3 vss oc[7]#/ gpi[15] vcc1_5_a vcc1_5_a dmi_zcomp vcc1_5_b perp[1] vss perp[2] vss perp[3] vcc1_5_b pern[4] vss dmi[0]rxp vss dmi[1]rxp vss dmi[2]rxp vcc1_5_b dmi[3]rxn vss vss dprstp# ? / tp[4] ? ferr# intr vccusbpll vss oc[6]#/ gpi[14] vcc1_5_a vss vcc1_5_b vcc1_5_b pern[1] vss pern[2] vss pern[3] vcc1_5_b vcc1_5_b vss dmi[0]rxn vss dmi[1]rxn vss dmi[2]rxn vcc1_5_b vcc1_5_b dmi_clkp dmi_clkn vss nmi cpupwrgd /gpo[49] vss oc[2]# oc[3]# vcc1_5_a vcc3_3 vcc1_5_b petp[1] vss petp[2] vss petp[3] vss petp[4] vcc1_5_b dmi[0]txp vss dmi[1]txp vss dmi[2]txp vss dmi[3]txp vcc1_5_b vss v_cpu_io stpclk# vss ignne# clk48 oc[1]# oc[0]# vcc1_5_a vss vcc1_5_b petn[1] vss petn[2] vss petn[3] vss petn[4] vcc1_5_b dmi[0]txn vss dmi[1]txn vss dmi[2]txn vss dmi[3]txn vcc1_5_b vccdmipll dpslp# ? / tp[2] ? cpuslp# init# smi#
726 intel ? i/o controller hub 6 (ich6) family datasheet ballout definition table 21-1. intel ? ich6 ballout by signal name signal name ball # a20gate af22 a20m# af23 acz_bit_clk c10 acz_rst# a10 acz_sdin[0] f11 acz_sdin[1] f10 acz_sdin[2] b10 acz_sdout c9 acz_sync b9 ad[0] e2 ad[1] e5 ad[2] c2 ad[3] f5 ad[4] f3 ad[5] e9 ad[6] f2 ad[7] d6 ad[8] e6 ad[9] d3 ad[10] a2 ad[11] d2 ad[12] d5 ad[13] h3 ad[14] b4 ad[15] j5 ad[16] k2 ad[17] k5 ad[18] d4 ad[19] l6 ad[20] g3 ad[21] h4 ad[22] h2 ad[23] h5 ad[24] b3 ad[25] m6 ad[26] b2 ad[27] k6 ad[28] k3 ad[29] a5 ad[30] l1 ad[31] k4 batlow# ? /tp[0] ? v2 bmbusy# ? /gpi[6] ? ad19 c/be[0]# j6 c/be[1]# h6 c/be[2]# g4 c/be[3]# g2 clk14 e10 clk48 a27 clkrun# ? /gpio[32] ? af19 cpupwrgd/ gpo[49] ag25 cpuslp# ae27 da[0] ac16 da[1] ab17 da[2] ac17 dcs1# ad16 dcs3# ae17 dd[0] ad14 dd[1] af15 dd[2] af14 dd[3] ad12 dd[4] ae14 dd[5] ac11 dd[6] ad11 dd[7] ab11 dd[8] ae13 dd[9] af13 dd[10] ab12 dd[11] ab13 dd[12] ac13 dd[13] ae15 dd[14] ag15 dd[15] ad13 ddack# ab15 ddreq ab14 devsel# c3 dior# ae16 diow# ac14 dmi[0]rxn t25 dmi[0]rxp t24 table 21-1. intel ? ich6 ballout by signal name signal name ball # dmi[0]txn r27 dmi[0]txp r26 dmi[1]rxn v25 dmi[1]rxp v24 dmi[1]txn u27 dmi[1]txp u26 dmi[2]rxn y25 dmi[2]rxp y24 dmi[2]txn w27 dmi[2]txp w26 dmi[3]rxn ab24 dmi[3]rxp ab23 dmi[3]txn aa27 dmi[3]txp aa26 dmi_clkn ad25 dmi_clkp ac25 dmi_ircomp f23 dmi_zcomp f24 dpslp# ? /tp[2] ? ad27 dprslpvr ? /tp[1] ? ae20 dprstp# ? /tp[4] ? ae24 ee_cs d12 ee_din f13 ee_dout d11 ee_shclk b12 ferr# af24 frame# j3 gnt[0]# c1 gnt[1]# b6 gnt[2]# f1 gnt[3]# c8 gnt[4]#/gpo[48] e7 gnt[5]#/gpo[17] f6 gnt[6]#/gpo[16] d8 gpo[23] ad21 gpi[7] ae19 gpi[8] r1 gpi[12] m2 gpi[13] r6 gpo[19] ab21 gpo[21] ad20 table 21-1. intel ? ich6 ballout by signal name signal name ball #
intel ? i/o controller hub 6 (ich6) family datasheet 727 ballout definition gpio[24] v3 gpio[25] p5 gpio[27] r3 gpio[28] t3 gpio[33] af20 gpio[34] ac18 ideirq ab16 ignne# ag26 init# af27 init3_3v# ae22 intr ag24 intruder# aa3 intvrmen aa5 iordy af16 irdy# a3 lad[0]/fwh[0] p2 lad[1]/fwh[1] n3 lad[2]/fwh[2] n5 lad[3]/fwh[3] n4 lan_clk f12 lan_rst# v5 lan_rstsync b11 lan_rxd[0] e12 lan_rxd[1] e11 lan_rxd[2] c13 lan_txd[0] c12 lan_txd[1] c11 lan_txd[2] e13 ldrq[0]# n6 ldrq[1]#/gpi[41] p4 lframe#/fwh[4] p3 linkalert# y5 mch_sync# ag21 nmi af25 oc[0]# c27 oc[1]# b27 oc[2]# b26 oc[3]# c26 oc[4]#/gpi[9] c23 oc[5]#/gpi[10] d23 oc[6]#/gpi[14] c25 table 21-1. intel ? ich6 ballout by signal name signal name ball # oc[7]#/gpi[15] c24 par e1 pciclk g6 pcirst# r2 pern[1] h25 pern[2] k25 pern[3] m25 pern[4] p24 perp[1] h24 perp[2] k24 perp[3] m24 perp[4] p23 perr# e3 petn[1] g27 petn[2] j27 petn[3] l27 petn[4] n27 petp[1] g26 petp[2] j26 petp[3] l26 petp[4] n26 pirq[a]# n2 pirq[b]# l2 pirq[c]# m1 pirq[d]# l3 pirq[e]#/gpi[2] d9 pirq[f]#/gpi[3] c7 pirq[g]#/gpi[4] c6 pirq[h]#/gpi[5] m3 plock# c5 pltrst# r5 pme# p6 pwrbtn# u1 pwrok aa1 rcin# ad23 req[0]# l5 req[1]# b5 req[2]# m5 req[3]# b8 req[4]#/gpi[40] f7 req[5]#/gpi[1] e8 table 21-1. intel ? ich6 ballout by signal name signal name ball # req[6]#/gpi[0] b7 ri# t2 rsmrst# y3 rtcrst# aa2 rtcx1 y1 rtcx2 y2 sata[0]gp/gpi[26] af17 sata[0]rxn ae3 sata[0]rxp ad3 sata[0]txn ag2 sata[0]txp af2 sata[1]gp ? /gpi[29] ae18 sata[1]rxn ? / reserved ? ac5 sata[1]rxp ? / reserved ? ad5 sata[1]txn ? / reserved ? af4 sata[1]txp ? / reserved ? ag4 sata[2]gp/gpi[30] af18 sata[2]rxn ad7 sata[2]rxp ac7 sata[2]txn af6 sata[2]txp ag6 sata[3]gp ? /gpi[31] ag18 sata[3]rxn ? / reserved ? ac9 sata[3]rxp ? / reserved ? ad9 sata[3]txn ? / reserved ? af8 sata[3]txp ? / reserved ? ag8 sata_clkn ac2 sata_clkp ac1 sataled# ac19 satarbias af11 satarbias# ag11 serirq ab20 serr# g5 slp_s3# t4 slp_s4# t5 slp_s5# t6 table 21-1. intel ? ich6 ballout by signal name signal name ball #
728 intel ? i/o controller hub 6 (ich6) family datasheet ballout definition smbalert#/gpi[11] w6 smbclk y4 smbdata w5 smi# ag27 smlink[0] w4 smlink[1] u6 spkr f8 stop# j1 stp_cpu# ? / gpo[20] ? ad22 stp_pci# ? /gpo[18] ? ac21 stpclk# ae26 sus_stat#/lpcpd# w3 susclk v6 sys_reset# u2 thrmtrip# ae23 thrm# ac20 tp[3] u3 trdy# j2 usbp[0]n c21 usbp[0]p d21 usbp[1]n a20 usbp[1]p b20 usbp[2]n d19 usbp[2]p c19 usbp[3]n a18 usbp[3]p b18 usbp[4]n e17 usbp[4]p d17 usbp[5]n b16 usbp[5]p a16 usbp[6]n c15 usbp[6]p d15 usbp[7]n a14 usbp[7]p b14 usbrbias b22 usbrbias# a22 v_cpu_io ab22 v_cpu_io ad26 v_cpu_io ag23 v5ref a8 table 21-1. intel ? ich6 ballout by signal name signal name ball # v5ref aa18 v5ref_sus f21 vcc1_5_a d24 vcc1_5_a d25 vcc1_5_a d26 vcc1_5_a d27 vcc1_5_a e20 vcc1_5_a e21 vcc1_5_a e22 vcc1_5_a e23 vcc1_5_a e24 vcc1_5_a f9 vcc1_5_a f20 vcc1_5_a g8 vcc1_5_a g20 vcc1_5_a l11 vcc1_5_a l12 vcc1_5_a l14 vcc1_5_a l16 vcc1_5_a l17 vcc1_5_a m11 vcc1_5_a m17 vcc1_5_a p11 vcc1_5_a p17 vcc1_5_a t11 vcc1_5_a t17 vcc1_5_a u11 vcc1_5_a u12 vcc1_5_a u14 vcc1_5_a u16 vcc1_5_a u17 vcc1_5_a aa6 vcc1_5_a aa7 vcc1_5_a aa8 vcc1_5_a aa9 vcc1_5_a aa19 vcc1_5_a aa20 vcc1_5_a aa21 vcc1_5_a ab4 vcc1_5_a ab5 vcc1_5_a ab6 table 21-1. intel ? ich6 ballout by signal name signal name ball # vcc1_5_a ab8 vcc1_5_a ac4 vcc1_5_a ac8 vcc1_5_a ad4 vcc1_5_a ad8 vcc1_5_a ae4 vcc1_5_a ae5 vcc1_5_a ae8 vcc1_5_a ae9 vcc1_5_a af5 vcc1_5_a af9 vcc1_5_a ag5 vcc1_5_a ag9 vcc1_5_b f25 vcc1_5_b f26 vcc1_5_b f27 vcc1_5_b g22 vcc1_5_b g23 vcc1_5_b g24 vcc1_5_b g25 vcc1_5_b h21 vcc1_5_b h22 vcc1_5_b j21 vcc1_5_b j22 vcc1_5_b k21 vcc1_5_b k22 vcc1_5_b l21 vcc1_5_b l22 vcc1_5_b m21 vcc1_5_b m22 vcc1_5_b n21 vcc1_5_b n22 vcc1_5_b n23 vcc1_5_b n24 vcc1_5_b n25 vcc1_5_b p21 vcc1_5_b p25 vcc1_5_b p26 vcc1_5_b p27 vcc1_5_b r21 vcc1_5_b r22 table 21-1. intel ? ich6 ballout by signal name signal name ball #
intel ? i/o controller hub 6 (ich6) family datasheet 729 ballout definition vcc1_5_b t21 vcc1_5_b t22 vcc1_5_b u21 vcc1_5_b u22 vcc1_5_b v21 vcc1_5_b v22 vcc1_5_b w21 vcc1_5_b w22 vcc1_5_b y21 vcc1_5_b y22 vcc1_5_b aa22 vcc1_5_b aa23 vcc1_5_b aa24 vcc1_5_b aa25 vcc1_5_b ab25 vcc1_5_b ab26 vcc1_5_b ab27 vcc2_5 p7 vcc2_5 ab18 vcc3_3 a6 vcc3_3 b1 vcc3_3 e4 vcc3_3 e26 vcc3_3 h1 vcc3_3 h7 vcc3_3 j7 vcc3_3 l4 vcc3_3 l7 vcc3_3 m7 vcc3_3 p1 vcc3_3 aa10 vcc3_3 aa12 vcc3_3 aa14 vcc3_3 aa15 vcc3_3 aa17 vcc3_3 ac15 vcc3_3 ad17 vcc3_3 ag10 vcc3_3 ag13 vcc3_3 ag16 vcc3_3 ag19 table 21-1. intel ? ich6 ballout by signal name signal name ball # vccdmipll ac27 vcclan1_5 ? / vccsus1_5 ? g10 vcclan1_5 ? / vccsus1_5 ? g11 vcclan3_3 ? / vccsus3_3 ? a13 vcclan3_3 ? / vccsus3_3 ? f14 vcclan3_3 ? / vccsus3_3 ? g13 vcclan3_3 ? / vccsus3_3 ? g14 vccrtc ab3 vccsatapll ae1 vccsus1_5 g19 vccsus1_5 r7 vccsus1_5 u7 vccsus3_3 a11 vccsus3_3 a17 vccsus3_3 a24 vccsus3_3 b17 vccsus3_3 c16 vccsus3_3 c17 vccsus3_3 d16 vccsus3_3 e16 vccsus3_3 f15 vccsus3_3 f16 vccsus3_3 f18 vccsus3_3 g15 vccsus3_3 g16 vccsus3_3 g17 vccsus3_3 g18 vccsus3_3 u4 vccsus3_3 v1 vccsus3_3 v7 vccsus3_3 w2 vccsus3_3 y7 vccusbpll a25 vrmpwrgd af21 vss a1 vss a4 vss a7 table 21-1. intel ? ich6 ballout by signal name signal name ball # vss a9 vss a12 vss a15 vss a19 vss a21 vss a23 vss a26 vss b13 vss b15 vss b19 vss b21 vss b23 vss b24 vss b25 vss c4 vss c14 vss c18 vss c20 vss c22 vss d1 vss d7 vss d10 vss d13 vss d14 vss d18 vss d20 vss d22 vss e14 vss e15 vss e18 vss e19 vss e25 vss e27 vss f4 vss f17 vss f19 vss f22 vss g1 vss g7 vss g9 vss g12 table 21-1. intel ? ich6 ballout by signal name signal name ball #
730 intel ? i/o controller hub 6 (ich6) family datasheet ballout definition vss g21 vss h23 vss h26 vss h27 vss j4 vss j23 vss j24 vss j25 vss k1 vss k7 vss k23 vss k26 vss k27 vss l13 vss l15 vss l23 vss l24 vss l25 vss m4 vss m12 vss m13 vss m14 vss m15 vss m16 vss m23 vss m26 vss m27 vss n1 vss n7 vss n11 vss n12 vss n13 vss n14 vss n15 vss n16 vss n17 vss p12 vss p13 vss p14 vss p15 vss p16 table 21-1. intel ? ich6 ballout by signal name signal name ball # vss p22 vss r4 vss r11 vss r12 vss r13 vss r14 vss r15 vss r16 vss r17 vss r23 vss r24 vss r25 vss t1 vss t7 vss t12 vss t13 vss t14 vss t15 vss t16 vss t23 vss t26 vss t27 vss u13 vss u15 vss u23 vss u24 vss u25 vss v4 vss v23 vss v26 vss v27 vss w1 vss w7 vss w23 vss w24 vss w25 vss y6 vss y23 vss y26 vss y27 vss aa4 table 21-1. intel ? ich6 ballout by signal name signal name ball # vss aa11 vss aa13 vss aa16 vss ab1 vss ab2 vss ab7 vss ab9 vss ab10 vss ab19 vss ac3 vss ac6 vss ac10 vss ac12 vss ac22 vss ac23 vss ac24 vss ac26 vss ad1 vss ad2 vss ad6 vss ad10 vss ad15 vss ad18 vss ad24 vss ae2 vss ae6 vss ae7 vss ae10 vss ae11 vss ae12 vss ae21 vss ae25 vss af1 vss af3 vss af7 vss af10 vss af12 vss af26 vss ag1 vss ag3 vss ag7 table 21-1. intel ? ich6 ballout by signal name signal name ball #
intel ? i/o controller hub 6 (ich6) family datasheet 731 ballout definition vss ag12 vss ag14 vss ag17 vss ag20 vss ag22 wake# u5 table 21-1. intel ? ich6 ballout by signal name signal name ball #
732 intel ? i/o controller hub 6 (i ch6) family datasheet ballout definition
intel ? i/o controller hub 6 (ich6) family datasheet 733 electrical characteristics 22 electrical characteristics this chapter contains the dc and ac character istics for the ich6. ac timing diagrams are included. 22.1 thermal specifications refer to the intel ? i/o controller hub 6 (ich6) thermal design guidelines document for ich6 thermal information. 22.2 absolute maximum ratings table 22-1. intel ? ich6 absolute maximum ratings parameter maximum limits voltage on any 3.3 v pin with respec t to ground -0.5 to vcc3_3 + 0.5 v voltage on any 5 v tolerant pin with respect to ground (v5ref=5v) -0.5 to v5ref + 0.5 v 1.5 v supply voltage with respect to vss -0.5 to 2.1 v 2.5 v supply voltage with respect to vss -0.5 to 3.1 v 3.3 v supply voltage with respect to vss -0.5 to 4.6 v 5.0 v supply voltage with respect to vss -0.5 to 5.5 v v_cpu_io supply voltage with respect to vss 0.8 to 1.75 v
734 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics 22.3 dc characteristics note: 1. iccrtc data is taken with vccrtc at 3.0 v while the sy stem is in g3 state at room temperature and only the g3 state for this power well is shown to provide an estimate of battery life. table 22-2. dc current characteristics power plane maximum power consumption symbol s0 s1 s3 hot s3 cold s4/s5 g3 vcc1_5_a 1.9 a 1.3 a 0.4 a n/a n/a n/a vcc1_5_b core 630 ma 230 ma 50 ma n/a n/a n/a vcc3_3 380 ma 60 ma 60 ma n/a n/a n/a vccsus3_3 70 ma 30 ma 50 ma 30 ma 40 ma n/a v5ref 150 a 150 a 150 a n/a n/a n/a v5ref_sus 10 ma 10 ma 10 ma 10 ma 10 ma n/a vccrtc 1 n/a n/a n/a n/a n/a 6 a
intel ? i/o controller hub 6 (ich6) family datasheet 735 electrical characteristics notes: 1. negligible change when vccsus1_5 internal vr is enabled. internal vccsus1_5 vr is enabled through ich6-m strap option. this internal vr is tied to the core well in s0. it is only tied to the vccsus3_3 rail for sleep states. 2. includes worst case leakage. 3. vcc2_5 internal vr enabled. 4. vcc2_5 internal vr disabled. 5. vccsus1_5 internal vr enabled. 6. vccsus1_5 internal vr disabled. 7. iccrtc data is taken with vccrtc at 3.0 v while the system is in g3 state at room temperature and only the g3 state for this power well is shown to provide an estimate of battery life. table 22-3. dc current characteristics (mobile only) power plane maximum power consumption symbol s0 s3 cold s4/s5 g3 v_cpu_io 14 ma off off off vcc1_5_a 1.9 a off off off vcc1_5_a 1,2 1.9 a off off off vcc1_5_b 630 ma off off off vcc2_5 3 ma off off off vcc3_3 3 340 ma off off off vcc3_3 4 340 ma off off off vcclan1_5 20 ma 10 ma 10 ma off vcclan3_3 5 30 ma 10 ma 10 ma off vcclan3_3 6 30 ma 10 ma 10 ma off vccsus1_5 20 ma 20 ma 20 ma off vccsus3_3 5 40 ma 30 ma 30 ma off vccsus3_3 6 40 ma 30 ma 30 ma off vccrtc 7 n/a n/a n/a 6 a v5ref 1 ma off off off v5ref_sus 10 ma < 10 ma < 10 ma off
736 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics table 22-4. dc characteristic input signal association (sheet 1 of 2) symbol associated signals v ih1 /v il1 (5 v tolerant) pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, plock#, req[3:0]#, req[4]#/gpi[40], req[5]#/gpi[1], req[6]#/gpi[0], serr#, stop#, trdy# interrupt signals: pirq[d:a]#, pirq[h:e]#/gpi[5:2] (open drain) strap signals: req:[4:1]# (strap purposes only) v ih2 /v il2 (5 v tolerant) interrupt signals: ideirq strap signals: spkr, tp[1]/dprslpvr, sataled# (strap purposes only) v ih3 /v il3 clock signals : clk14, clk48 power management signals: mch_sync#, thrm#, vrmpwrgd sata signals: desktop: satagp[3:0]/gpi[31:29,26] mobile: satagp[2,0]/gpi[30,26] gpio signals: desktop: gpi[13,12,8], gpio[34,33] mobile: gpi[31,29,13,12,8], gpio[34,33] v ih4 /v il4 clock signals: pciclk lpc/firmware hub signals: lad[3:0]/fwh[3:0], ldrq[0]#, ldrq[1]#/gpi[41] power management signals: desktop: lan_rst# mobile: bmbusy#, clkrun#, lan_rst# gpio signals: desktop: gpi[32,7,6] mobile: gpi[7] pci signals: pme# interrupt signals: serirq processor signals: a20gate, rcin# usb signals: oc[3:0]#, oc[5:4]#/gpi[10:9], oc[7:6]#/gpi[15:14] strap signals: gnt[6]#/gpo[16], gnt[5]#/gpo[17] (strap purposes only) v ih5 /v il5 smbus signals: smbclk, smbdata system management signals: smbalert#/gpi[11], smlink[1:0] v il6 /v ih6 lan signals: lan_clk, lan_rxd[2:0] eeprom signals: ee_din strap signals: ee_cs, ee_dout (strap purposes only) v il7 /v ih7 processor signals: ferr#, thrmtrip# v imin8 /v imax8 pci express* data rx signals: per[p,n][4:1] v il9 /v ih9 real time clock signals: rtcx1 v imin10 /v imax10 sata signals: desktop: sata[3:0]rx[p,n] mobile: sata[2,0]rx[p,n] v il11 /v ih11 ac ?97/intel high definition audio signals: acz_sdin[2:0] ac ?97 signals: acz_bit_clk strap signals: acz_sdout, acz_sync (strap purposes only) v il12 /v ih12 / v cross(abs) clock signals: dmi_clkn, dmi_clkp, sata_clkn, sata_clkp
intel ? i/o controller hub 6 (ich6) family datasheet 737 electrical characteristics v ih13 /v il13 power management signals: desktop: pwrbtn#, ri#, sys_reset#, wake# mobile: batlow#, pwrbtn#, ri#, sys_reset#, wake# system management signal: linkalert# gpio signals: gpio[28,27,25,24] other signals: tp[3] strap signals: linkalert#, gpio[25], tp[3] (strap purposes only) v ih14 /v il14 power management signals: pwrok, rsmrst#, rtcrst# system management signals: intruder# other signals: intvrmen v di / v cm / v se (5 v tolerant) usb signals: usbp[7:0][p,n] (low-speed and full-speed) v hssq / v hsdsc / v hscm (5 v tolerant) usb signals: usbp[7:0][p,n] (in high-speed mode) v+/v-/v hys / v thravg /v ring (5 v tolerant) ide signals: dd:[15:0], ddreq, iordy. for ultra dma mode 4 and lower, these signals follow the dc characteristic for v ih2 / v il2. table 22-4. dc characteristic input signal association (sheet 2 of 2) symbol associated signals
738 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics table 22-5. dc input characteristics (sheet 1 of 2) symbol parameter min max unit notes v il1 input low voltage ? 0.5 0.3(vcc3_3) v v ih1 input high voltage 0.5(vcc3_3) v5ref + 0.5 v v il2 input low voltage -0.5 0.8 v v ih2 input high voltage 2.0 v5ref + 0.5 v v il3 input low voltage ? 0.5 0.8 v v ih3 input high voltage 2.0 vcc3_3 + 0.5 v v il4 input low voltage ? 0.5 0.3(vcc3_3) v v ih4 input high voltage 0.5(vcc3_3) vcc3_3 + 0.5 v v il5 input low voltage ? 0.5 0.8 v v ih5 input high voltage 2.1 vccsus3_3 + 0.5 v v il6 input low voltage -0.5 0.3(vcc3_3) v v ih6 input high voltage 0.6(vcc3_3) vcc3_3 + 0.5 v v il7 input low voltage ? 0.5 0.58(v_cpu_io) v v ih7 input high voltage 0.73(v_cpu_io) v_cpu_io + 0.5 v v imin8 minimum input voltage 175 mvdiff p-p note 1 v imax8 maximum input voltage 1200 mvdiff p-p note 1 v il9 input low voltage ? 0.5 0.10 v v ih9 input high voltage 0.40 1.2 v v imin10 minimum input voltage 325 mvdiff p-p note 2 v imax10 maximum input voltage 600 mvdiff p-p note 2 v il11 input low voltage ? 0.5 0.35(vcc3_3) v v ih11 input high voltage 0.65(vcc3_3) vcc3_3 + 0.5 v v il12 input low voltage -0.150 0.150 v v ih12 input high voltage 0.660 0.850 v v il13 input low voltage ? 0.5 0.8 v v ih13 input high voltage 2.0 vccsus3_3 + 0.5 v v il14 input low voltage ? 0.5 0.78 v v ih14 input high voltage 2.0 vccrtc + 0.5 v note 3 v cross(abs) absolute crossing point 0.250 0.550 v v+ low to high input threshold 1.5 2.0 v note 4 v ? high to low input threshold 1.0 1.5 v note 4
intel ? i/o controller hub 6 (ich6) family datasheet 739 electrical characteristics notes: 1. pci express mvdiff p-p = |petp[x] ? petn[x]| 2. sata vdiff, tx (v imax/min10 is measured at the sata connector on the transmit side (generally, the motherboard connector), where sata mvdiff p-p = |sata[x]txp/rxp ? sata[x]txn/rxn| 3. vccrtc is the voltage applied to the vccrtc well of the ich6. when the system is in a g3 state, this is generally supplied by the coin cell battery, but for s5 and greater, this is generally vccsus3_3. 4. applies to ultra dma modes greater than ultra dma mode 4 5. this is an ac characteristic that r epresents transient val ues for these signals 6. v di = | usbpx[p] ? usbpx[n] 7. applies to high-speed usb 2.0 8. includes v di range v hys difference between input thresholds: (v+current value) ? (v ? current value) 320 mv note 4 v thravg average of thresholds: ((v+current value) + (v ? current value))/2 1.3 1.7 v note 4 v ring ac voltage at recipient connector ? 1 6 v note 4, 5 v di differential input sensitivity 0.2 v note 6, 7 v cm differential common mode range 0.8 2.5 v note 8, 7 v se single-ended receiver threshold 0.8 2.0 v note 7 v hssq hs squelch detection threshold 100 150 mv note 7 v hsdsc hs disconnect detection threshold 525 625 mv note 7 v hscm hs data signaling common mode voltage range ? 50 500 mv note 7 v hssq hs squelch detection threshold 100 150 mv note 7 v hsdsc hs disconnect detection threshold 525 625 mv note 7 v hscm hs data signaling common mode voltage range ? 50 500 mv note 7 table 22-5. dc input characteristics (sheet 2 of 2) symbol parameter min max unit notes
740 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics note: 1. these signals are open drain. table 22-6. dc characteristic output signal association symbol associated signals v oh1 /v ol1 ide signals: da[2:0], dcs[3,1]#, ddack#, dd[15:0], dior#, diow# v oh2 /v ol2 processor signals: desktop: a20m#, cpuslp#, ignne#, init#, intr, nmi, smi#, stpclk# mobile: a20m#, cpuslp#, dpslp#, dprstp#, ignne#, init#, intr, nmi, smi#, stpclk# v oh3 /v ol3 pci signals: ad[31:0], c/be[3:0]#, devsel#, frame#, irdy#, par, perr#, plock#, serr#, stop#, trdy# ac ?97/intel high definition audio signals: acz_rst#, acz_sdout, acz_sync intel high definition audio signals: acz_bit_clk v ol4 /v oh4 smbus signals: smbclk 1 , smbdata 1 system management signals: smlink[1:0] 1 v ol5 /v oh5 power management signals: desktop: pltrst#, slp_s3#, slp_s4#, slp_s5#, susclk#, sus_stat mobile: dprslpvr, pltrst#, slp_s3#, slp_s4#, slp_s5#, stp_cpu#, stp_pci#, susclk#, sus_stat gpio signals: desktop: gpo[24,23,20:18], gpio[34,33,28,27,25] mobile: gpo[24,23,19], gpio[34,33,28,27,25] other signals: spkr sata signal: sataled# processor interface signal: init3_3v# lan signals: lan_rstsync, lan_txd[2:0] eeprom signals: ee_cs, ee_dout, ee_shclk v ol6 /v oh6 usb signals : usbp[7:0][p,n] in low-speed and full-speed modes v omin7 /v omax7 pci express* data tx signals: pet[p,n][4:1] v omin8 /v omax8 sata signals: desktop: sata[3:0]tx[p,n] mobile: sata[2,0]tx[p,n] v ol9 /v oh9 lpc/firmware hub signals: lad[3:0]/fwh[3:0], lframe#/fwh[4] pci signals: desktop: pcirst#, gnt[3:0]#, gnt[4]/gpo[48], gnt[5]/gpo[17], gnt[6]/ gpo[16] mobile: pcirst#, clkrun#, gnt[3:0]#, gnt[4]/gpo[48], gnt[5]/gpo[17], gnt[6]/gpo[16] gpio signals: desktop: gpo[21], gpio[32] mobile: gpo[21] interrupt signals: serirq v ol10 /v oh10 processor signal: cpupwrgd/gpo[49] 1 v hsoi v hsoh v hsol v chirpj v chirpk usb signals: usbp[7:0][p:n] in high-speed mode
intel ? i/o controller hub 6 (ich6) family datasheet 741 electrical characteristics notes: 1. the cpupwrgd, serr#, pirq[h:a], smbdata, smbc lk, linkalert#, and smlink[1:0] signal has an open drain driver and sataled# has an open collector driver, and the v oh specification does not apply. this signal must have external pull up resistor. 2. for init3_3v only, for low current devices, the followi ng low current specification applies: vol5 max is 0.15v at iol5 of 2 ma. 3. pci express mvdiff p-p = |petp[x] ? petn[x]| 4. sata vdiff, tx (vomax/min8 is measured at t he sata connector on the tr ansmit side (generally, the motherboard connector), where sata mvdiff p-p = |sata[x]txp/rxp ? sata[x]txn/rxn| 5. maximum i ol for cpupwrgd is 12ma for short durations (<500ms per 1.5 s) and 9ma for long durations. table 22-7. dc output characteristics symbol parameter min max unit i ol / i oh notes v ol1 output low voltage ? 0.51 v tbd v oh1 output high voltage vcc3_3 ? 0.51 ? v tbd v ol2 output low voltage ? 0.255 v 3 ma v oh2 output high voltage v_cpu_io - 0.3 ? v -0.3 ma note 1 v ol3 output low voltage ? 0.1(vcc3_3) v 6 ma v oh3 output high voltage 0.9(vcc3_3) ? v -0.5 ma v ol4 output low voltage ? 0.4 v 4 ma v oh4 output high voltage vccsus3_3 - 0.5 ? v-2 ma note 1 v ol5 output low voltage ? 0.4 v 6 ma note 2 v oh5 output high voltage vcc3_3 - 0.5 ? v -2 ma note 1 v ol6 output low voltage ? 0.4 v 5 ma v oh6 output high voltage vcc3_3 ? 0.5 ? v-2 ma v omin7 minimum output voltage 800 ? mvdiff p-p note 3 v omax7 maximum output voltage ? 1200 mvdiff p-p note 3 v omin8 minimum output voltage 400 ? mvdiff p-p note 4 v omax8 maximum output voltage ? 600 mvdiff p-p note 4 v ol9 output low voltage ? 0.1(vcc3_3) v 1.5 ma v oh9 output high voltage 0.9(vcc3_3) ? v -0.5 ma v ol10 output low voltage ? 0.125 v 3 ma note 5 v oh10 output high voltage ?? note 1 v hsoi hs idle level ? 10.0 10.0 mv v hsoh hs data signaling high 360 440 mv v hsol hs data signaling low ? 10.0 10.0 mv v chirpj chirp j level 700 1100 mv v chirpk chirp k level ? 900 ? 500 mv
742 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. includes clk14, clk48, lan_clk and pciclk table 22-8. other dc characteristics symbol parameter min max unit notes v5ref ich6 core well reference voltage 4.75 5.25 v vcc3_3 i/o buffer voltage 3.135 3.465 v vcc1_5_a, vcc1_5_b, vccusbpll, vccsatapll, vccdmipll internal logic voltage 1.425 1.575 v v_cpu_io processor i/f 1.0 1.425 v v5ref_sus suspend well reference voltage 4.75 5.25 v vccsus3_3 suspend well i/o buffer voltage 3.135 3.465 v vcc2_5 internal logic voltage 2.375 2.625 v vccsus1_5 suspend well logic voltage 1.425 1.575 v vcclan3_3 (mobile only) lan controller i/o buffer voltage 3.135 3.465 v vcclan1_5 (mobile only) lan controller logic voltage 1.425 1.575 v vccrtc battery voltage 2.0 3.6 v v di differential input sensitivity 0.2 v |(usbpx+,usbpx ? )| v cm differential common mode range 0.8 2.5 v includes v di v crs output signal crossover voltage 1.3 2.0 v v se single ended rcvr threshold 0.8 2.0 v i li1 ata input leakage current ? 200 200 a (0 v < v in < 5v) i li2 pci_3v hi-z state data line leakage ? 10 10 a (0 v < v in < 3.3v) i li3 pci_5v hi-z state data line leakage ? 70 70 a max v in = 2.7 v min v in = 0.5 v i li4 input leakage current ? clock signals ? 100 +100 a note 1 c in input capacitance ? all other ? 12 pf f c = 1 mhz c out output capacitance ? 12 pf f c = 1 mhz c i/o i/o capacitance ? 12 pf f c = 1 mhz typical value c l xtal1 6 pf c l xtal2 6 pf
intel ? i/o controller hub 6 (ich6) family datasheet 743 electrical characteristics 22.4 ac characteristics 1 table 22-9. clock timings (sheet 1 of 2) sym parameter min max unit figure notes pci clock (pciclk) t1 period 30 33.3 ns 22-1 t2 high time 12 ns 22-1 t3 low time 12 ns 22-1 t4 rise time ? 3ns 22-1 t5 fall time ? 3ns 22-1 14 mhz clock (clk14) t6 period 67 70 ns 22-1 t7 high time 20 ? ns 22-1 t8 low time 20 ? ns 22-1 t41 rising edge rate 1.0 4.0 v/ns 1 t42 falling edge rate 1.0 4.0 v/ns 1 48 mhz clock (clk48) f clk48 operating frequency 48.000 ? mhz 2 t9 frequency tolerance ? 100 ppm t10 high time 7 ? ns 22-1 t11 low time 7 ? ns 22-1 t12 rise time ? 1.2 ns 22-1 t13 fall time ? 1.2 ns 22-1 smbus clock (smbclk) f smb operating frequency 10 16 khz t18 high time 4.0 50 us 22-16 3 t19 low time 4.7 ? us 22-16 t20 rise time ? 1000 ns 22-16 t21 fall time ? 300 ns 22-16
744 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. clk14 edge rates in a system as measured from 0.8 v to 2.0 v. 2. the clk48 expects a 40/60% duty cycle. 3. the maximum high time (t18 max) provide a simp le guaranteed method for devices to detect bus idle conditions. 4. the ich6 can tolerate a maximum of 2 ns of jitter from the input bitclk. note that clock jitter may impact system timing. if routing guidelines fo r ac ?97 were not followed as published in the platform design guides, system designers should ensure the input clock jitter does not negativel y impact the system timing. 5. bitclk rise and fall times are measured from 10%vdd and 90%vdd. 6. susclk duty cycle can range fr om 30% minimum to 70% maximum. ac ?97 clock (acz_bit_clk - ac ?97 mode) f ac97 operating frequency 12.288 mhz t26 input jitter (refer to clock chip specification) ? 2ns 4 t27 high time 36 45 ns 22-1 t28 low time 36 45 ns 22-1 t29 rise time 2.0 6.0 ns 22-1 5 t30 fall time 2.0 6.0 ns 22-1 5 acz_bit_clk (intel high definition audio mode) fhda operating frequency 24.0 mhz frequency tolerance ? 100 ppm t26a input jitter (refer to clock chip specification) ? 300 ppm t27a high time (measured at 0.75vcc) 18.75 22.91 ns 22-1 t28a low time (measured at 0.35vcc) 18.75 22.91 ns 22-1 sata clock (sata_clkp, sata_clkn) / dmi clock (dmi_clkp, dmi_clkn) t36 period 9.997 10.003 ns t37 rise time 175 700 ps t38 fall time 175 700 ps suspend clock (susclk) f susclk operating frequency 32 khz 6 t39 high time 10 ? us 6 t40 low time 10 ? us 6 table 22-9. clock timings (sheet 2 of 2) sym parameter min max unit figure notes
intel ? i/o controller hub 6 (ich6) family datasheet 745 electrical characteristics notes: 1. refer to note 3 of table 4-4 in section 4.2.2.2 and note 2 of table 4-6 in section 4.2.3.2 of the pci local bus specification, revision 2.3 for measurement details. table 22-10. pci interface timing sym parameter min max units figure notes t40 ad[31:0] valid delay 2 11 ns 22-2 1 t41 ad[31:0] setup time to pciclk rising 7 ? ns 22-3 t42 ad[31:0] hold time from pciclk rising 0 ? ns 22-3 t43 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, devsel# valid delay from pciclk rising 211ns 22-2 1 t44 c/be[3:0]#, frame#, trdy#, irdy#, stop#, par, perr#, plock#, idsel, devsel# output enable delay from pciclk rising 2 ? ns 22-6 t45 c/be[3:0]#, frame#, trdy#, irdy#, stop#, perr#, plock#, devsel#, gnt[a:b]# float delay from pciclk rising 228ns 22-4 t46 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, setup time to pciclk rising 7 ? ns 22-3 t47 c/be[3:0]#, frame#, trdy#, irdy#, stop#, serr#, perr#, devsel#, req[a:b]# hold time from pclkin rising 0 ? ns 22-3 t48 pcirst# low pulse width 1 ? ms 22-5 t49 gnt[6:0]# valid delay from pciclk rising 2 12 ns t50 req[6:0]# setup time to pciclk rising 12 ? ns table 22-11. ide pio mode timings sym parameter mode 0 (ns) mode 1 (ns) mode 2 (ns) mode 3 (ns) mode 4 (ns) figure t60 cycle time (min) 600 383 240 180 120 22-7 t61 addr setup to diow#/dior# (min) 70 50 30 30 25 22-7 t62 dirw#/dior# (min) 165 125 100 80 70 22-7 t62i diow#/dior# recovery time (min) ??? 70 25 22-7 t63 diow# data setup (min) 60 45 30 30 20 22-7 t64 diow# data hold (min) 30 20 15 10 10 22-7 t65 dior# data setup (min) 50 35 20 20 20 22-7 t66 dior# data hold (min) 5 5 5 5 5 22-7 t66z dior# data tri-state (max) 30 30 30 30 30 22-7 t69 diow#/dior# to address valid hold (min) 20 15 10 10 10 22-7 t60rd read data valid to iordy active (min) 0 0 0 0 0 22-7 t60aiordy setup 3535353535 22-7 t60b iordy pulse width (max) 1250 1250 1250 1250 1250 22-7 t60c iordy assertion to release (max) 5 5 5 5 5 22-7
746 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics table 22-12. ide multiword dma timings sym parameter mode 0 (ns) mode 1 (ns) mode 2 (ns) figure t70 cycle time (min) 480 150 120 22-8 t70d dior#/diow# (min) 215 80 70 22-8 t70e dior# data access (max) 150 60 50 22-8 t70f dior# data hold (min) 5 5 5 22-8 t70g dior#/diow# data setup (min) 100 30 20 22-8 t70h diow# data hold (min) 20 15 10 22-8 t70i ddack# to dior#/diow# setup (min) 0 0 0 22-8 t70j dior#/diow# to ddack# hold (min) 20 5 5 22-8 t70kr dior# negated pulse width (min) 50 50 25 22-8 t70kw diow# negated pulse width (min) 215 50 25 22-8 t70lr dior# to ddreq delay (max) 120 40 35 22-8 t70lw diow# to ddreq delay (max) 40 40 35 22-8 t70m dcs1#/dcs3# valid to dior#/diow# (min) 50 30 25 22-8 t70n dcs1#/dcs3# hold (min) 15 10 10 22-8 t70z ddack# to tri-state (max) 20 25 25 22-8
intel ? i/o controller hub 6 (ich6) family datasheet 747 electrical characteristics table 22-13. ultra ata timing (mode 0, mode 1, mode 2) (sheet 1 of 2) sym parameter 1 mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max t80 sustained cycle time (t2cyctyp) 240 160 120 sender connector t81 cycle time (tcyc) 112 ? 73 ? 54 ? end recipient connector 22-10 t82 two cycle time (t2cyc) 230 ? 153 ? 115 ? sender connector 22-10 t83a data setup time (tds) 15 ? 10 ? 7 ? recipient connector 22-10 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 14.7 ? 9.7 ? 6.8 ? ich6 ball t84a data hold time (tdh) 5 ? 5 ? 5 ? recipient connector 22-10 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 ? 4.8 ? 4.8 ? ich6 ball t85a data valid setup time (tdvs) 70 ? 48 ? 31 ? sender connector 22-10 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 72.9 ? 50.9 ? 33.9 ? ich6 ball t86a data valid hold time (tdvh) 6.2 ? 6.2 ? 6.2 ? sender connector 22-10 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9 ? 9 ? 9 ? ich6 ball t87 limited interlock time (tli) 0 150 0 150 0 150 note 2 22-12 t88 interlock time w/ minimum (tmli) 20 ? 20 ? 20 ? host connector 22-12 t89 envelope time (tenv) 20 70 20 70 20 70 host connector 22-9 t90 ready to pause time (trp) 160 ? 125 ? 100 ? recipient connector 22-11 t91 dmack setup/hold time (tack) 20 ? 20 ? 20 ? host connector 22-9 , 22-12 t92a crc word setup time at host (tcvs) 70 ? 48 ? 31 ? host connector t92b crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 ? 6.2 ? 6.2 ? host connector
748 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. the specification symbols in parenthes es correspond to the at attachment ? 6 with packet interface (ata/atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring these timing parameters. t93 strobe output released-to- driving to the first transition of critical timing (tzfs) 0 ? 0 ? 0 ? device connector 22-12 t94 data output released-to-driving until the first tunisian of critical timing (tdzfs) 70 ? 48 ? 31 ? sender connector 22-9 t95 unlimited interlock time (tui) 0 ? 0 ? 0 ? host connector 22-9 t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) ? 10 ? 10 ? 10 note 2 t96b minimum time for drivers to assert or negate (from released) (tzad) 0 ? 0 ? 0 ? device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) ? 75 ? 70 ? 60 sender connector 22-9 t98a maximum time before releasing iordy (tiordyz) ? 20 ? 20 ? 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 0 ? 0 ? 0 ? device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 ? 50 ? 50 ? sender connector 22-11 table 22-13. ultra ata timing (mode 0, mode 1, mode 2) (sheet 2 of 2) sym parameter 1 mode 0 (ns) mode 1 (ns) mode 2 (ns) measuring location figure min max min max min max
intel ? i/o controller hub 6 (ich6) family datasheet 749 electrical characteristics table 22-14. ultra ata timing (mode 3, mode 4, mode 5) (sheet 1 of 2) sym parameter 1 mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure min max min max min max t80 sustained cycle time (t2cyctyp) 90 60 40 sender connector t81 cycle time (tcyc) 39 ? 25 ? 16.8 ? end recipient connector 22-10 t82 two cycle time (t2cyc) 86 ? 57 ? 38 ? sender connector 22-10 t83 data setup time (tds) 7 ? 5 ? 4.0 ? recipient connector 22-10 t83b recipient ic data setup time (from data valid until strobe edge) (see note 2) (tdsic) 6.8 ? 4.8 ? 2.3 ? ich6 balls t84 data hold time (tdh) 5 ? 5 ? 4.6 ? recipient connector 22-10 t84b recipient ic data hold time (from strobe edge until data may become invalid) (see note 2) (tdhic) 4.8 ? 4.8 ? 2.8 ? ich6 balls t85 data valid setup time (tdvs) 20 ? 6.7 ? 4.8 ? sender connector 22-9 22-10 t85b sender ic data valid setup time (from data valid until strobe edge) (see note 2) (tdvsic) 22.6 ? 9.5 ? 6.0 ? ich6 balls t86 data valid hold time (tdvh) 6.2 ? 6.2 ? 4.8 ? sender connector 22-9 22-10 t86b sender ic data valid hold time (from strobe edge until data may become invalid) (see note 2) (tdvhic) 9.0 ? 9.0 ? 6.0 ? ich6 balls t87 limited interlock time (tli) 0 100 0 100 0 75 note 2 22-12 t88 interlock time w/ minimum (tmli) 20 ? 20 ? 20 ? host connector 22-12 t89 envelope time (tenv) 20 55 20 55 20 50 host connector 22-10 t90 ready to pause time (trp) 100 ? 100 ? 85 ? recipient connector 22-11 t91 dmack setup/hold time (tack) 20 ? 20 ? 20 ? host connector 22-12 t92a crc word setup time at host (tcvs) 20 ? 6.7 ? 10 ? host connector t92b crc word hold time at sender crc word valid hold time at sender (from dmack# negation until crc may become invalid) (see note 2) (tcvh) 6.2 ? 6.2 ? 10.0 ? host connector
750 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. the specification symbols in parenthes es correspond to the at attachment ? 6 with packet interface (ata/ atapi ? 6) specification name. 2. see the at attachment ? 6 with packet interface (ata/atapi ? 6) specification for further details on measuring these timing parameters. t93 strobe output released-to- driving to the first transition of critical timing (tzfs) 0 ? 0 ? 35 ? device connector 22-12 t94 data output released-to- driving until the first transition of critical timing (tdzfs) 20.0 ? 6.7 ? 25 ? sender connector t95 unlimited interlock time (tui) 0 ? 0 ? 0 ? host connector t96a maximum time allowed for output drivers to release (from asserted or negated) (taz) ? 10 ? 10 ? 10 note 2 t96b drivers to assert or negate (from released) (tzad) 0 ? 0 ? 0 ? device connector t97 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy#) (trfs) ? 60 ? 60 ? 50 sender connector t98a maximum time before releasing iordy (tiordyz) ? 20 ? 20 ? 20 device connector t98b minimum time before driving iordy (see note 2) (tziordy) 0 ? 0 ? 0 ? device connector t99 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) (tss) 50 ? 50 ? 50 ? sender connector 22-11 table 22-14. ultra ata timing (mode 3, mode 4, mode 5) (sheet 2 of 2) sym parameter 1 mode 3 (ns) mode 4 (ns) mode 5 (ns) measuring location figure min max min max min max
intel ? i/o controller hub 6 (ich6) family datasheet 751 electrical characteristics notes: 1. full-speed data rate has minimum of 11.97 mb/s and maximum of 12.03 mb/s. 2. driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. 3. timing difference between the differential data signals. 4. measured at crossover point of differential data signals. 5. measured at 50% swing point of data signals. 6. measured from last crossover point to 50% sw ing point of data line at leading edge of eop. 7. low-speed data rate has a minimum of 1.48 mb/s and a maximum of 1.52 mb/s. 8. measured from 10% to 90% of the data signal. table 22-15. universal serial bus timing sym parameter min max units fig notes full-speed source 1 t100 usbpx+, usbpx- driver rise time 4 20 ns 22-13 2, c l = 50 pf t101 usbpx+, usbpx- driver fall time 4 20 ns 22-13 2, c l = 50 pf t102 source differential driver jitter to next transition for paired transitions ? 3.5 ? 4 3.5 4 ns ns 22-14 3, 4 t103 source se0 interval of eop 160 175 ns 22-15 5 t104 source jitter for differential transition to se0 transition ? 25 ns 6 t105 receiver data jitter tolerance to next transition for paired transitions ? 18.5 ? 9 18.5 9 ns ns 22-14 4 t106 eop width: must accept as eop 82 ? ns 22-15 5 t107 width of se0 interval during differential transition ? 14 ns low-speed source 7 t108 usbpx+, usbpx ? driver rise time 75 300 ns 22-13 2, 8 c l = 50 pf c l = 350 pf t109 usbpx+, usbpx ? driver fall time 75 300 ns 22-13 2,8 c l = 50 pf c l = 350 pf t110 source differential driver jitter to next transition for paired transitions ? 25 ? 14 25 14 ns ns 22-14 3, 4 t111 source se0 interval of eop 1.25 1.50 s 22-15 5 t112 source jitter for differential transition to se0 transition ? 40 100 ns 6 t113 receiver data jitter tolerance to next transition for paired transitions ? 152 ? 200 152 200 ns ns 22-14 4 t114 eop width: must accept as eop 670 ? ns 22-15 5 t115 width of se0 interval during differential transition ? 210 ns
752 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. 20% ? 80% at transmitter 2. 80% ? 20% at transmitter 3. as measured from 100 mv differential cross points of last and first edges of burst. 4. operating data period during out-of-band burst transmissions. note: 1. t134 has a minimum timing for i 2 c of 0 ns, while the minimum timing for smbus is 300 ns. 2. a device will timeout when any clock low exceeds this value. 3. t137 is the cumulative time a slave device is allow ed to extend the clock cycles in one message from the initial start to stop. if a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 4. t138 is the cumulative time a ma ster device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. table 22-16. sata interface timings sym parameter min max units figure notes ui operating data period 666.43 670.12 ps rise time 0.2 0.41 ui 1 fall time 0.2 0.41 ui 2 tx differential skew ? 20 ps comreset 310.4 329.6 ns 3 comwake transmit spacing 103.5 109.9 ns 3 oob operating data period 646.67 686.67 ns 4 table 22-17. smbus timing sym parameter min max units fig notes t130 bus tree time between stop and start condition 4.7 ? s 22-16 t131 hold time after (repeated) start condition. after this period, the first clock is generated. 4.0 ? s 22-16 t132 repeated start condition setup time 4.7 ? s 22-16 t133 stop condition setup time 4.0 ? s 22-16 t134 data hold time 0 ? ns 22-16 1 t135 data setup time 250 ? ns 22-16 t136 device time out 25 35 ms 2 t137 cumulative clock low extend time (slave device) ? 25 ms 22-17 3 t138 cumulative clock low extend time (master device) ? 10 ms 22-17 4
intel ? i/o controller hub 6 (ich6) family datasheet 753 electrical characteristics 1 table 22-18. ac ?97 / intel ? high definition audio timing sym parameter min max units fig notes t140 acsdin[2:0] setup to falling edge of bitclk 10 ? ns 22-30 t141 acsdin[2:0] hold from falling edge of bitclk 10 ? ns 22-30 t142 acsync, acsdoutvalid delay from rising edge of bitclk ? 15 ns 22-30 t143 time duration for which sd0 is valid before bitclk edge. 7 ? ns 22-29 t144 time duration for which sdo is valid after bitclk edge. 7 ? ns 22-29 t145 setup time for sdi at rising edge of bitclk 15 ? ns 22-29 t146 hold time for sdi at the rising edge of bitclk 0 ? ns 22-29 table 22-19. lpc timing sym parameter min max units fig notes t150 lad[3:0] valid delay from pciclk rising 2 11 ns 22-2 t151 lad[3:0] output enable delay from pciclk rising 2 ? ns 22-6 t152 lad[3:0] float delay from pciclk rising 28 ns 22-4 t153 lad[3:0] setup time to pciclk rising 7 ? ns 22-3 t154 lad[3:0] hold time from pciclk rising 0 ? ns 22-3 t155 ldrq[1:0]# setup time to pciclk rising 12 ? ns 22-3 t156 ldrq[1:0]# hold time from pciclk rising 0 ? ns 22-3 t157 lframe# valid delay from pciclk rising 2 12 ns 22-2 table 22-20. miscellaneous timings sym parameter min max units fig notes t160 serirq setup time to pciclk rising 7 ? ns 22-3 t161 serirq hold time from pciclk rising 0 ? ns 22-3 t162 ri#, extsmi#, gpi, usb resume pulse width 2 ? rtcclk 22-5 t163 spkr valid delay from osc rising ? 200 ns 22-2 t164 serr# active to nmi active ? 200 ns t165 ignne# inactive from ferr# inactive ? 230 ns
754 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics table 22-21. (power sequencing and reset signal timings (sheet 1 of 2) sym parameter min max units fig notes t200 vccrtc active to rtcrst# inactive 5 ? ms 22-18 22-19 t201 v5ref_sus active to vccsus3_3 active 0 ? ms 22-18 22-19 1 t202 vccsus3_3 active to vccsus1_5 active ??? 22-18 22-19 2 t203 vccrtc supply active to vccsus supplies active 0 ? ms 22-18 22-19 3 t204 vccsus supplies active to lan_rst# inactive, rsmrst# inactive (desktop only) 10 ? ms 22-18 22-20 t205 vccsus supplies active to rsmrst# inactive (mobile only) 5 ? ms 22-19 22-21 t206 vcclan3_3 active to vcclan1_5 active (mobile only) ??? 22-19 4 t207 vccsus supplies active to vcclan supplies active (mobile only) 0 ? ms 22-19 5 t208 vcclan supplies active to lan_rst# inactive (mobile only) 10 ? ms 22-19 t209 v5ref active to vcc3_3 active 0 ? ms 22-18 22-19 1 t210 vcc3_3 active to vcc2_5 active ??? 22-18 22-19 6 t211 vcc1_5 active to v_cpu_io active ??? 22-18 22-19 7 t212 vcclan supplies active to vcc supplies active (mobile only) 0 ? ms 22-19 5 t213 vccsus supplies active to vcc supplies active (desktop only) 0 ? ms 22-18 3 t214 vcc supplies active to pwrok (s3 cold only) note: pwrok assertion indicates that pciclk has been stable for 1 ms. 99 ? ms 22-18 22-19 22-20 22-21 22-23 22-24 22-25 22-26 t214a v_cpu_io active to vrmpwrgd 10 ms t215 vcc active to stpclk# and cpuslp# inactive (desktop only) ? 50 ns 22-20 22-23 22-24 t216 vcc active to dprslpvr inactive and stpclk#, cpuslp#, stp_cpu#, stp_pci#, dpslp#, dprstp# inactive (mobile only) ? 50 ns 22-21 22-25 22-26
intel ? i/o controller hub 6 (ich6) family datasheet 755 electrical characteristics notes: 1. the v5ref supply must power up before its associated 3.3 v supply within 0.7 v, and must power down after the 3.3 v supply within 0.7v. see section 2.22.3.1 for details. 2. the associated 3.3 v and 1.5 v supplies are assumed to power up or down ?together?. if the integrated vccsus1_5 voltage regulator is not used: a ) vccsus3_3 must power up before vccsus1_5 or after vccsus1_5 within 0.7 v, b ) vccsus1_5 must power down before vccsus 3_3 or after vccsus3_3 within 0.7 v. 3. the vccsus supplies must never be active while the vccr tc supply is inactive. 4. (mobile only) ? a ) vcclan3_3 must power up before vcclan1_5 or after vcclan1_5 within 0.7 v, b ) vcclan1_5 must power down before vcclan3_3 or after vcclan3_3 within 0.7v. 5. (mobile only) - vcc or vcclan suppl ies must never be active while the vccsus supplies are inactive, and the vcc supplies must never be active wh ile the vcclan supplies are inactive. 6. if the integrated vcc2_5 voltage regulator is not used: a ) vcc3_3 must power up before vcc2_5 or after vcc2_5 within 0.7 v, b ) vcc2_5 must power down before vcc3_3 or after vcc3_3 within 0.7 v. 7. a ) vcc1_5 must power up before v_cpu_io or after v_cpu_io within 0.3 v, b ) v_cpu_io must power down before vcc1_5 or after vcc1_5 within 0.7 v. 8. init# value determined by value of the cpu bist e nable bit (chipset configuration register offset 3414h: bit 2). 9. these transitions are clocked off the inter nal rtc. 1 rtc clock is approximately 32 us. t217 pwrok and vrmpwrgd active and sys_reset# inactive to sus_stat# inactive and processor i/f signals latched to strap value 32 38 rtcclk 22-20 22-21 22-23 22-24 22-25 22-26 8, 9 t218 sus_stat# inactive to pltrst# and pcirst# inactive 23rtcclk 22-20 22-21 22-23 22-24 22-25 22-26 9 t228 acz_rst# active low pulse width 1 ? us t229 acz_rst# inactive to acz_bit_clk startup delay 162.8 ? ns table 22-21. (power sequencing and reset signal timings (sheet 2 of 2) sym parameter min max units fig notes
756 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics table 22-22. power management timings (sheet 1 of 3) sym parameter min max units fig notes t230 vccsus active to slp_s5#, slp_s4#, slp_s3#, sus_stat#, pltrst# and pcirst# active ? 50 ns 22-20 22-21 t231 t232 rsmrst# inactive to susclk running, slp_s5# inactive ? 110 ms 22-20 22-21 1 t233 slps5# inactive to slp_s4# inactive see note below 22-20 22-21 2 t234 slps4# inactive to slp_s3# inactive 1 2 rtcclk 22-20 22-21 3 t250 processor i/f signals la tched prior to stpclk# active (mobile only) 0 ? 22-27 22-28 22-29 4 t251 bus master idle to cpu_slp# active (mobile only) 2.88 ? pciclk 22-28 22-29 5, 6 t252 cpuslp# active to dpslp# active (mobile only) 16 ? pciclk 22-28 22-29 5 t253 dpslp# active to stp_cpu# active (mobile only) 11pciclk 22-28 22-29 5 t254 stp_cpu# active to processor clock stopped (mobile only) 0 ? pciclk 22-28 22-29 5, 7 t255 stp_cpu# active to dprstp#, dprslpvr active (mobile only) 0 ? 22-29 t265 break event to dprstp#, dprslpvr inactive (c4 exit) (mobile only) 1.5 1.8 s 22-29 8 t266 dprslpvr, dprstp# inactive to stp_cpu# inactive and cpu vcc ramped (mobile only) programable. see d31:f0:aa, bits 3:2 s 22-29 t267 break event to stp_cpu# inactive (c3 exit) (mobile only) 6 note 14 pciclk 22-28 5, 9,10 t268 stp_cpu# inactive to processor clock running (mobile only) 03pciclk 22-28 22-29 5, 7 t269 stp_cpu# inactive to dpslp# inactive (mobile only) 11pciclk 22-28 22-29 5,11 t270 dpslp# inactive to cpu_slp# inactive (mobile only) program- mable. see d31:f0:aah, bits 1:0 s 22-28 22-29 11 t271 s1 wake event to cpuslp# inactive (desktop only) 125pciclk 22-22 5 t272 cpuslp# inactive to stpclk# inactive (mobile only) 0 ? s 22-28 22-29 t273 break event to stpclk# inactive (c2 exit) (mobile only) 0 ? ns 22-27
intel ? i/o controller hub 6 (ich6) family datasheet 757 electrical characteristics t274 stpclk# inactive to proc essor i/f signals unlatched (mobile only) 89pciclk 22-27 22-28 22-29 4, 5 t280 stpclk# active to dmi message 0 ? pciclk 22-22 22-23 22-24 22-25 22-26 12 t281 dmi message to cpuslp# active 60 63 pciclk 22-22 5 t283 dmi message to sus_stat# active 2 ? rtcclk 22-23 22-24 22-25 22-26 3 t284 sus_stat# active to pltrst#, pcirst# active (desktop only) 717rtcclk 22-23 22-24 3 t285 sus_stat# active to stp_pci# active (mobile only) 210rtcclk 22-25 22-26 3 t286 stp_pci# active to pltrst# and pcirst# active (mobile only) 57rtcclk 22-25 22-26 3 t287 pltrst#, pcirst# active to slp_s3# active 1 2 rtcclk 22-23 22-24 22-25 22-26 3 t288 (s3 cold configuration only) slp_s3# active to pwrok, vrmpwrgd inactive (mobile only) 0 ? ms 22-25 13 t289 slp_s3# active to pwrok, vrmpwrgd inactive (desktop only) 0 ? ms 22-23 13 t290 (s3 cold configuration only) pwrok, vrmpwrgd inactive to vcc supplies inactive (mobile only) 20 ? ns 22-25 t291 slp_s3# active to slp_s4# active 1 2 rtcclk 22-23 22-24 22-25 22-26 3 t292 (s3 hot configuration only) slp_s3# active to vrmpwrgd inactive 0 ? ms 22-24 22-26 13 t293 (s3 hot configuration only) pwrok, vrmpwrgd inactive to vcc supplies inactive 20 ? ns 22-24 22-26 t294 pwrok, vrmpwrgd inactive to vcc supplies inactive (desktop only) 20 ? ns 22-23 t295 slp_s4# active to slp_s5# active 1 ? 2rtcclk 22-23 22-24 22-25 22-26 3, 14 t296 wake event to slp_s5# inactive 1 10 rtcclk 22-23 22-24 22-25 22-26 3 table 22-22. power management timings (sheet 2 of 3) sym parameter min max units fig notes
758 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics notes: 1. if there is no rtc battery in the system, so vccrtc and the vccsus supplies come up together, the delay from rtcrst# and rsmrst# inactive to susclk toggling may be as much as 2.5 s. 2. the min/max times depend on the programming of the ?slp_s4# minimum assertion width? and the ?slp_s4# assertion stretch enabl e bits (d31:f0:a4h bits 5:3). 3. these transitions are clock ed off the internal rtc. 1 rtc clock is approximately 32 s. 4. note that this does not apply for synchronous smis. 5. these transitions are clock ed off the 33 mhz pciclk. 1 pciclk is approximately 30ns. 6. if the (g)mch does not have the cpuslp# signal, then the minimu m value can be 0 s. 7. this is a clock generator specification 8. this is non-zero to enforce the minimum assert time for dprslpvr. if the minimum assert time for dprslpvr has been met, then this is permitted to be 0. 9. this is non-zero to enforce the minimum assert time for stp_cpu#. if the minimum assert time for stp_cpu# has been met, then this is permitted to be 0. 10.this value should be at most a few clocks greater than the minimum. 11.this value is programmable in multiples of 1024 pci clocks. maximum is 819 2 pci clocks (245.6 s). 12.the ich6 stpclk# assertion will trigger the processor to send a stop grant acknowledge cycle. the timing for this cycle getting to the ich6 is dependant on the processor and the memory controller. 13.the ich6 has no maximum timing requirement for this tr ansition. it is up to the system designer to determine if the slp_s3#, slp_s4# and slp_s5# si gnals are used to control the power planes. 14.if the transition to s5 is due to power button override, slp_s3#, slp_s4# and slp_s5# are asserted together similar to timing t287 (pcirst# active to slp_s3# active). t297 slp_s5# inactive to slp_s4# inactive see note below 22-23 22-24 22-25 22-26 2 t298 slp_s4# inactive to slp_s3# inactive 1 2 rtcclk 22-23 22-24 22-25 22-26 3 t299 s4 wake event to slp_s4# inactive (s4 wake) see note below 22-23 22-24 22-25 22-26 2 t300 s3 wake event to slp_s3# inactive (s3 wake) 0 small as possi ble rtcclk 22-23 22-24 22-25 22-26 3 t301 cpuslp# inactive to stpclk# inactive (desktop only) 8 ? pciclk 22-22 t302 (s3 hot configuration only) slp_s3# inactive to ich6 check for pwrok active 45msec 22-23 22-24 22-25 22-26 other timings t310 thrmtrip# active to slp_s3#, slp_s4#, slp_s5# active ? 2 pci clk table 22-22. power management timings (sheet 3 of 3) sym parameter min max units fig notes
intel ? i/o controller hub 6 (ich6) family datasheet 759 electrical characteristics 22.5 timing diagrams figure 22-1. clock timing figure 22-2. valid delay from rising clock edge figure 22-3. setup and hold times 2.0v 0.8v period high time low time fall time rise time clock 1.5v valid delay vt output clock vt input hold time setup time vt 1.5v
760 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-4. float delay figure 22-5. pulse width figure 22-6. output enable delay input vt output float delay vt pulse width vt clock output output enable delay vt 1.5v
intel ? i/o controller hub 6 (ich6) family datasheet 761 electrical characteristics figure 22-7. ide pio mode figure 22-8. ide multiword dma cs0#, cs1#, da[2:0] dior#/diow# dd[15:0] writes dd[15:0] reads iordy iordy t60 t61 t62 t69 t62i t63 t64 t65 t66 t66z t60a t60b t60rd t60c t60c cs0#/ cs1# ddreq ddack# dior#/diow# dd[15:0] read dd[15:0] write t70m t70n t70 t70l t70i t70d t70k t70j t70e t70f t70z t70g t70g t70h
762 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-9. ultra ata mode (drive initiating a burst read) figure 22-10. ultra ata mode (sustained burst) dmarq (drive) t91 t89 t89 dmack# (host) stop (host) dmardy# (host) strobe (drive) dd[15:0] da[2:0], cs[1:0] t96 t98 t94 t95 t85 t86 t97 t99b strobe @ sender t81 data @ sender t86 t85 t86 t85 t81 t82 t86 strobe @ receiver data @ receiver t84 t83 t84 t83 t84 t99e t99e t99e t99d t99d t99g t99g t99g t99f t99f
intel ? i/o controller hub 6 (ich6) family datasheet 763 electrical characteristics figure 22-11. ultra ata mode (pausing a dma burst) figure 22-12. ultra ata mode (terminating a dma burst) t90 strobe data s top (host) dmardy# t99 t88 stop (host) strobe (host) dmardy# (drive) data (host) dmack# (host) t91 t87 dmarq (drive) crc t99c t87 t99a t91 t92 t93
764 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-13. usb rise and fall times figure 22-14. usb jitter figure 22-15. usb eop width differential data lines 90% 10% 10% 90% t r t f rise time fall time c l c l low-speed: 75 ns at c l = 50 pf, 300 ns at c l = 350 pf full-speed: 4 to 20 ns at c l = 50 pf high-speed: 0.8 to 1.2 ns at c l = 10 pf paired transitions consecutive transitions crossover points t period differential data lines jitter differential data lines eop width data crossover level tperiod
intel ? i/o controller hub 6 (ich6) family datasheet 765 electrical characteristics figure 22-16. smbus transaction figure 22-17. smbus timeout t130 smbclk smbdata t131 t19 t134 t20 t21 t135 t132 t18 t133 start stop t137 clk ack clk ack t138 t138 smbclk smbdata
766 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-18. power sequencing and reset signal timings (desktop only) vccrtc vcc2_5, v_cpu_io vccsus3_3 rtcrst# lan_rst#, rsmrst# t200 t201 v5ref_sus v5ref pwrok vcc3_3, vcc1_5 vccsus1_5 t203 t204 t209 t210 and t211 t214 t202 t213
intel ? i/o controller hub 6 (ich6) family datasheet 767 electrical characteristics figure 22-19. power sequencing and reset signal timings (mobile only) vccrtc vcc2_5 v_cpu_io vccsus3_3 rtcrst# rsmrst# t200 t201 v5ref_sus v5ref pwrok vcc3_3 vcc1_5 vccsus1_5 t203 t202 t209 t212 t214 lan_rst# vcclan1_5 vcclan3_3 t207 t208 t205 t210 and t211 t206
768 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-20. g3 (mechanical off) to s0 timings (desktop only) vccsus1_5 running susclk slp_s3# vcc pwrok sus_stat# pltrst# , pcirst# processor i/f signals stpclk#, cpuslp# dmi message rsmrst# lan_rst# t204 t214 t217 t218 t230 t231 t215 g3 s3 s0 s0 state g3 s5 system state s4 slp_s4# slp_s5# t232 t233 t234 vccsus3_3 strap values normal operation
intel ? i/o controller hub 6 (ich6) family datasheet 769 electrical characteristics figure 22-21. g3 (mechanical off) to s0 timings (mobile only) figure 22-22. s0 to s1 to s0 timing slp_s3# vcc, vcclan pwrok, lan_rst# sus_stat# pltrst#, pcirst# processor i/f signals stpclk#, cpuslp#, stp_cpu#, stp_pci#, dpslp#, dprstp# dmi message system state running strap values normal operation t205 t217 t218 t230 t231 t216 s3 s0 s0 state g3 s5 s4 t232 t233 t234 t214 main battery removed (g3) vccsus1_5 susclk rsmrst# slp_s4# slp_s5# vccsus3_3 t280 t281 t271 t301 s0 s0 s1 s1 s1 s0 s0 state stpclk# dmi message cpuslp# wake event
770 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-23. s0 to s5 to s0 timings, s3 cold (desktop only) stpclk# dmi message sus_stat# pltrst#, pcirst# slp_s3# (s3 cold config) slp_s5# wake event pwrok, vrmpwrgd vcc s0 s0 s3 s3 s5 s0 t283 t284 t287 t289 t294 t214 t217 t218 t215 t280 slp_s4# t291 t295 t297 t298 s4 s4 s3 s3/s4/s5 s0 t296 t300 t299
intel ? i/o controller hub 6 (ich6) family datasheet 771 electrical characteristics figure 22-24. s0 to s5 to s0 timings, s3 hot (desktop only) stpclk# dmi message sus_stat# pltrst#, pcirst# slp_s3# (s3 hot config) slp_s5# wake event vrmpwrgd vcc s0 s0 s3 s3 s5 s0 t283 t284 t287 t292 t293 t217 t218 t215 t280 slp_s4# t291 t295 t297 t298 s4 s4 s3 s3/s4/s5 s0 t296 t300 t299 t302
772 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-25. s0 to s5 to s0 timings, s3 cold (mobile only) stp_cpu#, cpuslp#, dpslp#, dprstp# pltrst# pcirst# slp_s3# (s3 cold board config) slp_s5# wake event pwrok, vrmpwrgd vcc s0 s0 s3 s3 s5 s3/s4/s5 s0 s0 t295 t288 t290 t296 t214 t217 t218 stp_pci# stpclk# dmi message dprslpvr t280 t283 t285 t287 t286 sus_stat# s4 slp_s4# t291 t297 t300 t298 t216 t299
intel ? i/o controller hub 6 (ich6) family datasheet 773 electrical characteristics figure 22-26. s0 to s5 to s0 timings, s3 hot (mobile only) figure 22-27. c0 to c2 to c0 timings (mobile only) stp_cpu#, cpuslp#, dpslp#, dprstp# pltrst# pcirst# slp_s3# (s3 hot board config) slp_s5# wake event vrmpwrgd vcc s0 s0 s3 s3 s5 s3/s4/s5 s0 s0 t295 t292 t293 t296 t217 t218 stp_pci# stpclk# dmi message dprslpvr t280 t283 t285 t287 t286 sus_stat# s4 slp_s4# t291 t297 t300 t298 t216 t299 t302 unlatched latched unlatched cpu i/f signals stpclk# break event t250 t273 t274
774 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics figure 22-28. c0 to c3 to c0 timings (mobile only) figure 22-29. c0 to c4 to c0 timings (mobile only) unlatched latched cpu i/f signals stpclk# break event bus master cpuslp# stp_cpu# t250 t251 t252 t253 t268 t269 t274 t272 active idle dpslp# t270 unlatched cpu clocks running running stopped t267 t254 unlatched cpu i/f signals stpclk# break event bus master cpuslp# stp_cpu# t250 t251 t252 t253 t266 t269 t274 t270 dprstp# dpslp# active idle dprslpvr unlatched t272 cpu clocks running running t254 t255 cpu vcc t265 stopped t268 latched
intel ? i/o controller hub 6 (ich6) family datasheet 775 electrical characteristics figure 22-30. ac ?97 data input and output timings v oh v ol acz_sdout acz_sdin[2:0] acz_sync acz_bit_clk v ih v il t co t hold t setup figure 22-31. intel ? high definition audio in put and output timings acz_sdout acz_sdin[2:0] acz_bit_clk t143 t143 t144 t144 t145 t146
776 intel ? i/o controller hub 6 (i ch6) family datasheet electrical characteristics
intel ? i/o controller hub 6 (ich6) family datasheet 777 package information 23 package information the ich6 package info rmation is shown in figure 23-1 and figure 23-2 . the figures are preliminary and subject to change. figure 23-1. intel ? ich6 package (top and side views) pin a1 identifier pin a1 corner 31.00 0.10 26.00 0.20 top view 45 chamfer (4 places) 22.10 ref 0.127 a -a- -b- 0.127 a 22.10 ref 26.00 0.20 31.00 0.10 3 x ? 1.00 thru 0.61 0.06 side view seating plane (see note 3) -c- 30 0.50 0.10 1.17 0.05 2.28 0.21 0.20 0.15 c notes: 1. all dimensions are in millimeters. 2. all dimensions and tolerances conform to ansi y14.5m - 1982. 3. primary datum (-c-) and seating plane are defined by the sperical crowns of the solder balls. 1.0 dia. x 0.15 depth 9.0 x 9.0 from center line 1.70 au gate
778 intel ? i/o controller hub 6 (i ch6) family datasheet package information figure 23-2. intel ? ich6 package (bottom view) pin a1 corner b o tt om vi ew b c d e f g h j k l p r t u v y ab aa n w m notes: 1. all dimensions are in millimeters. 2. all dimensions and tolerances conform to ansi y14.5m - 1982. 3. dimension is measured at the maximum solder ball diameter. parallel to datum (-c-) on side view illustration. ac ad a 0.70 ? 0.50 note 3 s b s a c s ? 0.30 0.97 0.97 2 10 16 20 22 3 5 7 9 11 13 15 17 19 1 21 4 6 18 8 12 14 23 24 26 25 27 ae af 1.118 1.118 ag 0.74 ref 0.74 ref
intel ? i/o controller hub 6 (ich6) family datasheet 779 testability 24 testability 24.1 xor chain test mode description the intel ? ich6 supports xor chain test mode. this n on-functional test mode is a dedicated test mode when the chip is not operating in its normal manner. the xor chain mode is entered as indicated in the following figure: figure 24-1. xor chain test mode selection, entry and testing req# settings xor chain req[4:1]# = 0000 xor 1 req[4:1]# = 0001 xor 2 req[4:1]# = 0010 xor 3 req[4:1]# = 0011 xor 4 req[4:1]# = 0100 xor 5 pciclk rsmrst# / lan_rst# rtcrst# pwrok chain select (1-5) req[4:1]# acz_sdout / ee_dout xor chain test mode selection, entry and testing notes: rsmrst#, pwrok, rtcrst#, lan_rst# must be held high during test mode and output testing. pciclk & dmi_clk should be approximately 1 mhz while running/toggling tp3 / gpio25 dmi_clk 5ms 10ms run 120 ms run 2 ms dmi_clkp = ?0? dmi_clkn = ?1? toggle held low xor output enabled chain 4 combination option: see note on chain 4 option if lan_rst# = 0 during testing (xor output enabled) then chains 4-1 and 4-2 are separate. if lan_rst# = 1 during testing then chains 4-1 and 4-2 are combined with output on pltrst#. lan_rst# must be high for all other chains for chains 4 and 5, all petx[n] signals (of that chain) must be driven during testing.
780 intel ? i/o controller hub 6 (i ch6) family datasheet testability 24.1.1 xor chain testability algorithm example xor chain testing allows motherboard manuf acturers to check component connectivity (e.g., opens and shorts to vcc or gnd). an example algorithm to do this is shown in table 24-1 . in this example, vector 1 applies all 0?s to the chain inputs. the outputs being non-inverting will consistently produce a 1 at the xor output on a good board. one short to vcc (or open floating to vcc) will result in a 0 at th e chain output, signaling a defect. likewise, applying vector 7 (all 1?s) to the chain inputs (given that ther e are an even number of input signals in the chain), will consistently produce a 1 at the xor chain output on a good board. one short to vss (or open floating to vss) will result in a 0 at the chain output, signaling a defect. it is important to note that the number of inputs pulled to 1 will affect the expected chain output value. if the number of chain inputs pulled to 1 is even, then expect 1 at th e output. if the number of chain inputs pulled to 1 is odd, expect 0 at the output. continuing with the example in table 24-1 , as the input pins are driv en to 1 across the chain in sequence, the xor output will toggle between 0 and 1. any break in the toggling sequence (e.g., ?1011?) will identify the location of the short or open. figure 24-2. example xor chain circuitry input pin 2 vcc input pin 1 input pin 3 input pin 4 input pin 5 input pin 6 xor chain output table 24-1. xor test pattern example vector input pin 1 input pin 2 input pin 3 input pin 4 input pin 5 input pin 6 xor output 1000000 1 2100000 0 3110000 1 4111000 0 5111100 1 6111110 0 7111111 1
intel ? i/o controller hub 6 (ich6) family datasheet 781 testability 24.2 xor chain tables table 24-2. xor chain #1 (req[4:1]# = 0000) pin name ball # notes pin name ball # notes acz_sync b9 top of xor chain serr# g5 30 th signal in xor acz_bit_clk c10 2nd signal in xor ad[4] f3 acz_sdout c9 ad[6] f2 req[3]# b8 c/be[1]# h6 gnt[3]# c8 ad[20] g3 req[6]#/gpi[0] b7 gnt[2]# f1 pirq[f]#/gpi[3] c7 c/be[0]# j6 gnt[6]#/gpo[16] d8 ad[15] j5 gnt[1]# b6 ad[13] h3 req[1]# b5 ad[22] h2 pirq[g]#/gpi[4] c6 frame# j3 req[5]#/gpi[1] e8 trdy# j2 ad[10] a2 stop# j1 pirq[e]#/gpi[2] d9 ad[28] k3 gnt[4]#/gpo[48] e7 req[0]# l5 ad[24] b3 ad[16] k2 ad[26] b2 pirq[d]# l3 ad[1] e5 pirq[b]# l2 ad[9] d3 ad[30] l1 gnt[5]#/gpo[17] f6 req[2]# m5 ad[5] e9 pirq[h]#/gpi[5] m3 ad[18] d4 pirq[c]# m1 req[4]#/gpi[40] f7 pirq[a]# n2 ad[2] c2 pltrst# r5 ad[3] f5 acz_sdin[0] f11 gnt[0]# c1 acz_rst# a10 ad[11] d2 acz_sdin[2] b10 par e1 acz_sdin[1] f10 ad[0] e2 batlow#/tp[0] v2 xor chain #1 output
782 intel ? i/o controller hub 6 (i ch6) family datasheet testability table 24-3. xor chain #2 (req[4:1]# = 0001) pin name ball # notes pin name ball # notes ad[29] a5 top of xor chain gpi[8] r1 27th signal in xor irdy# a3 2nd signal in xor ri# t2 ad[14] b4 pwrbtn# u1 ad[7] d6 tp[3] u3 plock# c5 batlow#/tp[0] v2 ad[12] d5 satarbias# ag11 ad[8] e6 satarbias af11 devsel# c3 sata[0]rxn ae3 perr# e3 sata[0]rxp ad3 pciclk g6 sata[0]txn ag2 c/be[2]# g4 sata[0]txp af2 ad[23] h5 sata[1]rxn/ reserved ac5 ad[21] h4 sata[1]rxp/ reserved ad5 c/be[3]# g2 sata[1]txn/ reserved af4 ad[27] k6 sata[1]txp/ reserved ag4 ad[17] k5 bmbusy#/ gpi[6] ad19 ad[31] k4 sata[1]gp/ gpi[29] ae18 ad[19] l6 gpi[7] ae19 ad[25] m6 sata[0]gp/ gpi[26] af17 lad[0]/fwh[0] p2 clkrun#/ gpio[32] af19 lad[1]/fwh[1] n3 gpio[33] af20 lad[2]/fwh[2] n5 gpio[34] ac18 lad[3]/fwh[3] n4 gpo[21] ad20 ldrq[0]# n6 thrm# ac20 lframe#/ fwh[4] p3 mch_sync# ag21 ldrq[1]#/gpi[41] p4 req[6]#/gpi[0] b7 xor chain #2 output
intel ? i/o controller hub 6 (ich6) family datasheet 783 testability table 24-4. xor chain #3 (req[4:1]# = 0010) pin name ball # notes pin name ball # notes intruder# aa3 top of xor chain da[0] ac16 25th signal in xor intvrmen aa5 2nd signal in xor dcs3# ae17 dd[6] ad11 ideirq ab16 dd[10] ab12 da[2] ac17 dd[3] ad12 da[1] ab17 dd[7] ab11 dprslpvr/ tp[1] ae20 dd[12] ac13 vrmpwrgd af21 dd[8] ae13 init3_3v# ae22 dd[15] ad13 gpo[23] ad21 dd[5] ac11 gpo[19] ab21 dd[9] af13 stp_pci#/ gpo[18] ac21 dd[4] ae14 stp_cpu#/ gpo[20] ad22 dd[0] ad14 a20gate af22 diow# ac14 rcin# ad23 dd[2] af14 a20m# af23 dd[14] ag15 intr ag24 ddack# ab15 dprstp#/tp[4] ae24 dd[11] ab13 cpupwrgd/ gpo[49] ag25 dd[13] ae15 nmi af25 ddreq ab14 init# af27 dd[1] af15 cpuslp# ae27 iordy af16 stpclk# ae26 dior# ae16 thrmtrip# ae23 dcs1# ad16 dpslp#/tp[2] ad27 ri# t2 xor chain #3 output
784 intel ? i/o controller hub 6 (i ch6) family datasheet testability 2 table 24-5. xor chain #4-1 (req[4:1]# = 0011) pin name ball # notes pin name ball # notes dmi[3]rxn ab24 top of xor chain oc[4]#/gpi[9] c23 22nd signal in xor dmi[3]rxp ab23 2nd signal in xor oc[7]#/gpi[15] c24 dmi[3]txp aa26 oc[6]#/gpi[14] c25 dmi[3]txn aa27 clk48 a27 dmi[2]rxn y25 usbp[0]n c21 dmi[2]rxp y24 usbp[0]p d21 dmi[2]txp w26 usbp[1]n a20 dmi[2]txn w27 usbp[1]p b20 pern[4] p24 usbp[2]n d19 perp[4] p23 usbp[2]p c19 petp[4] n26 usbp[3]n a18 petn[4] n27 usbp[3]p b18 pern[3] m25 usbp[4]n e17 perp[3] m24 usbp[4]p d17 petp[3] l26 usbp[5]n b16 petn[3] l27 usbp[5]p a16 oc[0]# c27 usbp[6]n c15 oc[2]# b26 usbp[6]p d15 oc[1]# b27 usbp[7]n a14 oc[5]#/gpi[10] d23 usbp[7]p b14 oc[3]# c26 gpi[8] r1 xor chain #4-1 output
intel ? i/o controller hub 6 (ich6) family datasheet 785 testability 2 2 2 table 24-6. xor chain #4-2 (req[4:1]# = 0011) pin name ball # notes pin name ball # notes lan_rxd[2] c13 top of xor chain smlink[1] u6 26th signal in xor ee_shclk b12 2nd signal in xor sys_reset# u2 lan_txd[0] c12 gpio[24] v3 lan_txd[2] e13 susclk v6 ee_cs d12 sus_stat#/ lpcpd# w3 lan_rstsync b11 smlink[0] w4 ee_din f13 smbdata w5 lan_rxd[0] e12 smbclk y4 lan_txd[1] c11 smbalert#/ gpi[11] w6 ee_dout d11 linkalert# y5 lan_rxd[1] e11 sata[2]rxn ad7 lan_clk f12 sata[2]rxp ac7 clk14 e10 sata[2]txn af6 spkr f8 sata[2]txp ag6 gpi[12] m2 sata[3]rxn/ reserved ac9 gpio[25] p5 sata[3]rxp/ reserved ad9 pme# p6 sata[3]txn/ reserved af8 pcirst# r2 sata[3]txp/ reserved ag8 gpio[27] r3 sata[3]gp/ gpi[31] ag18 gpi[13] r6 sataled# ac19 gpio[28] t3 sata[2]gp/ gpi[30] af18 slp_s5# t6 serirq ab20 slp_s4# t5 ferr# af24 slp_s3# t4 smi# ag27 wake# u5 ignne# ag26 pltrst# r5 xor chain #4-2 output
786 intel ? i/o controller hub 6 (i ch6) family datasheet testability table 24-7. xor chain #5 (req[4:1]# = 0100) pin name ball # notes pin name ball # notes dmi[1]rxn v25 top of xor chain pern[2] k25 9th signal in xor dmi[1]rxp v24 2nd signal in xor perp[2] k24 dmi[1]txp u26 petp[2] j26 dmi[1]txn u27 petn[2] j27 dmi[0]rxn t25 pern[1] h25 dmi[0]rxp t24 perp[1] h24 dmi[0]txp r26 petp[1] g26 dmi[0]txn r27 petn[1] g27 req[6]#/gpi[0] b7 xor chain #5 output

▲Up To Search▲

Price & Availability of 82801FR

	To Download 82801FR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .